Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/25/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election with traverse of claims 1-15 in the reply filed on 10/22/2025 is acknowledged.
Response to Arguments
Applicant’s argument has been fully considered but found not persuasive.
As indicated in the restriction requirement:
I. Claim 1-15, drawn to a method for manufacturing a flash memory device, CPC H10D30/6891
II. Claim 16-20, drawn to a flash memory device, CPC H10B41/30.
The inventions are distinct, each from the other because of the following reasons: the invention II can be made by another and materially different process. Instead of performing two separate annealing processes with a chlorine etching process in between the device can be made by performing one annealing process after a fluorine etching process (SF6 or CF2).
“Serious burden” is a technical term specifically defined in the MPEP. For purposes of the initial requirement, appropriate explanation of separate classification, or separate status in the art, or a different field of search as defined in MPEP § 808.02 may prima facie show a serious burden on the examiner. See MPEP § 803 part II. That prima facie showing may be rebutted by appropriate showings or evidence by the applicant. In the case at hand, the examiner showed, prima facie, a “serious burden,” by an appropriate explanation of mutually exclusive characteristics of independent or distinct invention and the two inventions belong to different class. It is necessary to search for one of the inventions in a manner that is not likely to result in finding art pertinent to the other invention(s) (e.g., searching different classes/subclasses or electronic resources, or employing different search queries); hence, a different field of search is required as the search must in fact be pertinent to the type of subject matter covered by the claims.
The requirement is still deemed proper and is therefore made FINAL. Applicant timely traversed the restriction (election) requirement in the reply filed on 10/22/2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 7-12 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. US 2022/0181339 in view of Yu et al. US 2019/0371914 and Van Aerde et al. US 2016/0020093.
Re claim 1, Wu teaches a method for manufacturing a flash memory device (fig1C-1G), comprising:
forming a plurality of isolation structures (112, 114, fig1E, [18, 23]) in a substrate (102, fig1E, [18]), wherein an opening (115, fig1E, [25]) is formed between adjacent two of the isolation structures, wherein a top width (W2, fig1E, [36]) of the opening is less than a bottom width of the opening (W3, fig1E, [36]);
Wu teaches fill opening with polysilicon layer (122, fig1F, [26]) and completely fill the opening (fig1F).
Wu does not explicitly show conformally depositing a first silicon seed layer on the substrate and the isolation structures; performing a first cycle, wherein the first cycle comprises: performing a first deposition process to conformally form a first amorphous silicon layer on the first silicon seed layer, wherein a first recess is defined by the first amorphous silicon layer; and after the first deposition process, performing a first in-situ chlorine etching process to widen a caliber of the first recess; performing a first thermal annealing process to transform the first amorphous silicon layer into a first polysilicon layer; and performing an amorphous silicon deposition process to form an amorphous silicon layer on the first polysilicon layer.
Yu teaches conformally depositing a first silicon seed layer (204, fig4A, [12]) on the substrate (270, fig4, [12]) and the isolation structures (248, fig4, [13]);
performing a first cycle (152 and 154, fig2, [18, 25]), wherein the first cycle comprises:
performing a first deposition process (206, fig5, [18]) to conformally form a first amorphous silicon layer (a-Si 206, fig5, [18]) on the first silicon seed layer (204, fig4A, [12]), wherein a first recess (form 208 with Cl2, fig6, [24, 25]) is defined by the first amorphous silicon layer; and
after the first deposition process, performing a first in-situ chlorine etching process to widen a caliber of the first recess (halogen treatment etch 206, fig6, [26]);
performing a first thermal annealing process ([27]); and
performing an amorphous silicon deposition process (156, fig2, [29]) to form an amorphous silicon layer (206 deposited in process 156, fig7, [29]) on the first polysilicon layer (206 deposited in process 152, fig6, [18]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu and Yu to use the process of Yu in fig2 to form 122 of Wu. The motivation to do so is to avoid formation of voids or seams in the film in the trench (Yu, [8]).
Wu in view of Yu does not explicitly show performing a first thermal annealing process to transform the first amorphous silicon layer into a first polysilicon layer.
Van Aerde teaches a first thermal annealing process ([32]) to transform the first amorphous silicon layer into a first polysilicon layer ([15]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Wu, Yu and Van Aerde to add in an anneal process after treatment of the deposited amorphous Si layer. The motivation to do so is to avoid formation of voids or seams in the film in the trench (Van Aerde, [15]) and remove any physisorbed residual gas used in the treatment process.
Re claim 3, Wu modified above teaches the method as claimed in claim 1, further comprising: after performing the first thermal annealing process (anneal after Yu fig6) and before performing the amorphous silicon deposition process (Yu, 206, fig11), performing an acid etching process (treatment with HCL, fig12, [25, 34]); after the acid etching process (Yu, fig12), conformally depositing a second silicon seed layer (Yu, 206, fig13) on the first polysilicon layer (Yu, 206 with added anneal process after treatment 208, fig6, [18]); after the amorphous silicon layer completely filling the opening (Yu, 206, fig14A), performing a second thermal annealing process to transform the amorphous silicon layer into a second polysilicon layer (added anneal process to crystalize a-Si to avoid voids and remove residual gas during treatment process); and performing a planarization process to level a top surface of the second polysilicon layer with a top surface of the isolation structures (Wu, CMP, fig1F, [26]).
Re claim 4, Wu modified above teaches the method as claimed in claim 1, wherein before the first thermal annealing process, a smallest caliber of the first recess is greater than or equal to 5 nm (Wu, W2 greater than H3 ~15-40nm, fig1E and 4, [36, 51]).
Re claim 7, Wu modified above teaches the method as claimed in claim 1, wherein during each of the first in-situ chlorine etching process, an etching amount of the first amorphous silicon layer at a top of the first recess is greater than an etching amount of the first amorphous silicon layer at a bottom of the first recess (Yu, fig6, [26]).
Re claim 8, Wu modified above teaches the method as claimed in claim 1, wherein during each of the first cycle, a deposition thickness of the first amorphous silicon layer at a bottom of the first recess is greater than an etching thickness of the first amorphous silicon layer at the bottom of the first recess (Yu, 206, fig6-14).
Re claim 9, Wu modified above teaches the method as claimed in claim 1, further comprising: before performing the amorphous silicon deposition process (Yu, 206, fig13-14), performing a second cycle (Yu, 206, fig11-12), wherein the second cycle comprises: performing a second deposition process to conformally form a second amorphous silicon layer (Yu, 206, fig11) on the first polysilicon layer (Yu, 206, fig5), wherein a second recess is defined by the second amorphous silicon layer (Yu, recess 253 in 206, fig11); and after the second deposition process, performing a second in-situ chlorine etching process to widen a caliber of the second recess (Yu, fig12).
Re claim 10, Wu modified above teaches the method as claimed in claim 9, wherein the first cycle is repeated x times and the second cycle is repeated y times, wherein y is less than or equal to x (Yu, fig5-14).
Re claim 11, Wu modified above teaches the method as claimed in claim 9, further comprising: after performing the first thermal annealing process (Yu, anneal in fig6 after treatment) and before performing the amorphous silicon deposition process (Yu, 206, fig14), performing an acid etching process (Yu, fig12); after the acid etching process (Yu, fig12), conformally depositing a second silicon seed layer (Yu, 206, fig13) on the first polysilicon layer; after the amorphous silicon layer completely filling the opening (Yu, 206, fig14A), performing a second thermal annealing process (Van Aerde anneal process to reduce voide, [15]) to transform the second amorphous silicon layer and the amorphous silicon layer into a second polysilicon layer; and performing a planarization process to level a top surface of the second polysilicon layer with a top surface of the isolation structures (Wu, CMP, fig1F, [26).
Re claim 12, Wu modified above teaches the method as claimed in claim 9, wherein before each of the second in-situ chlorine etching process, a smallest caliber of the second recess is 5-10 nm (Wu, W2 greater than H3 ~15-40nm and fill from bottom up, fig1E and 4, [36, 51]).
Re claim 14, Wu modified above teaches the method as claimed in claim 1, wherein the first cycle is repeated x times, and wherein x is an integer between 2 and 5 (Yu, fig5-14A).
Re claim 15, Wu modified above teaches the method as claimed in claim 1, wherein a temperature of the first thermal annealing process is between 700℃ and 1000℃ (Van Aerde, 700-800C, [32]).
Allowable Subject Matter
Claims 2, 5-6 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
Specifically, the limitations are material to the inventive concept of the application in hand to have avoid pinch off during trench filling process and avoid the formation of pits between polysilicon and isolation structure.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812