DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 6, 8, 10 and 11 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6, 8, 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (Tsai) (US 2022/0359369 A1) in view of in view of Chung et al. (Chung) (US 9,984,983 B2).
.In regards to claim 1, Tsai (Figs. 31A-31C and associated text) discloses a device (Figs. 31A-31C) comprising: a device layer (items 106 plus 109 plus 125) comprising a first transistor (item 109); a first interconnect structure (item 120) on a front-side of the device layer (items 106 plus 109 plus 125); and a second interconnect structure (item 140) on a backside of the device layer (items 106 plus 109 plus 125), the second interconnect structure item 140) comprising a power rail (item 132, paragraph 92); a semiconductor substrate (item 170) indirectly bonded to the first interconnect structure (item 120), but does not specifically disclose a first heat dissipation layer physically contacting a sidewall of a semiconductor material of the semiconductor substrate.
Chung (Figs. 1A, 2, 3 and associated text) discloses wherein the first heat dissipation layer (items 18 plus 20 or item 24 of 20) physically contacting a sidewall of a material of a substrate (item 10, Chung).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chung for the purpose of improving heat dissipation and EMI shielding (col. 7, lines 30-34).
In regards to claim 2, Tsai as modified by Chung does not specifically disclose wherein the first heat dissipation layer has a thermal conductivity in a range of 10 W/m.Math.K to 1500 W/m.Math.K.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a first heat dissipation layer having a thermal conductivity in a range of 10 W/m.Math.K to 1500 W/m.Math.K for the purpose heat dissipation, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 3, Tsai as modified by Chung does not specifically disclose wherein the first heat dissipation layer comprises AlN, BN, Y.sub.2O.sub.2, Y.sub.3A.sub.15O.sub.12 (YAG), AL.sub.2O.sub.2, BeO, SiC, graphene, diamond-like-carbon (DLC), or diamond.
It would have been obvious to modify the invention to include a first heat dissipation layer comprising AlN, BN, Y.sub.2O.sub.2, Y.sub.3A.sub.15O.sub.12 (YAG), AL.sub.2O.sub.2, BeO, SiC, graphene, diamond-like-carbon (DLC), or diamond for the purpose of heat dissipation, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 6, Tsai (Figs. 31A-31C and associated text) discloses wherein the first heat dissipation layer (item 160) is further disposed on an opposing side of the carrier substrate (item 170) as the first interconnect structure (item 120).
In regards to claim 8, (Fig. 1A and associated text) discloses heat dissipation (items 18 plus 20 or item 24 of 20) covers the top and side surfaces of the entire package (item 1a), therefore Tsai (Figs. 29A-31C and associated text) as modified by Chung (Fig. 1A and associated text) discloses wherein the first heat dissipation layer (items 18 plus 20 or item 24 of 20, Chung) is disposed on a sidewall of first interconnect structure (item 120, Tsai), the device layer (items 106 plus 109 plus 125, Tsai), and the second interconnect structure (item 140, Tsai).
In regards to claim 10, Tsai (Figs. 29A-31C and associated text) discloses a device comprising: a first transistor structure (item 109) and a second transistor structure (item 109) in device layer (items 106 plus 109 plus 125); a front-side interconnect structure (items 120 or 140) on a front-side of the device layer (items 106 plus 109 plus 125), the first transistor structure (item 109) being electrically coupled to the second transistor structure (item 109) through the front-side interconnect structure (item 120 or 140); a backside interconnect structure (item 140, or 120) on a backside of the device layer (items 106 plus 109 plus 125), the backside interconnect structure (item 140, or 120) comprising a power supply line (item 132 or 122); a semiconductor substrate (item 170) bonded to the front-side interconnect structure (item 140, or 120).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate different teachings and/or configurations other embodiments taught by Tsai for the purpose of have different nano-FET structures, since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japiske, 86 USPQ 70).
Tsai does not specifically disclose a first heat dissipation layer in physical contact with a lateral surface of the semiconductor substrate, wherein the first heat dissipation layer and the semiconductor substrate a (are) co-terminus in a cross-section view.
Chung (Fig. 1A and associated text) discloses a heat dissipation layer (items 20 or 18 plus 20 or item 24 of item 20) in physical contact with a lateral surface of a substrate (item 10), wherein the first heat dissipation layer (items 20 or 18 plus 20 or item 24 of item 20) and the (semiconductor) substrate (item 10) a (are) co-terminus in a cross-section view.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chung for the purpose of improving heat dissipation and EMI shielding (col. 7, lines 30-34).
In regards to claim 11, Tsai as modified by Chung discloses does not specifically disclose wherein the heat dissipation layer comprises diamond-like-carbon (DLC).
It would have been obvious to modify the invention to include a heat dissipation layer comprising diamond-like-carbon (DLC) for the purpose of heat dissipation, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Claim(s) 1-3, 6, 8, 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (Yu) (US 2021/0408247 A1) in view of Chung et al. (Chung) (US 9,984,983 B2).
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In regards to claim 1, Yu (Figs. 29A-29C, 36A-36E and associated text) discloses a device (items 200, 250) comprising: a device layer (items 106 plus 96 plus 115 plus 50 plus 160 plus 162) comprising a first transistor (item 115); a first interconnect structure (item 120) on a front-side of the device layer (items 106 plus 96 plus 115 plus 50 plus 160 plus 162); and a second interconnect structure (item 136 plus 132 plus 134) on a backside of the device layer (items 106 plus 96 plus 115 plus 50 plus 160 plus 162), the second interconnect (item 136 plus 132 plus 134) comprising a power rail (item 134, paragraph 91); a semiconductor substrate (item 150) bonded to the first interconnect structure (item 120), but does not specifically disclose a first heat dissipation layer physically contacting a sidewall of a semiconductor material of the semiconductor substrate.
Chung (Figs. 1A, 2, 3 and associated text) discloses wherein the first heat dissipation layer (items 18 plus 20 or item 24 of 20) physically contacting a sidewall of a material of a substrate (item 10, Chung).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chung for the purpose of improving heat dissipation and EMI shielding (col. 7, lines 30-34).
In regards to claim 2, Yu as modified by Chung does not specifically disclose wherein the first heat dissipation layer has a thermal conductivity in a range of 10 W/m.Math.K to 1500 W/m.Math.K.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a first heat dissipation layer having a thermal conductivity in a range of 10 W/m.Math.K to 1500 W/m.Math.K for the purpose heat dissipation, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 3, Yu as modified by Chung does not specifically disclose wherein the first heat dissipation layer comprises AlN, BN, Y.sub.2O.sub.2, Y.sub.3A.sub.15O.sub.12 (YAG), AL.sub.2O.sub.2, BeO, SiC, graphene, diamond-like-carbon (DLC), or diamond.
It would have been obvious to modify the invention to include a first heat dissipation layer comprising AlN, BN, Y.sub.2O.sub.2, Y.sub.3A.sub.15O.sub.12 (YAG), AL.sub.2O.sub.2, BeO, SiC, graphene, diamond-like-carbon (DLC), or diamond for the purpose of heat dissipation, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 6, Yu (Figs. 29A-29C, 36A-36E and associated text) as modified by Chung (Fig. 1A and associated text) discloses wherein the first heat dissipation layer (items 20 or 18 plus 20, Chung) is further disposed on an opposing side of the carrier substrate (item 150, Yu) as the first interconnect structure (item 120).
In regards to claim 8, Chung (Fig. 1A and associated text) discloses a heat dissipation (items 18 plus 20 or item 24 of 20) covers the top and side surfaces of the entire package (item 1a), therefor Yu (Figs. 29A-29C, 36A-36E and associated text) as modified by Chung (Fig. 1A and associated text) discloses wherein the first heat dissipation layer (items 18 plus 20 or item 24 of 20, Chung) is disposed on a sidewall of first interconnect structure (item 120, Yu), the device layer (items 106 plus 96 plus 115 plus 50 plus 160 plus 162, Yu), and the second interconnect structure (item 136 plus 132 plus 134, Yu).
In regards to claim 10, Yu (Figs. 29A-29C, 36A-36E and associated text) discloses a device comprising: a first transistor structure (item 115) and a second transistor (item 115) in device layer (items 106 plus 96 plus 115 plus 50 plus 160 plus 162); a front-side interconnect structure (items 120) on a front-side of the device layer (items 106 plus 96 plus 115 plus 50 plus 160 plus 162), the first transistor structure (item 115) being electrically coupled to the second transistor structure (item 115) through the front-side interconnect structure (item 120); a backside interconnect structure (item 136 plus 132 plus 134) on a backside of the device layer (items 106 plus 96 plus 115 plus 50 plus 160 plus 162), the backside interconnect structure (item 136 plus 132 plus 134) comprising a power supply line (item 134); a semiconductor substrate (item 150) bonded to the front-side interconnect structure (item 120).
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate different teachings and/or configurations other embodiments taught by Yu for the purpose of have different nano-FET structures, since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japiske, 86 USPQ 70).
Yu does not specifically disclose a first heat dissipation layer in physical contact with a lateral surface of the semiconductor substrate, wherein the first heat dissipation layer and the semiconductor substrate a (are) co-terminus in a cross-section view.
Chung (Fig. 1A and associated text) discloses a heat dissipation layer (items 20 or 18 plus 20 or item 24 of item 20) in physical contact with a lateral surface of a substrate (item 10), wherein the first heat dissipation layer (items 20 or 18 plus 20 or item 24 of item 20) and the (semiconductor) substrate (item 10) a (are) co-terminus in a cross-section view.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chung for the purpose of improving heat dissipation and EMI shielding (col. 7, lines 30-34).
In regards to claim 11, Yu as modified by Chung discloses does not specifically disclose wherein the heat dissipation layer comprises diamond-like-carbon (DLC).
It would have been obvious to modify the invention to include a heat dissipation layer comprising diamond-like-carbon (DLC) for the purpose of heat dissipation, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Allowable Subject Matter
Claims 29-35 are allowed.
Claims 5, 28, 36 and 37 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 August 28, 2026
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