Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Attorney Docket Number: TSMCP802USD
Filling Date: 5/26/23
Priority Date: 11/14/19
Inventor: Yao et al
Examiner: Bilkis Jahan
DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “claim 1 recites, the non-zero distance being directly over the one or more vertically extending segments” and “first sidewall, 2nd sidewall” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1-7 and 8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1, last two lines recites “the non-zero distance being directly over the one or more vertically extending segments”. However, the specification does not recites this feature. The specification recites “the non-zero distance being directly over the horizontally extending segment”.
Claims 2-7 and 8 are depending from claim 1. Therefore, the claims 2-7 and 8 are also rejected under 112 1st rejection.
Inasmuch as understood in light of 112 1st rejections, the art rejections as follows:
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-9 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bode et al (US 2014/0001546 A1).
Regarding claim 1, Bode discloses an integrated chip (Fig. 2), comprising: a substrate 210 (Para. 35); a doped isolation region 220, 222 (Para. 35) disposed within the substrate 210 and comprising a horizontally extending segment 220 and one or more vertically extending segments 222 extending outward from the horizontally extending segment 220; and wherein the substrate 210 comprises a first sidewall and a second sidewall (two sidewalls of 210) separated from the first sidewall a non-zero distance 216, the non-zero distance 216 being directly over the one or more vertically extending segments 222.
Regarding claim 2, Bode discloses the integrated chip of claim 1, further comprising: a conductive material 232 (Para. 36, N-doped) disposed between the first sidewall and the second sidewall, the conductive material 232 being a different material than the substrate 210 (Paras. 24, 35, undoped).
Regarding claim 3, Bode discloses the integrated chip of claim 1, wherein the substrate 210 comprises: a base substrate layer (bottom portion of 210) comprising a first semiconductor material; and a second semiconductor material (top portion of 210, two sides horizontal portions of 222) over a topmost surface of the base substrate layer (210 portion under 220), the first sidewall and the second sidewall being formed at least in part by the second semiconductor material 210 (top portions two sides).
Regarding claim 4, Bode discloses the integrated chip of claim 3, wherein an upper boundary of the one or more vertically extending segments 222 is vertically offset from the topmost surface of the base substrate layer (See figure 2, upper surface covered by 224, so offset to the substrate 210 top surface). 6. The integrated chip of claim 1, wherein the one or more vertically extending segments laterally and continuously extend between the first sidewall and the second sidewall.
Regarding claim 6, Bode discloses the integrated chip of claim 1, wherein the one or more vertically extending segments 22 laterally and continuously extend between the first sidewall 210 (left) and the second sidewall 210 (right).
Regarding claim 7, Bode discloses the integrated chip of claim 1, further comprising: one or more additional isolation regions 250, 252, 254 (Para. 37) arranged along an upper surface of the substrate 210, wherein a top of the doped isolation region 220, 222 is vertically below a bottom of the one or more additional isolation regions 250, 252, 254.
Regarding claim 8, Bode discloses the integrated chip of claim 1, wherein the substrate 210 comprises a first substrate layer 210 (bottom portion under 222) and a second substrate 210 (top portion of 220) layer over a top of the first substrate layer; and wherein a majority of the horizontally extending segment 220 is within the first substrate layer and a majority of the one or more vertically extending segments 222 are within the second substrate layer 210 (top portion, claim does not define how the first and second substrate are different).
Regarding claim 9, Bode discloses an integrated chip (Fig. 2), comprising: a substrate 210 (Paras. 24, 35) comprising a first semiconductor material 210 (bottom portion); a second semiconductor material 232 (Para. 36) over the first semiconductor material 210, wherein the second semiconductor material 232 is a different material than the first semiconductor material 210; an implant isolation region 220 (Para. 35) disposed within the substrate 210; and wherein one or more gaps 250 (Para. 37) extend into the second semiconductor material 232 over the implant isolation region 220, the one or more gaps 250 laterally surrounding parts of the second semiconductor material 232 that are directly above the implant isolation region 220.
Regarding claim 12, Bode discloses the integrated chip of claim 9, wherein the implant isolation region 220 has one or more bumps 222 (Para. 35) disposed along an upper border of the implant isolation region 220.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bode et al (US 2014/0001546 A1) in view of Pendharkar et al (US 6,225,673 B1, Pen hereinafter).
Regarding claim 5, Bode does not explicitly disclose the integrated chip of claim 1, further comprising: a first power switch arranged on or within the substrate directly over the doped isolation region; and a second power switch arranged on or within the substrate laterally outside of the doped isolation region.
However, Pen discloses a first power switch 18 (Fig. 2, col. 2, line 55) arranged on or within the substrate 51 (col. 3, line 60) directly over the doped isolation region 53 (col. 3, lines 56-57); and a second power switch 17 (col. 2, line 55) arranged on or within the substrate 51 laterally outside of the doped isolation region 53.
Pen teaches the above modification is used to obtain less power consumption of the device (col. 1, lines 10-15). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Bode structure with Pen switching structures as suggested above to obtain less power consumption of the device (col. 1, lines 10-15).
Regarding claim 13, Bode does not explicitly disclose the integrated chip of claim 9, wherein the substrate comprises p-type dopants; and wherein the implant isolation region comprises n-type dopants.
However, Pen discloses the substrate 51 comprises p-type dopants; and wherein the implant isolation region 53 comprises n-type dopants (Fig. 2).
Pen teaches the above modification is used to obtain less power consumption of the device (col. 1, lines 10-15). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to substitute Bode substrate conductivity with Pen substrate conductivity as suggested above to obtain less power consumption of the device (col. 1, lines 10-15).
Regarding claim 14, Bode does not explicitly disclose the integrated chip of claim 9, further comprising: a first gate structure disposed over the second semiconductor material and directly over the implant isolation region; and a second gate structure disposed over the second semiconductor material and laterally outside of the implant isolation region.
However, Pen discloses a first gate structure 72 (Fig. 2, col. 4, line 10) disposed over the second semiconductor material 57 (col. 3, line 59) and directly over the implant isolation region 53; and a second gate structure 87 (col. 4, line 28) disposed over the second semiconductor material 57 and laterally outside of the implant isolation region 53.
Pen teaches the above modification is used to obtain less power consumption of the device (col. 1, lines 10-15). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Bode substrate conductivity with Pen gate structures as suggested above to obtain less power consumption of the device (col. 1, lines 10-15).
Claim(s) 15, 18-19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Pendharkar et al (US 6,225,673 B1, Pen hereinafter) in view of Bode et al (US 2014/0001546 A1).
Regarding claim 15, Pen discloses an integrated chip (Fig. 2), comprising: a substrate 51 (col. 3, line 60); a first gate structure 72 (col. 4, line 10) arranged over the substrate 51; a second gate structure 87 (col. 4, line 28) arranged over the substrate 51; an implant isolation region 53 (col. 3, lines 56-57) disposed within the substrate 51 below the first gate structure 72 and laterally outside of the second gate structure 87.
Pen does not explicitly disclose a conductive contact extending though the substrate to electrically contact the implant isolation region.
However, Bode discloses a conductive contact 224 (Fig. 2, Para. 38) extending though the substrate 210 (Para. 35) to electrically contact the implant isolation region 220, 222 (Para. 35). Bode teaches the above modification is used to make external connection of the device (Fig. 2).
It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to combine Pen structure with Bode conductive contact as suggested above to make external connection of the device (Fig. 2).
Regarding claim 18, Pen discloses the integrated chip of claim 15, wherein the implant isolation region 53 (horizontal portion) has one or more protrusions 53 (two vertical portions) vertically extending outward from an upper boundary of the implant isolation region and Bode discloses the conductive contact 224 contacting the one or more protrusions 222.
Regarding claim 19, Bode discloses the integrated chip of claim 18, wherein a bottom of the conductive contact 224 is vertically above the upper boundary (Fig. 2).
Regarding claim 20, Bode discloses the integrated chip of claim 15, wherein the conductive contact 224 physically contacts the implant isolation region 220, 222 at an interface that is vertically offset from an upper surface of the substrate 210 (Fig. 2).
Allowable Subject Matter
Claims 10-11, 16 and 17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
BILKIS . JAHAN
Primary Examiner
Art Unit 2817
/BILKIS JAHAN/Primary Examiner, Art Unit 2817