DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The 12/29/2025 "Reply" elects without traverse and identifies claims 15-34 as being drawn to Species A. The Reply cancels claim 1-14.
The 11/17/2025 restriction requirement is proper, is maintained, and is hereby made final.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 15-18 and 20-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai (US Pub. No. 2017/0062496).
Regarding claim 15, in FIGs. 1-16, Lai discloses a method for forming an image sensor, comprising: forming a first integrated circuit (IC) die (100), comprising: forming a plurality of photodetectors (104, paragraph [0014]) in a first substrate; and forming a plurality of first pixel transistors (106, paragraph [0010]) on the first substrate, individual to and respectively bordering the plurality of photodetectors, wherein the plurality of photodetectors and the plurality of first pixel transistors form a first pixel portion; forming a second IC die (200), comprising: forming a plurality of second pixel transistors (204, paragraph [0013]) on a second substrate, wherein the second pixel transistors form a second pixel portion; bonding the first IC die and the second IC die together (paragraph [0014]) such that the first pixel portion and the second pixel portion are stacked and electrically coupled together to form a pixel; and forming a deep trench isolation (DTI) structure (144, paragraph [0015]) extending through the first substrate and separating the plurality of photodetectors from each other after the bonding.
Regarding claim 16, in FIGs. 1-16, Lai discloses that the forming of the first IC die further comprises: forming an interconnect structure (112, paragraph [0011]) overlying and electrically coupled to the plurality of first pixel transistors, wherein the interconnect structure comprises a plurality of wires and a plurality of vias alternatingly stacked.
Regarding claim 17, in FIGs. 1-16, Lai discloses that the forming of the first IC die comprises repeatedly forming the first pixel portion, and wherein the forming of the second IC die comprises repeatedly forming the second pixel portion (multiple pixels are disclosed).
Regarding claim 18, in FIGs. 1-16, Lai discloses that the bonding comprises bonding conductors respectively of the first and second IC dies together at an interface and bonding dielectric layers respectively of the first and second IC dies together at the interface (paragraph [0012]).
Regarding claim 20, in FIGs. 1-16, Lai discloses that the forming of the DTI structure comprises forming a metal core (142, tungsten, paragraph [0032]) lined by a dielectric liner (140, paragraph [0031]).
Regarding claim 21, in FIGs. 1-16, Lai discloses forming a micro lens (154, paragraph [0035]) overlying the plurality of photodetectors on an opposite side of the first substrate as the second IC die.
Regarding claim 22, in FIGs. 1-16, Lai discloses a method for forming an image sensor, comprising: forming a first semiconductor structure (100), which comprises a pair of photodetectors (2 adjacent 104) in a first substrate; forming a second semiconductor structure (200), which comprises a plurality of pixel transistors (106) on a second substrate; bonding the first semiconductor structure and the second semiconductor structure together (paragraph [0014]), such that the pair of photodetectors and the plurality of pixel transistors form a pixel; forming a trench isolation structure extending completely through the first substrate (“Trench 122 may extend partially into substrate 102 or fully through substrate 102,” paragraph [0019]) and completely separating the pair of photodetectors from each other; and forming a color filter (152, paragraph [0035]) overlying the pair of photodetectors on an opposite side of the first substrate as the second semiconductor structure.
Allowable Subject Matter
Claims 29-34 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 29-34, the prior art failed to disclose or reasonably suggest the claimed method for forming an image sensor particularly characterized by forming a second IC die comprising a plurality of pixel transistors on a second substrate; bonding the second IC die to the first substrate to form a pixel that comprises the plurality of photodetectors, the plurality of transfer transistors, and the plurality of pixel transistors; forming a third IC die comprising a plurality of logic transistors; bonding the third IC die to the second IC die on an opposite side of the second IC die as the first IC die; and forming a trench isolation structure extending through the first substrate after the bonding of the third IC die, wherein the trench isolation structure separates the source/drain regions of the plurality of transfer transistors from each other.
Claims 19 and 23-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 19, the prior art failed to disclose or reasonably suggest the claimed method for forming an image sensor particularly characterized by forming a third IC die, comprising: forming a plurality of logic devices on a third substrate; and forming an interconnect structure overlying and electrically coupled to the logic devices, wherein the logic devices and the interconnect structure form an application-specific integrated circuit (ASIC); and bonding the second IC die and the third IC die together, such that the second IC die is between the first IC die and the third IC die and such that the ASIC is electrically coupled to the pixel.
Regarding claims 23-24, the prior art failed to disclose or reasonably suggest the claimed method for forming an image sensor particularly characterized by performing a first planarization into the second substrate after the bonding and before the forming of the trench isolation structure to reduce a thickness of the second substrate.
Regarding claim 25, the prior art failed to disclose or reasonably suggest the claimed method for forming an image sensor particularly characterized by the first semiconductor structure further comprising a pair of transfer transistors that further form the pixel and that are individual to and respectively border the pair of photodetectors, wherein the pair of photodetectors comprise individual collector regions buried in the first substrate and having a same doping type as individual source/drain regions of the pair of transfer transistors, and wherein the method further comprises: performing a planarization into the first substrate before the forming of the trench isolation structure to expose the pair of collector regions.
Regarding claim 26, the prior art failed to disclose or reasonably suggest the claimed method for forming an image sensor particularly characterized by the pair of photodetectors comprising a first photodetector and a second photodetector having individual top profiles stepping down towards a width-wise center between the first and second photodetectors, and wherein the trench isolation structure is formed extending completely through the first substrate at the width-wise center.
Regarding claims 27-28, the prior art failed to disclose or reasonably suggest the claimed method for forming an image sensor particularly characterized by the first semiconductor structure further comprising a pair of transfer transistors further forming the pixel and individual to and respectively bordering the pair of photodetectors, and wherein the forming of the first semiconductor structure comprises forming a ring-shaped conductive wire overlying and electrically coupled to individual source/drain regions of the pair of transfer transistors.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891