Attorney’s Docket Number: ONS03356D01USUS
Filing Date: 5/26/2023
Claimed Dates: 10/29/2019 (US 16/666,771)
8/13/2019 (US 62/885,882)
Inventors: Lee et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the election filed on 10/13/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis for a rejection as subject to pre-AIA instead will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Species Election
The election filed on 10/13/2025 in reply to the restriction in paper no. 4, mailed on 8/13/2025, has been entered. Applicant’s election without traverse of species 1, reading on figure 1A, is acknowledged. The applicant indicated that claims 1-6 and 8-19 read on the elected species. The examiner agrees. Accordingly, claims 7 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Specification
Claim 19 recites that the side portion has a height of at least 0.05 µm. The specification is objected to as failing to provide proper antecedent basis for this subject matter recited in claim 19. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tomohiro (US 2018/0114845).
Regarding claim 8, Tomohiro (see, e.g., fig. 3) teaches all aspects of the instant invention including a method for fabricating a power semiconductor device, the method comprising:
Etching a trench 7 in a substrate 1 having body 4 and drift 2 regions
Forming a gate dielectric structure 8 including first 8a and second 8b gate insulation layers, and
Providing a conductive material 9 within the trench and over the dielectric structure to make a gate
wherein:
The first insulation layer 8a has a first dielectric constant
The second gate insulation 8b has a second dielectric constant, and
The first constant is different from the second constant
Regarding claim 11, Tomohiro (see, e.g., fig. 3) teaches all aspects of the instant invention including a method comprising:
Forming a body region 4 and a drift layer 2 in a substrate 1
Forming a trench 7 in the substrate
Forming a gate dielectric structure including first 8a and second 8b gate insulation layers, and
Forming a conductive material 9 within the trench and over the dielectric structure
wherein:
The first insulation layer 8a has a first dielectric constant
The second insulation layer 8b has a second dielectric constant, and
The first constant is different from the second constant
Regarding claim 9, Tomohiro teaches that the substrate 1 is a silicon carbide (SiC) substrate (see, e.g., par. 0018/ll.1-3), that the first insulation layer 8a includes silicon oxide (SiO) (see, e.g., par. 0023/ll.1-3), and that the second insulation layer 8b includes silicon nitride (SiN) or aluminum nitride (AlN) (see, e.g., par. 0024/l.6).
Regarding claim 10, Tomohiro teaches that the second gate insulation layer 8b wraps around a bottom corner of the conductive material 9 to reduce electric field buildup at the bottom corner during an operation (see, e.g., par. 0031/ll.1-5).
Regarding claim 16, Tomohiro teaches that the substrate 1 is a SiC substrate, and that the first insulation layer 8a extends below the body region 4 and into the drift layer 2 (see, e.g., fig. 3 and par. 0018/ll.1-3).
Regarding claim 17, Tomohiro teaches that the first insulation layer 8a includes SiO (see, e.g., par. 0023/ll.1-3), that the second constant is greater than the constant of SiO (see, e.g., par. 0024/l.6), and that the second insulation layer 8b is configured to reduce electric field buildup in the trench during operation (see, e.g., par. 0031/ll.1-5).
Regarding claim 18, Tomohiro teaches that the second insulation layer 8b includes lower and side portions that wrap around a bottom corner of the conductive material 9, wherein the side portion is configured to reduce the electric field buildup at the bottom corner during the device operation (see, e.g., par. 0031/ll.1-5 and fig. 3).
Regarding claim 12, Tomohiro teaches that the substrate 1 is a SiC substrate, that the first insulation layer 8a is over a sidewall of the trench 7, and that the second insulation layer 8b is over a bottom of the trench (see, e.g., fig. 3 and par. 0018/ll.1-3).
Regarding claim 13, Tomohiro teaches that the first insulation layer 8a is SiO (see, e.g., par. 0023/ll.1-3), and that the second constant is higher than the constant of SiO (see, e.g., par. 0024/l.6).
Regarding claim 14, Tomohiro teaches that the second insulation layer includes SiN (see, e.g., par. 0024/l.6).
Regarding claim 15, Tomohiro teaches that the second insulation layer includes AlN (see, e.g., par. 0024/l.6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Takaya (US 2018/0175149) in view of Saito (US 2011/0260243).
Regarding claim 1, Takaya (see, e.g., fig. 18 and par. 0062/ll.8-17) shows most aspects of the instant invention including a method for fabricating a power semiconductor device, the method comprising:
Etching a trench 34 in a substrate 12 having a body region 26 and a drift layer 28
Depositing a first dielectric material 38b over the substrate and into the trench, the first material having a first dielectric constant
Etching the first material 38b to expose a sidewall of the trench and provide the first material with a first thickness
Forming a second dielectric material 38a over the sidewalls of the trench, the second material having a second dielectric constant, and
Providing a conductive material 40 within the trench and over the first and second dielectric materials to form a gate
wherein the first and second materials define a gate dielectric structure 38 for the gate.
Takaya, however, fails to teach that the first and second constants are different. Saito, on the other hand, teaches using different constants to reduce the on-resistance while maintaining the high speed of the gate at switching, reducing delay time and driving losses (see, e.g., par. 0029 and 0056).
Accordingly, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have the dielectric materials of Takaya have the first and second constants of Saito to reduce the on-resistance and delay time.
Regarding claim 2, Takaya teaches that the substrate 12 is a SiC substrate (see, e.g., par. 0040/l.2); Saito teaches etching the first material 77 to reduce the first material to a second thickness (see, e.g., fig. 4A).
Regarding claim 3, Saito (see, e.g., fig. 3) shows that the first material 77 includes lower and side portions that wrap a bottom corner of the conductive material 9.
Regarding claim 4, Saito (see, e.g., par. 0030) teaches that the first constant is at least 4, and the second material 8 is SiO.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Takaya/Saito in view of Tomohiro.
Regarding claims 5 and 6, Saito fails to teach that the first material 77 includes SiN or AlN. Tomohiro (see, e.g., par. 0024/l.6), in a similar device to Takaya and Saito, teaches that SiN and AlN are equivalents in the art for the first material of Saito. Saito (see, e.g., fig. 4A) and Tomohiro (see, e.g., fig. 3), both show that the first material is a portion of the gate dielectric of the transistor.
Therefore, it would have been obvious at the time of the invention to one of ordinary skill in the art to use either SiN or AlN for the first material of Saito because these were recognized as equivalents in the semiconductor art for their use as gate dielectric materials, as taught by Tomohiro, and selecting among known equivalents for their intended use would be within the level of ordinary skill in the art.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tomohiro in view of Saito.
Tomohiro discloses a semiconductor device including a second gate insulation layer 8b having a side portion adjacent to a gate electrode 9 (see, e.g., fig. 3). While Tomohiro does not explicitly disclose a numerical height of the side portion, Tomohiro nonetheless teaches the presence of the claimed side portion.
Saito discloses a semiconductor device having a second gate insulation layer 77 with a side portion and teaches that the height of the side portion affects gate-to-source capacitance, thereby influencing device operating speed (see, e.g., fig. 4A, and pars. 0029 and 0056). Saito thus teaches that the height of the side portion is a result-effective variable that may be adjusted to achieve desired electrical performance.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Tomohiro to select an appropriate height for the side portion, as taught by Saito, in order to control gate-to-source capacitance and improve device speed. Such optimization would have involved routine experimentation and design choice.
The claimed limitation that the height of the side portion is at least 0.05 microns represents an obvious selection from a range of suitable values for a known result-effective variable, absent evidence of criticality or unexpected results associated with the claimed threshold.
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
January 20, 2026