DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/14/2026 has been entered.
Claim Objections
Claims 21 and 23 are objected to because of the following informalities:
Claim 21 recites “the intermediate dielectric layer” that lacks antecedent basis in the claims 21 and 20, and should be replaced with “the silicon oxide layer or the silicon nitride layer”.
Claim 23 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 7. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 21 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 21 recites “the intermediate dielectric layer is in physical contact with each of the conductive layer and the semiconductor material” (the intermediate dielectric layer is interpreted as “the silicon oxide layer or the silicon nitride layer”). However, claim 20 recites “the silicon oxide layer or the silicon nitride layer has a first surface in direct contact with the conductive laver and a second surface opposite the first surface in direct contact with the semiconductor material”. Thus, claim 21 fails to further limit the subject matter of the claim upon which it depends.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0342618 to Chen et al. (hereinafter Chen’618) in view of Chan (US 2012/0199887) (the reference US 2011/0073951 by Chatty, the reference US 2016/0351402 by Suzuki, and the reference US 2004/0060812 by Chen are presented as evidence).
With respect to claim 20, Chen’618 discloses a semiconductor structure (e.g., NMOS transistor structure 100) (Chen’618, Fig. 4, ¶0003-¶0004, ¶0015-¶0020) comprising:
a conductive layer (24, gate electrode including tungsten material) (Chen’618, Fig. 4, ¶0016);
either a silicon oxide layer or a silicon nitride layer (e.g., 22, U-shaped gate dielectric layer including silicon oxide material or silicon nitride material) (Chen’618, Fig. 4, ¶0016) in direct contact with the conductive layer (24), wherein the conductive layer (24) at least partially extends into the silicon oxide layer or the silicon nitride layer (e.g., 22); and
a semiconductor material (e.g., semiconductor substrate 10 having doped source/drain regions 14 comprising a p-type dopant) (Chen’618, Fig. 4, ¶0015, ¶0016) having an incorporated dopant, wherein the silicon oxide layer or the silicon nitride layer (e.g., 22) is disposed between the conductive layer (24) and the semiconductor material (10) having the incorporated dopant, and wherein the silicon oxide layer or the silicon nitride layer (e.g., 22) has a first surface in direct contact with the conductive laver (24) and a second surface opposite the first surface in direct contact with the semiconductor material (10).
Further, Chen’618 does not specifically disclose a conductive layer characterized by a first tensile stress less than or about 1 MPa.
However, Chan teaches forming nFET transistor (Chan, Figs. 2, 4, ¶0041-¶0044) comprising a low stress or stress-free metal gate including TiN in the metal gate region and forming a tungsten layer on the TiN layer for the gate structure (204) characterized by a first stress including a low stress or stress neutral tungsten, to improve the electron mobility of the channel region (210), and to improve performance of the NMOS transistor.
It is well-known in the art (e.g., Chatty (¶0009-¶0011) that the stress is a measure of the average amount of force exerted per unit area. The neutral or slightly tensile stress refers to a stress magnitude between 0 MPa and 200 MPa, as evidenced by Chatty (¶0011).
Further, a low stress in a conductive material (e.g., a tungsten film 305) (as evidence by Suzuki, Figs. 7-8, 10, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) refers to a stress magnitude of about 148.5 Pa or less than about 300 MPa (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
The claimed range less than 1 MPa overlaps or lies inside the prior art ranges of Chatty (e.g., between 0 MPa and 200 MPa), and Suzuki (e.g., 148.5 Pa or less than about 300 MPa) (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
Further, Suzuki teaches that a stress in the conductive layer (e.g., tungsten film) (Suzuki, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) depends on a thickness of the conductive layer, a method of forming, and a stress reduction process, to provide the conductive layer that is stressed as little as possible, to prevent bending of the semiconductor device.
Further, Chen teaches forming a conductive layer (Chen, Fig. 6, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037) with controlled intrinsic stress to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device, wherein the film stress (tensile or compressive) in the conductive layer is controlled by applying a bias power to the substrate during the deposition (Chen, Fig. 6, ¶0024). Specifically, the stress in the deposited copper layer (Chen, Fig. 6, ¶0037) is tensile (e.g., less than 20 MPa, as shown in Fig. 6) at the bias power below about 200 watts.
Thus, Suzuki recognizes that a method of forming and a thickness of the conductive layer impact the stress of the conductive layer. Further, Chen recognizes that a method of forming the conductive layer impacts a magnitude of the stress of the conductive layer. Thus, the method of forming and the thickness of the conductive layer are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a method of forming and a thickness of the conductive layer as Suzuki and Chen have identified a method of forming and a thickness of the conductive layer as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific slightly tensile stress in the conducive layer less than or about 1 MPa, in order to provide conductive layer with reduced stress to prevent bending of the semiconductor device as taught by Suzuki (¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device as taught by Chen (¶0002, ¶0008, ¶0010, ¶0024, ¶0037) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chen’618 by forming low stress or stress-free metal gate including a conductive layer of TiN layer and tungsten layer on the TiN layer as taught by Chan, and optimizing the thickness and method of forming of the conductive layer (as evidenced by Suzuki and Chen) to provide the lowly stressed conductive layer having a specific stress magnitude to have the semiconductor structure, comprising a conductive layer characterized by a first tensile stress less than or about 1 MPa, to provide conductive layer with reduced stress to prevent bending of the semiconductor device; and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device (Chan, ¶0002-¶0006, ¶0041, ¶0044; Suzuki, ¶0009-¶0010, ¶0127, ¶0129; Chen, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037).
Regarding claim 21, Chen’618 in view of Chan discloses the semiconductor structure of claim 20. Further, Chen’618 discloses the semiconductor structure, wherein the intermediate dielectric layer (22) (Chen’618, Fig. 4, ¶0015, ¶0016) is in physical contact with each of the conductive layer (24) and the semiconductor material (10) having the incorporated dopant.
Allowable Subject Matter
Claims 1, 3-10, 12-17, and 22 are allowed.
Reasons for Allowance
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest forming a semiconductor structure comprising a conductive layer characterized by a first tensile stress less than 1 MPa and an intermediate dielectric layer characterized by a second tensile stress at least ten times the first tensile stress, wherein the intermediate dielectric layer defines a contact trench including the conductive layer, and is disposed between and in direct contact with each of the conductive layer and a doped semiconductor material, in combinations with other claim limitations as required by claim 1.
The search of the prior art does not disclose or reasonably suggest forming a semiconductor structure comprising a conductive layer characterized by a first tensile stress less than 1 MPa and an intermediate dielectric layer characterized by a second tensile stress at least fifteen times the first tensile stress, wherein the intermediate dielectric layer defines a contact trench including the conductive layer, and in direct contact with each of the conductive layer and a substrate, in combinations with other claim limitations as required by claim 10.
The dependent claims 3-9, 12-17, and 22 are allowable by virtue of the dependence upon the claims 1 and 10.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 05/14/2026 have been fully considered but they are not persuasive.
In response to Applicant’s argument regarding claim 1 that “[t]he cited references do not teach or suggest, as recited in amended independent claim 20, that the intermediate dielectric layer is either a silicon oxide layer or a silicon nitride layer”, the examiner submits that prior at by chen’618 teaches that the intermediate dielectric layer (22) (Chen’618, Fig. 4, ¶0016) is either a silicon oxide layer or a silicon nitride layer. Thus, the above Applicant’s argument is not persuasive, and the rejection of claim 20 under 35 USC 103 over Chen’618 in view of Chan is maintained.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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