DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 11/12/2025.
Applicant’s amendments filed 11/12/2025 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 20-21 and the addition of new claim 22.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-10, 12-18, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2009/0017640 to Huh et al. (hereinafter Huh) in view of Chan et al. (US 2012/0199887, hereinafter Chan) (the reference US 2011/0073951 by Chatty, the reference US 2016/0351402 by Suzuki, and the reference US 2004/0060812 by Chen are presented as evidence).
With respect to claim 1, Huh discloses a semiconductor structure (e.g., NMOS transistor structure 100) (Huh, Fig. 6F, ¶0008-¶0009, ¶0019, ¶0029-¶0030, ¶0034, ¶0038, ¶0041-¶0054) comprising:
a conductive layer (132, tungsten plug) (Huh, Fig. 6F, ¶0050, ¶0054);
an intermediate dielectric layer (e.g., 120/122/124/134, including silicon nitride material and boron-containing film 122 has a tensile stress greater than 2 GPa) (Huh, Fig. 6F, ¶0019, ¶0045, ¶0047, ¶0051) in contact with the conductive layer (132), wherein the intermediate dielectric layer (120/122/124/134) is characterized by a second tensile stress (e.g., boron-containing film 122 has a tensile stress greater than 2 GPa) (Huh, Fig. 6F, ¶0019), and wherein the intermediate dielectric laver (120/122/124) defines one or more contact trenches (e.g., a contact via 128) (Huh, Fig. 6F, ¶0048-¶0050, ¶0054) with the conductive laver (132) being deposited within the one or more contact trenches (128); and
a semiconductor material (e.g., p-type well 118 of the n-type NMOS transistor has a p-type dopant and the source/drain regions 112/114 have an n-type dopant) (Huh, Fig. 6F, ¶0046) having an incorporated dopant, wherein the intermediate dielectric layer (120/122/124/134) is disposed between and in contact with each of the conductive layer (132) and the semiconductor material (118) having the incorporated dopant.
Further, Huh does not specifically disclose a conductive layer characterized by a first tensile stress, wherein the first tensile stress in the conductive layer is less than 1 MPa; and wherein a second tensile stress is at least ten times the first tensile stress.
However, Chan teaches forming nFET transistor (Chan, Figs. 2, 4, ¶0042-¶0044) comprising a conductive layer (e.g., a tungsten layer for gate structure 204) characterized by a first stress including a low stress or stress neutral tungsten to improve the electron mobility of the channel region (210).
It is well-known in the art (e.g., Chatty (¶0009-¶0011) that the stress is a measure of the average amount of force exerted per unit area. The neutral or slightly tensile stress refers to a stress magnitude between 0 MPa and 200 MPa, as evidenced by Chatty (¶0011).
Further, a low stress in a conductive material (e.g., a tungsten film 305) (as evidence by Suzuki, Figs. 7-8, 10, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) refers to a stress magnitude of about 148.5 Pa or less than about 300 MPa (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
The claimed range less than 1 MPa overlaps or lies inside the prior art ranges of Chatty (e.g., between 0 MPa and 200 MPa), and Suzuki (e.g., 148.5 Pa or less than about 300 MPa) (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
Further, Suzuki teaches that a stress in the conductive layer (e.g., tungsten film) (Suzuki, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) depends on a thickness of the conductive layer, a method of forming, and a stress reduction process, to provide the conductive layer that is stressed as little as possible, to prevent bending of the semiconductor device.
Further, Chen teaches forming a conductive layer (Chen, Fig. 6, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037) with controlled intrinsic stress to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device, wherein the film stress (tensile or compressive) in the conductive layer is controlled by applying a bias power to the substrate during the deposition, and the conductive layer includes copper, aluminum, or tungsten (Chen, Fig. 6, ¶0024). Specifically, the stress in the deposited copper layer (Chen, Fig. 6, ¶0037) is tensile (e.g., less than 20 MPa, as shown in Fig. 6) at the bias power below about 200 watts.
Thus, Suzuki recognizes that a method of forming and a thickness of the conductive layer impact the stress of the conductive layer. Further, Chen recognizes that a method of forming the conductive layer impacts a magnitude of the stress of the conductive layer. Thus, the method of forming and the thickness of the conductive layer are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a method of forming and a thickness of the conductive layer as Suzuki and Chen have identified a method of forming and a thickness of the conductive layer as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific slightly tensile stress in the conducive layer less than 1 MPa, in order to provide conductive layer with reduced stress to prevent bending of the semiconductor device as taught by Suzuki (¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device as taught by Chen (¶0002, ¶0008, ¶0010, ¶0024, ¶0037) (MPEP 2144.05).
Thus, a person of ordinary skill in the art would recognize that by forming a conductive layer of Huh comprised of tungsten material characterized by a first tensile stress that is substantially low stress with a specific magnitude of stress (as taught by Chan and evidenced by Suzuki, Chatty, and Chen), wherein the magnitude of the first stress is less than 1 MPa, a second tensile stress of Huh with stress magnitude of greater than 2GPa would be at least ten times the first tensile stress.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Huh by forming a conductive layer including a lowly stressed tungsten as taught by Chan, and optimizing the thickness and method of forming of the conductive layer (as evidenced by Suzuki and Chen) to provide the lowly stressed conductive layer having a specific stress magnitude to have the semiconductor structure, comprising a conductive layer characterized by a first tensile stress, wherein the first tensile stress in the conductive layer is less than 1 MPa; and wherein a second tensile stress is at least ten times the first tensile stress, in order to improve the electron mobility of the channel region; and to provide conductive layer with reduced stress to prevent bending of the semiconductor device; and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device (Chan, ¶0002-¶0006, ¶0044; Suzuki, ¶0009-¶0010, ¶0127, ¶0129; Chen, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037).
Regarding claim 3, Huh in view of Chan discloses the semiconductor structure of claim 1. Further, Huh discloses the semiconductor structure, wherein the second tensile stress (e.g., greater than 2 GPa) in the intermediate dielectric layer (e.g., 120/122/124/134, including boron-containing film 122 has a tensile stress greater than 2 GPa) (Huh, Fig. 6F, ¶0019, ¶0045, ¶0047, ¶0051) is greater than 1 MPa.
Regarding claim 4, Huh in view of Chan discloses the semiconductor structure of claim 1. Further, Huh does not specifically disclose the semiconductor structure, wherein the first tensile stress in the conductive layer is less than 0.1 MPa.
However, Chan teaches forming the conductive layer having stress neutral tungsten (Chan, Figs. 2, 4, ¶0044).
It is well-known in the art (e.g., Chatty (¶0009-¶0011) that the stress is a measure of the average amount of force exerted per unit area. The neutral or slightly tensile stress refers to a stress magnitude between 0 MPa and 200 MPa, as evidenced by Chatty (¶0011).
Further, a low stress in a conductive material (e.g., a tungsten film 305) (as evidence by Suzuki, Figs. 7-8, 10, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) refers to a stress magnitude of about 148.5 Pa or less than about 300 MPa (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
The claimed range less than 0.1 MPa overlaps tor lies inside the prior art ranges of Chatty (e.g., between 0 MPa and 200 MPa), and Suzuki (e.g., 148.5 Pa or less than about 300 MPa) (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
Further, Suzuki teaches that a stress in the conductive layer (e.g., tungsten film) (Suzuki, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) depends on a thickness of the conductive layer, a method of forming, and a stress reduction process, to provide the conductive layer that is stressed as little as possible, to prevent bending of the semiconductor device.
Further, Chen teaches forming a conductive layer (Chen, Fig. 6, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037) with controlled intrinsic stress to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device, wherein the film stress (tensile or compressive) in the conductive layer is controlled by applying a bias power to the substrate during the deposition, and the conductive layer includes copper, aluminum, or tungsten (Chen, Fig. 6, ¶0024). Specifically, the stress in the deposited copper layer (Chen, Fig. 6, ¶0037) is tensile (e.g., less than 20 MPa, as shown in Fig. 6) at the bias power below about 200 watts.
Thus, Suzuki recognizes that a method of forming and a thickness of the conductive layer impact the stress of the conductive layer. Further, Chen recognizes that a method of forming the conductive layer impacts a magnitude of the stress of the conductive layer. Thus, the method of forming and the thickness of the conductive layer are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a method of forming and a thickness of the conductive layer as Suzuki and Chen have identified a method of forming and a thickness of the conductive layer as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific slightly tensile stress in the conducive layer less than 0.1 MPa, in order to provide conductive layer with reduced stress to prevent bending of the semiconductor device as taught by Suzuki (¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device as taught by Chen (¶0002, ¶0008, ¶0010, ¶0024, ¶0037) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Huh/Chan by forming a conductive layer including a lowly stressed tungsten as taught by Chan, and optimizing the thickness and method of forming of the conductive layer (as evidenced by Suzuki and Chen) to have the lowly stressed conductive layer having a specific stress magnitude to have the semiconductor structure, wherein the first tensile stress in the conductive layer is less than 0.1 MPa, in order to improve the electron mobility of the channel region; and to provide conductive layer with reduced stress to prevent bending of the semiconductor device; and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device (Chan, ¶0002-¶0006, ¶0044; Suzuki, ¶0009-¶0010, ¶0127, ¶0129; Chen, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037).
Regarding claim 5, Huh in view of Chan discloses the semiconductor structure of claim 1. Further, Huh discloses the semiconductor structure, wherein the second tensile stress (e.g., greater than 2 GPa) in the intermediate dielectric layer (e.g., 120/122/124/134, including boron-containing film 122 has a tensile stress greater than 2 GPa) (Huh, Fig. 6F, ¶0019, ¶0045, ¶0047, ¶0051) is greater than 50 MPa.
Regarding claim 6, Huh in view of Chan discloses the semiconductor structure of claim 1. Further, Huh discloses the semiconductor structure, wherein the conductive layer (132) (Huh, Fig. 6F, ¶0050, ¶0054) comprises tungsten.
Regarding claim 7, Huh in view of Chan discloses the semiconductor structure of claim 1. Further, Huh discloses the semiconductor structure, wherein the intermediate dielectric layer (e.g., 120/122/124/134, including silicon nitride layers 120 and 124, and boron-containing film 122 such as boron silicon nitride BSiN) (Huh, Fig. 6F, ¶0019, ¶0045, ¶0047, ¶0051) comprises silicon nitride.
Regarding claim 8, Huh in view of Chan discloses the semiconductor structure of claim 1. Further, Huh discloses the semiconductor structure, wherein the semiconductor material (e.g., p-type well 118 of the n-type NMOS transistor has a p-type dopant and the source/drain regions 112/114 have an n-type dopant) (Huh, Fig. 6F, ¶0046) having an incorporated dopant comprises a source region (112), a drain region (114), or a channel region of a semiconductor transistor.
Regarding claim 9, Huh in view of Chan discloses the semiconductor structure of claim 1. Further, Huh discloses the semiconductor structure, wherein the semiconductor structure comprises an n-channel MOSFET (Huh, Fig. 6F, ¶0046).
With respect to claim 10, Huh discloses a semiconductor structure (e.g., NMOS transistor structure 100) (Huh, Fig. 6F, ¶0008-¶0009, ¶0019, ¶0029-¶0030, ¶0034, ¶0038, ¶0041-¶0054) comprising:
a substrate (e.g., a substrate including isolation regions 116 and p-type well 118 of the n-type NMOS transistor) (Huh, Fig. 6F, ¶0046) comprising doped source (112) and drain (114) regions (the source/drain region in the p-type well 118 of the NMOS include n-type dopant);
a conductive layer (132, tungsten plug) (Huh, Fig. 6F, ¶0050, ¶0054);
an intermediate dielectric layer (e.g., 120/122/124/134, including silicon nitride material and boron-containing film 122 has a tensile stress greater than 2 GPa) (Huh, Fig. 6F, ¶0019, ¶0045, ¶0047, ¶0051) in physical contact with each of the conductive layer (132) and the substrate (e.g., the substrate including isolation regions 116), wherein the intermediate dielectric layer (120/122/124/134) is characterized by a second tensile stress (e.g., boron-containing film 122 has a tensile stress greater than 2 GPa) (Huh, Fig. 6F, ¶0019), and wherein the intermediate dielectric laver (120/122/124) defines one or more contact trenches (e.g., a contact via 128) (Huh, Fig. 6F, ¶0048-¶0050, ¶0054) with the conductive layer (132) being deposited within the one or more contact trenches (128).
Further, Huh does not specifically disclose a conductive layer characterized by a first tensile stress, wherein the first tensile stress in the conductive layer is less than 1 MPa; and wherein a second tensile stress is at least fifteen times the first tensile stress.
However, Chan teaches forming nFET transistor (Chan, Figs. 2, 4, ¶0042-¶0044) comprising a conductive layer (e.g., a tungsten layer for gate structure 204) characterized by a first stress including a low stress or stress neutral tungsten to improve the electron mobility of the channel region (210).
It is well-known in the art (e.g., Chatty (¶0009-¶0011) that the stress is a measure of the average amount of force exerted per unit area. The neutral or slightly tensile stress refers to a stress magnitude between 0 MPa and 200 MPa, as evidenced by Chatty (¶0011).
Further, a low stress in a conductive material (e.g., a tungsten film 305) (as evidence by Suzuki, Figs. 7-8, 10, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) refers to a stress magnitude of about 148.5 Pa or less than about 300 MPa (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
The claimed range less than 1 MPa overlaps or lies inside the prior art ranges of Chatty (e.g., between 0 MPa and 200 MPa), and Suzuki (e.g., 148.5 Pa or less than about 300 MPa) (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
Further, Suzuki teaches that a stress in the conductive layer (e.g., tungsten film) (Suzuki, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) depends on a thickness of the conductive layer, a method of forming, and a stress reduction process, to provide the conductive layer that is stressed as little as possible, to prevent bending of the semiconductor device.
Further, Chen teaches forming a conductive layer (Chen, Fig. 6, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037) with controlled intrinsic stress to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device, wherein the film stress (tensile or compressive) in the conductive layer is controlled by applying a bias power to the substrate during the deposition, and the conductive layer includes copper, aluminum, or tungsten (Chen, Fig. 6, ¶0024). Specifically, the stress in the deposited copper layer (Chen, Fig. 6, ¶0037) is tensile (e.g., less than 20 MPa, as shown in Fig. 6) at the bias power below about 200 watts.
Thus, Suzuki recognizes that a method of forming and a thickness of the conductive layer impact the stress of the conductive layer. Further, Chen recognizes that a method of forming the conductive layer impacts a magnitude of the stress of the conductive layer. Thus, the method of forming and the thickness of the conductive layer are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a method of forming and a thickness of the conductive layer as Suzuki and Chen have identified a method of forming and a thickness of the conductive layer as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific slightly tensile stress in the conducive layer less than 1 MPa, in order to provide conductive layer with reduced stress to prevent bending of the semiconductor device as taught by Suzuki (¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device as taught by Chen (¶0002, ¶0008, ¶0010, ¶0024, ¶0037) (MPEP 2144.05).
Thus, a person of ordinary skill in the art would recognize that by forming a conductive layer of Huh comprised of tungsten material characterized by a first tensile stress that is substantially low stress with a specific magnitude of stress (as taught by Chan and evidenced by Suzuki, Chatty, and Chen), wherein the magnitude of the first stress is less than 1 MPa, a second tensile stress of Huh with stress magnitude of greater than 2GPa would be at least fifteen times the first tensile stress.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Huh by forming a conductive layer including a lowly stressed tungsten as taught by Chan, and optimizing the thickness and method of forming of the conductive layer (as evidenced by Suzuki and Chen) to provide the lowly stressed conductive layer having a specific stress magnitude to have the semiconductor structure, comprising a conductive layer characterized by a first tensile stress, wherein the first tensile stress in the conductive layer is less than 1 MPa; and wherein a second tensile stress is at least fifteen times the first tensile stress, in order to improve the electron mobility of the channel region; and to provide conductive layer with reduced stress to prevent bending of the semiconductor device; and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device (Chan, ¶0002-¶0006, ¶0044; Suzuki, ¶0009-¶0010, ¶0127, ¶0129; Chen, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037).
Regarding claim 12, Huh in view of Chan discloses the semiconductor structure of claim 10. Further, Huh discloses the semiconductor structure, wherein the second tensile stress (e.g., greater than 2 GPa) in the intermediate dielectric layer (e.g., 120/122/124/134, including boron-containing film 122 has a tensile stress greater than 2 GPa) (Huh, Fig. 6F, ¶0019, ¶0045, ¶0047, ¶0051) is greater than 1 MPa.
Regarding claim 13, Huh in view of Chan discloses the semiconductor structure of claim 10. Further, Huh does not specifically disclose the semiconductor structure, wherein the first tensile stress in the conductive layer is less than 0.1 MPa.
However, Chan teaches forming the conductive layer having stress neutral tungsten (Chan, Figs. 2, 4, ¶0044).
It is well-known in the art (e.g., Chatty (¶0009-¶0011) that the stress is a measure of the average amount of force exerted per unit area. The neutral or slightly tensile stress refers to a stress magnitude between 0 MPa and 200 MPa, as evidenced by Chatty (¶0011).
Further, a low stress in a conductive material (e.g., a tungsten film 305) (as evidence by Suzuki, Figs. 7-8, 10, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) refers to a stress magnitude of about 148.5 Pa or less than about 300 MPa (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
The claimed range less than 0.1 MPa overlaps tor lies inside the prior art ranges of Chatty (e.g., between 0 MPa and 200 MPa), and Suzuki (e.g., 148.5 Pa or less than about 300 MPa) (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
Further, Suzuki teaches that a stress in the conductive layer (e.g., tungsten film) (Suzuki, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) depends on a thickness of the conductive layer, a method of forming, and a stress reduction process, to provide the conductive layer that is stressed as little as possible, to prevent bending of the semiconductor device.
Further, Chen teaches forming a conductive layer (Chen, Fig. 6, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037) with controlled intrinsic stress to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device, wherein the film stress (tensile or compressive) in the conductive layer is controlled by applying a bias power to the substrate during the deposition, and the conductive layer includes copper, aluminum, or tungsten (Chen, Fig. 6, ¶0024). Specifically, the stress in the deposited copper layer (Chen, Fig. 6, ¶0037) is tensile (e.g., less than 20 MPa, as shown in Fig. 6) at the bias power below about 200 watts.
Thus, Suzuki recognizes that a method of forming and a thickness of the conductive layer impact the stress of the conductive layer. Further, Chen recognizes that a method of forming the conductive layer impacts a magnitude of the stress of the conductive layer. Thus, the method of forming and the thickness of the conductive layer are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a method of forming and a thickness of the conductive layer as Suzuki and Chen have identified a method of forming and a thickness of the conductive layer as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific slightly tensile stress in the conducive layer less than 0.1 MPa, in order to provide conductive layer with reduced stress to prevent bending of the semiconductor device as taught by Suzuki (¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device as taught by Chen (¶0002, ¶0008, ¶0010, ¶0024, ¶0037) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Huh/Chan by forming a conductive layer including a lowly stressed tungsten as taught by Chan, and optimizing the thickness and method of forming of the conductive layer (as evidenced by Suzuki and Chen) to have the lowly stressed conductive layer having a specific stress magnitude to have the semiconductor structure, wherein the first tensile stress in the conductive layer is less than 0.1 MPa, in order to improve the electron mobility of the channel region; and to provide conductive layer with reduced stress to prevent bending of the semiconductor device; and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device (Chan, ¶0002-¶0006, ¶0044; Suzuki, ¶0009-¶0010, ¶0127, ¶0129; Chen, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037).
Regarding claim 14, Huh in view of Chan discloses the semiconductor structure of claim 10. Further, Huh discloses the semiconductor structure, wherein the second tensile stress (e.g., greater than 2 GPa) in the intermediate dielectric layer (e.g., 120/122/124/134, including boron-containing film 122 has a tensile stress greater than 2 GPa) (Huh, Fig. 6F, ¶0019, ¶0045, ¶0047, ¶0051) is greater than 50 MPa.
Regarding claim 15, Huh in view of Chan discloses the semiconductor structure of claim 10. Further, Huh discloses the semiconductor structure, wherein the conductive layer (132) (Huh, Fig. 6F, ¶0050, ¶0054) comprises tungsten.
Regarding claim 16, Huh in view of Chan discloses the semiconductor structure of claim 10. Further, Huh discloses the semiconductor structure, wherein the intermediate dielectric layer (e.g., 120/122/124/134, including silicon nitride layers 120 and 124, and boron-containing film 122 such as boron silicon nitride BSiN) (Huh, Fig. 6F, ¶0019, ¶0045, ¶0047, ¶0051) comprises silicon nitride.
Regarding claim 17, Huh in view of Chan discloses the semiconductor structure of claim 10. Further, Huh discloses the semiconductor structure, wherein the semiconductor structure comprises an n-channel MOSFET (Huh, Fig. 6F, ¶0046).
Regarding claim 18, Huh in view of Chan discloses the semiconductor structure of claim 1. Further, Huh discloses the semiconductor structure, wherein the intermediate dielectric layer (e.g., 120/122/124/134) is in physical contact with each of the conductive layer (132) and the semiconductor material (e.g., the source/drain regions 112/114 having an n-type dopant) (Huh, Fig. 6F, ¶0046) having the incorporated dopant.
Regarding claim 22, Huh in view of Chan discloses the semiconductor structure of claim 1. Further, Huh discloses the semiconductor structure, wherein the intermediate dielectric layer (e.g., 120/122/124/134) fully defines one or more contact trenches (e.g., a contact via 128 is circumscribed by the dielectric layers 120/122/124 that is interpreted as “dielectric layer fully defines”) (Huh, Figs. 6B, 6F, ¶0048) is formed.
Claims 20 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0342618 to Chen et al. (hereinafter Chen’618) in view of Chan (US 2012/0199887) (the reference US 2011/0073951 by Chatty, the reference US 2016/0351402 by Suzuki, and the reference US 2004/0060812 by Chen are presented as evidence).
With respect to claim 20, Chen’618 discloses a semiconductor structure (e.g., NMOS transistor structure 100) (Chen’618, Fig. 4, ¶0003-¶0004, ¶0015-¶0020) comprising:
a conductive layer (24, gate electrode including tungsten material) (Chen’618, Fig. 4, ¶0016);
an intermediate dielectric layer (e.g., 22, U-shaped gate dielectric layer including silicon oxide or silicon nitride material) (Chen’618, Fig. 4, ¶0016) in contact with the conductive layer (24), wherein the conductive layer (24) at least partially extends into the intermediate dielectric layer (e.g., 22); and
a semiconductor material (e.g., semiconductor substrate 10 having doped source/drain regions 14 comprising a p-type dopant) (Chen’618, Fig. 4, ¶0015, ¶0016) having an incorporated dopant, wherein the intermediate dielectric layer (22) is disposed between the conductive layer (24) and the semiconductor material (10) having the incorporated dopant, and wherein the intermediate dielectric layer (22) has a first surface in contact with the conductive laver (24) and a second surface opposite the first surface in contact with the semiconductor material (10).
Further, Chen’618 does not specifically disclose a conductive layer characterized by a first tensile stress less than or about 1 MPa.
However, Chan teaches forming nFET transistor (Chan, Figs. 2, 4, ¶0042-¶0044) comprising a conductive layer (e.g., a tungsten layer for gate structure 204) characterized by a first stress including a low stress or stress neutral tungsten to improve the electron mobility of the channel region (210).
It is well-known in the art (e.g., Chatty (¶0009-¶0011) that the stress is a measure of the average amount of force exerted per unit area. The neutral or slightly tensile stress refers to a stress magnitude between 0 MPa and 200 MPa, as evidenced by Chatty (¶0011).
Further, a low stress in a conductive material (e.g., a tungsten film 305) (as evidence by Suzuki, Figs. 7-8, 10, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) refers to a stress magnitude of about 148.5 Pa or less than about 300 MPa (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
The claimed range less than 1 MPa overlaps or lies inside the prior art ranges of Chatty (e.g., between 0 MPa and 200 MPa), and Suzuki (e.g., 148.5 Pa or less than about 300 MPa) (Suzuki, Figs. 8, 10, ¶0127, ¶0129).
In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists (M.P.E.P. §2144.05).
Further, Suzuki teaches that a stress in the conductive layer (e.g., tungsten film) (Suzuki, ¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) depends on a thickness of the conductive layer, a method of forming, and a stress reduction process, to provide the conductive layer that is stressed as little as possible, to prevent bending of the semiconductor device.
Further, Chen teaches forming a conductive layer (Chen, Fig. 6, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037) with controlled intrinsic stress to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device, wherein the film stress (tensile or compressive) in the conductive layer is controlled by applying a bias power to the substrate during the deposition, and the conductive layer includes copper, aluminum, or tungsten (Chen, Fig. 6, ¶0024). Specifically, the stress in the deposited copper layer (Chen, Fig. 6, ¶0037) is tensile (e.g., less than 20 MPa, as shown in Fig. 6) at the bias power below about 200 watts.
Thus, Suzuki recognizes that a method of forming and a thickness of the conductive layer impact the stress of the conductive layer. Further, Chen recognizes that a method of forming the conductive layer impacts a magnitude of the stress of the conductive layer. Thus, the method of forming and the thickness of the conductive layer are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, a method of forming and a thickness of the conductive layer as Suzuki and Chen have identified a method of forming and a thickness of the conductive layer as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific slightly tensile stress in the conducive layer less than or about 1 MPa, in order to provide conductive layer with reduced stress to prevent bending of the semiconductor device as taught by Suzuki (¶0009-¶0010, ¶0045, ¶0103, ¶0124, ¶0127, ¶0129) and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device as taught by Chen (¶0002, ¶0008, ¶0010, ¶0024, ¶0037) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor structure of Chen’618 by forming a conductive layer including a lowly stressed tungsten as taught by Chan, and optimizing the thickness and method of forming of the conductive layer (as evidenced by Suzuki and Chen) to provide the lowly stressed conductive layer having a specific stress magnitude to have the semiconductor structure, comprising a conductive layer characterized by a first tensile stress less than or about 1 MPa, to provide conductive layer with reduced stress to prevent bending of the semiconductor device; and to prevent cracking in the deposited layer to ensure the reliability of the semiconductor device (Chan, ¶0002-¶0006, ¶0044; Suzuki, ¶0009-¶0010, ¶0127, ¶0129; Chen, ¶0002, ¶0008, ¶0010, ¶0024, ¶0037).
Regarding claim 21, Chen’618 in view of Chan discloses the semiconductor structure of claim 20. Further, Chen’618 discloses the semiconductor structure, wherein the intermediate dielectric layer (22) (Chen’618, Fig. 4, ¶0015, ¶0016) is in physical contact with each of the conductive layer (24) and the semiconductor material (10) having the incorporated dopant.
Response to Arguments
Applicant's arguments filed 11/12/2025 have been fully considered but they are not persuasive.
In response to Applicant’s argument regarding claim 1 that “[o]nly one layer, liner 120 of FIG. 6F of Huh, is actually in contact with each of the conductive layer and the semiconductor material having the incorporated dopant (or substrate). As such, the other cited layers (boron-containing film 122, cap 124, and …a dielectric surface 134) of Huh are not in contact with each of the conductive layer and the semiconductor material having the incorporated dopant (or substrate)”, the examiner submits that the term “in contact” is considered as a broad term which does not require two elements to be in direct contact. Thus, the above Applicant’s argument regarding claim 1 is not persuasive, and the rejection of claim 1 under 35 USC 103 over Huh in view of Chan is maintained.
In response to Applicant’s argument regarding claim 10 that “[H]uh does not teach or suggest the intermediate dielectric layer defines one or more contact trenches”, the examiner submits that the contact trench (e.g., a contact via 128) of Huh (Fig. 6B) is etched through the dielectric layers (120/122/124) such that the contact via (128) is circumscribed by the dielectric layers (120/122/124), thus the dielectric layers (e.g., 120/122/124) defines one or more contact trenches as required by claim 10.
In response to Applicant’s argument regarding claim 10 that “[H]uh does not teach or suggest …the intermediate dielectric layer is disposed between and in contact with, such as in physical contact with, each of the conductive layer and the semiconductor material having the incorporated dopant (or substrate)”, the examiner submits that the intermediate dielectric layer (120/122/124) of Huh is direct contact with the conductive layer and the semiconductor material (substrate). Note that the limitation “an intermediate dielectric layer” is interpreted as “one or more” because the claim uses an open ended transition phrase “comprising”. Further, claim 10 does not define “an intermediate dielectric layer” as a single layer. Thus, the above Applicant’s arguments are not persuasive, and the rejection of claim 10 under 35 USC 103 over Huh in view of Chan is maintained.
Regarding dependent claims 3-9, 12-18, and 22 which depend on the independent claims 1 and 10, the examiner respectfully submits that the applicant’s arguments with respect to dependent claims are not persuasive for the above reasons, thus, the rejections of the dependent claims are sustained.
Applicant’s arguments with respect to claim 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891