DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9-20 are canceled from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/12/2025.
Claims 1-8 and claim 21-32 are still pending.
Claim Objections
Claims 1-8, and 21-32 is/are objected to because of the following informalities:
Claim 1 recites "First CESL" in line L18 but should read --the First contact etch stop layer (CESL)--.
Claim 2 recites "if the source/drain feature” in lines L2-3but should read --of the source/drain feature--.
Claim 4 recites "the First CESL" in line L2 but should read --the First contact etch stop layer (CESL)--.
Claim 6 recites "the First CESL" in line L3 but should read --the First contact etch stop layer (CESL)--.
Claim 7 recites "the First CESL" in line L4 but should read --the First contact etch stop layer (CESL)--.
Claim 8 recites "the First CESL" in line 3 but should read --the First contact etch stop layer (CESL)--.
Claim 21 recites "the First CESL" in line L11 but should read --the First contact etch stop layer (CESL)--.
Claim 22 recites "the First CESL" in line L2 but should read --the First contact etch stop layer (CESL)--.
Claim 24 recites "the First CESL" in line L1 but should read --the First contact etch stop layer (CESL)--.
Claim 28 recites "the First CESL" in lines L14-15 but should read --the First contact etch stop layer (CESL)--.
Claim 28 recites "the First CESL" in line L16 but should read --the First contact etch stop layer (CESL)--.
Claim 28 recites " the contact plug are spaced apart” in line L12 but should read -- the contact plug is spaced apart --.
Claim 31 recites "the First CESL" in line L1 but should read --the First contact etch stop layer (CESL)--.
The balance of claims are objected to for being dependent upon an already objected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 21-23, 25-27, 28-30, and 32 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20210376139 A1-Huang39).
Regarding claim 1, Huang39 discloses a semiconductor structure (Title), comprising:
an active region extending along a first direction (Active region horizontally extending-Examiner's annotated Fig 16A) and comprising
a first channel region (First channel region 58/52-Examiner's annotated Fig 16A),
a second channel region (Second channel region 58/52-Examiner's annotated Fig 16A), and
a source/drain region sandwiched between the first channel region and the second channel region along the first direction (Source/Drain Region indicated by a dashed line rectangle under 70, sandwiched between both channel regions 52-Examiner's annotated Fig 16A);
a first gate structure disposed over the first channel region (Left Gate structure 84/82 over channel region 52-Examiner's annotated Fig 16A) and
extending lengthwise along a second direction perpendicular to the first direction (84 vertically extending so extending along a second direction perpendicular to the first horizontal direction-Examiner's annotated Fig 16A);
a second gate structure disposed over the second channel region (Right Gate structure 84/82 over channel region 52-Examiner's annotated Fig 16A) and
extending lengthwise along the second direction (84 vertically extending so extending along a second direction perpendicular to the first horizontal direction-Examiner's annotated Fig 16A);
a source/drain feature disposed over the source/drain region (Source/drain feature 70 over source/drain region indicated with a dashed rectangle under 70-Examiner's annotated Fig 16A);
a first gate spacer disposed along a sidewall of the first gate structure (First/Left gate spacer 66 disposed along sidewall of 84/82-Examiner's annotated Fig 16A);
a second gate spacer disposed along a sidewall of the second gate structure (Second/Right gate spacer 66 disposed along sidewall of 84/82-Examiner's annotated Fig 16A);
a first contact etch stop layer (CESL) disposed over a top surface of the source/drain feature (First CESL 72 over a top surface of 70-Examiner's annotated Fig 16A) and
extending along sidewalls of the first gate spacer and the second gate spacer (72 extending along 66-Examiner's annotated Fig 16A);
a second CESL disposed over the top surface of the source/drain feature (ILD 74 has been interpretated as the second CESL-Examiner's annotated Fig 16A) and
extending along sidewalls of the first CESL (74 extending on sidewalls of 72-Examiner's annotated Fig 16A); and
a contact plug extending through the second CESL (Contact plug 102 extending through the second CESL 74)
such that the second CESL is sandwiched between first CESL and the contact plug (Second CESL 74 is sandwiched between First CESL 72 and contact plug 102-Examiner's annotated Fig 16A).
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Regarding claim 2, Huang39 discloses all the elements of claim 1, as noted above.
Huang39 further discloses a semiconductor structure further comprising:
a silicide layer wrapping over the top surface and sidewalls if the source/drain feature (Silicide layer 96 wrapping around Drain/Source feature 70-Examiner's annotated Fig 16B),
wherein the contact plug is electrically coupled to the source/drain feature by way of the silicide layer (silicide layer 96 is electrically coupled to S/D feature 70-[0059] L 9-10; the contact plug is electrically connected to silicide layer 96 so connected to D/S feature 70 by the way of silicide layer 96-[0061] L14-17).
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Regarding claim 3, Huang39 discloses all the elements of claim 2, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer undercuts the second CESL (silicide layer 96 undercuts second CESL 74-[0059] L1-2, Fig 12A and 12B).
Regarding claim 4, Huang39 discloses all the elements of claim 2, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer further undercuts the first CESL. (silicide layer 96 undercuts the first CESL 72, especially at the portion 72B in the undercut 94-[0059] L14-16, Fig 12a and 12B).
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Regarding claim 5, Huang39 discloses all the elements of claim 2, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer extends between a sidewall of the source/drain feature and the second CESL (Silicide layer 96 extends between a sidewall of S/D feature 70 and the second CESL 74-Examiner’s annotated Fig 16B).
Regarding claim 6, Huang39 discloses all the elements of claim 1, as noted above.
Huang39 further discloses a semiconductor structure
wherein top surfaces of the first gate structure, the second gate structure, the first gate spacer, the second gate spacer, the first CESL, and the second CESL are coplanar (top surface of Left/right gate structures 84/82, left/right gate spacer 66, First CESL 72, and second CESL 74 are coplanar-Examiner's annotated Fig 12A).
Regarding claim 7, Huang39 discloses all the elements of claim 6, as noted above.
Huang39 further discloses a semiconductor structure
further comprising: an etch stop layer (ESL) disposed on and in contact with the top surfaces of the first gate structure, the second gate structure, the first gate spacer, the second gate spacer, the first CESL, and the second CESL (ESL layer is present under ILD layer 90 so on and in contact with top surface of Left/right gate structures 84/82, left/right gate spacer 66, First CESL 72, and second CESL 74-Examiner's annotated Fig 12A, [0052] L11-16).
Regarding claim 8, Huang39 discloses all the elements of claim 1, as noted above.
Huang39 further discloses a semiconductor structure
wherein a bottom surface of the second CESL extends further into the source/drain feature than a bottom surface of the first CESL (A bottom surface of Second CESL 74 extending further into the source/drain feature 70 than a bottom surface of First CESL 72-Examiner's annotated Fig 7A).
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Regarding claim 21, Huang39 discloses a semiconductor structure (Title), comprising:
an active region extending along a first direction (Active region horizontally extending-Examiner's annotated Fig 16A) and comprising
a source/drain region (Examiner's annotated Fig 16A);
a source/drain feature disposed over the source/drain region (Source/drain feature 70 over source/drain region indicated with a dashed rectangle under 70-Examiner's annotated Fig 16A);
a silicide layer disposed over and interfacing the source/drain feature (Silicide layer 96 over and interfacing Drain/Source feature 70-Examiner's annotated Fig 16A); and
a contact plug disposed over and interfacing the silicide layer (Contact plug 102 disposed over and interfacing the silicide layer 96-Examiner's annotated Fig 16A),
wherein the contact plug is disposed between a first gate spacer and a second gate spacer along the first direction (Contact plug 102 disposed between Left/First gate spacer 66 and second/Right gate spacer 66 along the horizontal/first direction-Examiner's annotated Fig 16A),
wherein sidewalls of the contact plug are spaced apart from the first gate spacer and the second gate spacer by a first contact etch stop layer (CESL) (sidewalls of contact plug 102 spaced apart from both gate spacers 66-Examiner's annotated Fig 16A) ,
wherein the sidewalls of the contact plug are spaced apart from the first CESL by a second CESL (ILD 74 and a liner inside the recess 92 before forming the contact plug 102 have been interpretated as the second CESL so spacing apart the sidewalls of contact plug 102 from first CESL 72-[0061] L1-6-Fig 13A and 13B) ,
wherein, along the first direction, the silicide layer undercuts the second CESL (along the first/horizontal direction, the silicide layer 96 undercuts the liner inside the recess 92 so on the sidewalls of the contact plug 102-[0061] L1-6-Fig 13A and 13B).
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Regarding claim 22, Huang39 discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein, along the first direction, the silicide layer further undercuts the first CESL (Along the horizontal/first direction, silicide layer 96 undercuts the first CESL 72, especially at the portion 72B in the undercut 94-[0059] L14-16, Fig 12A and 12B).
Regarding claim 23, Huang39 discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein, along a second direction perpendicular to the first direction, the contact plug is spaced apart from the second CESL by the silicide layer (vertically spaced apart from the second CESL 74 by the silicide layer 96, so in a direction perpendicular to the first/horizontal direction-Examiner's annotated Fig 16B).
Regarding claim 25, Huang39 discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer comprises TiSi, ZrSi, SbSi, BiSi, NiSi, SnSi, MoSi, or a combination thereof. (silicide layer 96 formed with metal such as Titanium or Nickel so comprising TiSi or NiSi-[0059] L 5-8)
Regarding claim 26, Huang39 discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein the contact plug comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo),or tungsten (W) (contact plug 102 comprising a liner which may include Titanium, and comprising copper-[0061] L6-10).
Regarding claim 27, Huang39 discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer comprises a thickness between about 1 nm and about 10 nm (the silicide layer 96 thickness being between 2nm to 5 nm so between 1nm and 10 nm-[060] L 8-9).
Regarding claim 28, Huang39 discloses a semiconductor structure (Title), comprising:
an active region extending lengthwise along a first direction (Active region horizontally extending-Examiner's annotated Fig 16A), the active region comprising
a source/drain region (Source/Drain Region 70 sandwiched between both channel regions 52-Examiner's annotated Fig 16A) and
a channel region adjacent the source/drain region (Source/Drain Region 70 sandwiched between both channel regions 58/52-Examiner's annotated Fig 16A);
an isolation feature surrounding a base portion of the active region (Isolation feature 56 surrounding a base portion of the active region 52-Fig 16B);
a gate structure wrapping over the channel region (Right Gate structure 84/82 wrapping over channel region 58/52-Examiner's annotated Fig 16A/B);
a gate spacer extending along a sidewall of the gate structure (gate spacer 66 disposed along sidewall of 84/82-Examiner's annotated Fig 16A);
a source/drain feature over the source/drain region (Source/drain feature 70 over source/drain region indicated with a dashed rectangle under 70-Examiner's annotated Fig 16A) and
interfacing with a sidewall of the channel region (Source/drain feature 70 interfacing channel region 52/58- Examiner's annotated Fig 16A);
a silicide layer covering a top surface and sidewalls of the source/drain feature (Silicide layer 96 covering a top surface and sidewalls of Drain/Source feature 70-Examiner's annotated Fig 16B); and
a contact plug disposed over and interfacing with the silicide layer (Contact plug 102 over and interfacing silicide layer 96-Examiner's annotated Fig 16B),
wherein, along the first direction, the contact plug are spaced apart from the gate spacer by a first contact etch stop layer (CESL),
wherein, along the first direction, the contact plug is spaced apart from the first CESL by a second CESL (ILD 74 and a liner inside the recess 92 before forming the contact plug 102 have been interpretated as the second CESL so spacing apart the sidewalls of contact plug 102 from first CESL 72-[0061] L1-6-Fig 13A and 13B; contact plug 102 spaced apart from first CESL 72 by second CESL 74 along the horizontal/first direction-Examiner's annotated Fig 16A),
wherein the first CESL and the second CESL are disposed over and interfacing the silicide layer (ILD 74 and a liner inside the recess 92 before forming the contact plug 102 have been interpretated as the second CESL; first CESL 72 and second CESL 74 disposed over and interfacing silicide layer 96-[0061] L1-6-Fig 13A and 13B).
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Regarding claim 29, Huang39 discloses all the elements of claim 28, as noted above.
Huang39 further discloses a semiconductor structure wherein
along a second direction perpendicular to the first direction, the contact plug is spaced apart from the second CESL by the silicide layer (vertically spaced apart from the second CESL 74 by the silicide layer 96, so in a direction perpendicular to the first/horizontal direction-Examiner's annotated Fig 16B).
Regarding claim 30, Huang39 discloses all the elements of claim 28, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer comprises TiSi, ZrSi, SbSi, BiSi, NiSi, SnSi, MoSi, or a combination thereof (silicide layer 96 formed with metal such as Titanium or Nickel so comprising TiSi or NiSi-[0059] L 5-8).
Regarding claim 32, Huang39 discloses all the elements of claim 28, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer comprises a thickness between about 1 nm and about 10 nm (the silicide layer 96 thickness being between 2nm to 5 nm so between 1nm and 10 nm-[060] L 8-9).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 24 and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210376139 A1-Huang39) in view of Loubet et al. (US 10916627 B2-Loubet27).
Regarding claim 24, Huang39 discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein the first CESL (72 is silicon nitride-[0046] L 1-7, [0057]) and the second CESL (ILD 74 has been interpretated as the second CESL-Examiner's annotated Fig 16A).
Huang39 does not disclose a semiconductor structure wherein
the second CESL comprise silicon nitride or silicon oxynitride.
Loubet27 teaches a semiconductor structure wherein
the second CESL (ILD 410 has been interpretated as the second CESL) comprise silicon nitride or silicon oxynitride (ILD material 410 being silicon nitride or silicon oxynitride- C5 L53-57).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Huang39, as taught by Loupet27 for the purpose of enabling greater management of leakage and capacitance in the active regions, even as drive currents increase (Loubet27: Column C3 Lines L53-57).
Regarding claim 31, Huang39 discloses all the elements of claim 28, as noted above.
Huang39 further discloses a semiconductor structure
wherein the first CESL (72 is silicon nitride-[0046] L 1-7, [0057]) and the second CESL (ILD 74 has been interpretated as the second CESL-Examiner's annotated Fig 16A).
Huang39 does not disclose a semiconductor structure wherein
the second CESL comprise silicon nitride or silicon oxynitride.
Loubet27 teaches a semiconductor structure wherein
the second CESL (ILD 410 has been interpretated as the second CESL) comprise silicon nitride or silicon oxynitride (ILD material 410 being silicon nitride or silicon oxynitride- C5 L53-57).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Huang39, as taught by Loupet27 for the purpose of enabling greater management of leakage and capacitance in the active regions, even as drive currents increase (Loubet27: Column C3 Lines L53-57).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yu et al. (US20220069076A1-Yu76) teaches a semiconductor structure comprising a source/drain structure (260D/S-Fig 17), two gate structures (240-Fig 8), a silicide layer (273-Fig 17), a first CESL (269-Fig 17), and a channel region (Fig 2D).
Wu et al (US 20200075421 A1-Wu21) teaches a semiconductor structure comprising a source/drain structure (162-Fig 1B), two gate structures (149-Fig 4A), a silicide layer (165-Fig 1B), a First CESL (164-Fig 1B), and a channel region (104a/b-Fig 6A).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 01/06/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812