DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 05/06/2026 has been accepted and entered. Claims 1-8 and claim 21-32 remain pending in this application. Applicant’s amendments to the Claims have overcome few of the objections previously set forth in the Non-Final Office Action mailed on 1/30/2026.
Claim Objections
Claims 1-8, and 21-32 is/are objected to because of the following informalities:
Claim 1 recites "between First CESL" in line L18 but should read –between the First contact etch stop layer (CESL)--.
Claim 4 recites "the First CESL" in line L2 but should read --the First contact etch stop layer (CESL)--.
Claim 6 recites "the First CESL" in line L3 but should read --the First contact etch stop layer (CESL)--.
Claim 7 recites "the First CESL" in line L4 but should read --the First contact etch stop layer (CESL)--.
Claim 8 recites "the First CESL" in line 3 but should read --the First contact etch stop layer (CESL)--.
Claim 21 recites "the First CESL" in line L13 but should read --the First contact etch stop layer (CESL)--.
Claim 22 recites "the First CESL" in line L2 but should read --the First contact etch stop layer (CESL)--.
Claim 24 recites "the First CESL" in line L1 but should read --the First contact etch stop layer (CESL)--.
Claim 28 recites "the First CESL" in lines L14-15 but should read --the First contact etch stop layer (CESL)--.
Claim 28 recites "the First CESL" in line L16 but should read --the First contact etch stop layer (CESL)--.
Claim 31 recites "the First CESL" in line L1 but should read --the First contact etch stop layer (CESL)--.
The balance of claims are objected to for being dependent upon an already objected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 28-30, and 32 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20210376139 A1-Huang39).
Regarding claim 28, Huang39 discloses a semiconductor structure (Title), comprising:
an active region extending lengthwise along a first direction (Active region horizontally extending-Examiner's annotated Fig 16A), the active region comprising
a source/drain region (Source/Drain Region 70 sandwiched between both channel regions 52-Examiner's annotated Fig 16A) and
a channel region adjacent the source/drain region (Source/Drain Region 70 sandwiched between both channel regions 58/52-Examiner's annotated Fig 16A);
an isolation feature surrounding a base portion of the active region (Isolation feature 56 surrounding a base portion of the active region 52-Fig 16B);
a gate structure wrapping over the channel region (Right Gate structure 84/82 wrapping over channel region 58/52-Examiner's annotated Fig 16A/B);
a gate spacer extending along a sidewall of the gate structure (gate spacer 66 disposed along sidewall of 84/82-Examiner's annotated Fig 16A);
a source/drain feature over the source/drain region (Source/drain feature 70 over source/drain region indicated with a dashed rectangle under 70-Examiner's annotated Fig 16A) and
interfacing with a sidewall of the channel region (Source/drain feature 70 interfacing channel region 52/58- Examiner's annotated Fig 16A);
a silicide layer covering a top surface and sidewalls of the source/drain feature (Silicide layer 96 covering a top surface and sidewalls of Drain/Source feature 70-Examiner's annotated Fig 16B); and
a contact plug disposed over and interfacing with the silicide layer (Contact plug 102 over and interfacing silicide layer 96-Examiner's annotated Fig 16B),
wherein, along the first direction, the contact plug are spaced apart from the gate spacer by a first contact etch stop layer (CESL),
wherein, along the first direction, the contact plug is spaced apart from the first CESL by a second CESL (ILD 74 and a liner inside the recess 92 before forming the contact plug 102 have been interpretated as the second CESL so spacing apart the sidewalls of contact plug 102 from first CESL 72-[0061] L1-6-Fig 13A and 13B; contact plug 102 spaced apart from first CESL 72 by second CESL 74 along the horizontal/first direction-Examiner's annotated Fig 16A),
wherein the first CESL and the second CESL are disposed over and interfacing the silicide layer (ILD 74 and a liner inside the recess 92 before forming the contact plug 102 have been interpretated as the second CESL; first CESL 72 and second CESL 74 disposed over and interfacing silicide layer 96-[0061] L1-6-Fig 13A and 13B, Examiner’s annotated Huang39 Fig 12A).
PNG
media_image1.png
788
680
media_image1.png
Greyscale
PNG
media_image2.png
674
744
media_image2.png
Greyscale
PNG
media_image3.png
637
872
media_image3.png
Greyscale
Regarding claim 29, Huang39 discloses all the elements of claim 28, as noted above.
Huang39 further discloses a semiconductor structure wherein
along a second direction perpendicular to the first direction, the contact plug is spaced apart from the second CESL by the silicide layer (vertically spaced apart from the second CESL 74 by the silicide layer 96, so in a direction perpendicular to the first/horizontal direction-Examiner's annotated Fig 16B).
Regarding claim 30, Huang39 discloses all the elements of claim 28, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer comprises TiSi, ZrSi, SbSi, BiSi, NiSi, SnSi, MoSi, or a combination thereof (silicide layer 96 formed with metal such as Titanium or Nickel so comprising TiSi or NiSi-[0059] L 5-8).
Regarding claim 32, Huang39 discloses all the elements of claim 28, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer comprises a thickness between about 1 nm and about 10 nm (the silicide layer 96 thickness being between 2nm to 5 nm so between 1nm and 10 nm-[060] L 8-9).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 21-23, 25-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210376139 A1-Huang39) in view of Wu et al (US 20200075421 A1-Wu21).
Regarding claim 1, Huang39 discloses a semiconductor structure (Title), comprising:
an active region extending along a first direction (Active region horizontally extending-Examiner's annotated Fig 16A) and comprising
a first channel region (First channel region 58/52-Examiner's annotated Fig 16A),
a second channel region (Second channel region 58/52-Examiner's annotated Fig 16A), and
a source/drain region sandwiched between the first channel region and the second channel region along the first direction (Source/Drain Region indicated by a dashed line rectangle under 70, sandwiched between both channel regions 52-Examiner's annotated Fig 16A);
a first gate structure disposed over the first channel region (Left Gate structure 84/82 over channel region 52-Examiner's annotated Fig 16A) and
extending lengthwise along a second direction perpendicular to the first direction (84 vertically extending so extending along a second direction perpendicular to the first horizontal direction-Examiner's annotated Fig 16A);
a second gate structure disposed over the second channel region (Right Gate structure 84/82 over channel region 52-Examiner's annotated Fig 16A) and
extending lengthwise along the second direction (84 vertically extending so extending along a second direction perpendicular to the first horizontal direction-Examiner's annotated Fig 16A);
a source/drain feature disposed over the source/drain region (Source/drain feature 70 over source/drain region indicated with a dashed rectangle under 70-Examiner's annotated Fig 16A);
a first gate spacer disposed along a sidewall of the first gate structure (First/Left gate spacer 66 disposed along sidewall of 84/82-Examiner's annotated Fig 16A);
a second gate spacer disposed along a sidewall of the second gate structure (Second/Right gate spacer 66 disposed along sidewall of 84/82-Examiner's annotated Fig 16A);
a first contact etch stop layer (CESL) disposed over a top surface of the source/drain feature (First CESL 72 over a top surface of 70-Examiner's annotated Fig 16A) and
extending along sidewalls of the first gate spacer and the second gate spacer (72 extending along 66-Examiner's annotated Fig 16A);
a second CESL disposed over the top surface of the source/drain feature (ILD 74 has been interpretated as the second CESL-Examiner's annotated Fig 16A) and
extending along sidewalls of the first CESL (74 extending on sidewalls of 72-Examiner's annotated Fig 16A); and
a contact plug extending through the second CESL (Contact plug 102 extending through the second CESL 74)
such that the second CESL is sandwiched between first CESL and the contact plug (Second CESL 74 is sandwiched between First CESL 72 and contact plug 102-Examiner's annotated Fig 16A).
Huang39 does not disclose a semiconductor structure comprising:
a dielectric layer over the second CESL;
wherein a bottommost surface of the dielectric layer is lower than a topmost surface of the second CESL.
Wu21 teaches a semiconductor structure comprising:
a dielectric layer over the second CESL (Dielectric layer 166 over second CESL 186-Examiner’s annotated Wu21 Fig 1B);
wherein a bottommost surface of the dielectric layer is lower than a topmost surface of the second CESL (Dielectric layer 166 Bottommost surface being lower than Second CESL 186 Topmost surface-Examiner’s annotated Wu21 Fig 1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Huang39, as taught by Wu21 for the purpose of reducing contact resistance by using a silicide feature (Wu21: [0053]).
PNG
media_image4.png
788
680
media_image4.png
Greyscale
PNG
media_image5.png
612
1007
media_image5.png
Greyscale
Regarding claim 2, Huang39 and Wu21 combination discloses all the elements of claim 1, as noted above.
Huang39 further discloses a semiconductor structure further comprising:
a silicide layer wrapping over the top surface and sidewalls of the source/drain feature (Silicide layer 96 wrapping around Drain/Source feature 70-Examiner's annotated Fig 16B),
wherein the contact plug is electrically coupled to the source/drain feature by way of the silicide layer (silicide layer 96 is electrically coupled to S/D feature 70-[0059] L 9-10; the contact plug is electrically connected to silicide layer 96 so connected to D/S feature 70 by the way of silicide layer 96-[0061] L14-17).
PNG
media_image6.png
674
744
media_image6.png
Greyscale
Regarding claim 3, Huang39 and Wu21 combination discloses all the elements of claim 2, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer undercuts the second CESL (silicide layer 96 undercuts second CESL 74-[0059] L1-2, Fig 12A and 12B).
Regarding claim 4, Huang39 and Wu21 combination discloses all the elements of claim 2, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer further undercuts the first CESL. (silicide layer 96 undercuts the first CESL 72, especially at the portion 72B in the undercut 94-[0059] L14-16, Fig 12a and 12B).
PNG
media_image7.png
637
865
media_image7.png
Greyscale
Regarding claim 5, Huang39 and Wu21 combination discloses all the elements of claim 2, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer extends between a sidewall of the source/drain feature and the second CESL (Silicide layer 96 extends between a sidewall of S/D feature 70 and the second CESL 74-Examiner’s annotated Fig 16B).
Regarding claim 6, Huang39 and Wu21 combination discloses all the elements of claim 1, as noted above.
Huang39 further discloses a semiconductor structure
wherein top surfaces of the first gate structure, the second gate structure, the first gate spacer, the second gate spacer, the first CESL, and the second CESL are coplanar (top surface of Left/right gate structures 84/82, left/right gate spacer 66, First CESL 72, and second CESL 74 are coplanar-Examiner's annotated Fig 12A).
Regarding claim 7, Huang39 and Wu21 combination discloses all the elements of claim 6, as noted above.
Huang39 further discloses a semiconductor structure
further comprising: an etch stop layer (ESL) disposed on and in contact with the top surfaces of the first gate structure, the second gate structure, the first gate spacer, the second gate spacer, the first CESL, and the second CESL (ESL layer is present under ILD layer 90 so on and in contact with top surface of Left/right gate structures 84/82, left/right gate spacer 66, First CESL 72, and second CESL 74-Examiner's annotated Fig 12A, [0052] L11-16).
Regarding claim 8, Huang39 and Wu21 combination discloses all the elements of claim 1, as noted above.
Huang39 further discloses a semiconductor structure
wherein the second CESL extends further into the source/drain feature than the first CESL (A bottom surface of Second CESL 74 extending further into the source/drain feature 70 than a bottom surface of First CESL 72-Examiner's annotated Fig 7A).
PNG
media_image8.png
1051
813
media_image8.png
Greyscale
Regarding claim 21, Huang39 discloses a semiconductor structure (Title), comprising:
an active region extending along a first direction (Active region horizontally extending-Examiner's annotated Fig 16A) and comprising
a source/drain region (Examiner's annotated Fig 16A);
a source/drain feature disposed over the source/drain region (Source/drain feature 70 over source/drain region indicated with a dashed rectangle under 70-Examiner's annotated Fig 16A);
a silicide layer disposed over and interfacing the source/drain feature (Silicide layer 96 over and interfacing Drain/Source feature 70-Examiner's annotated Fig 16A); and
a contact plug disposed over and interfacing the silicide layer (Contact plug 102 disposed over and interfacing the silicide layer 96-Examiner's annotated Fig 16A),
wherein the contact plug is disposed between a first gate spacer and a second gate spacer along the first direction (Contact plug 102 disposed between Left/First gate spacer 66 and second/Right gate spacer 66 along the horizontal/first direction-Examiner's annotated Fig 16A),
wherein sidewalls of the contact plug are spaced apart from the first gate spacer and the second gate spacer by a first contact etch stop layer (CESL) (sidewalls of contact plug 102 spaced apart from both gate spacers 66-Examiner's annotated Fig 16A) ,
wherein the sidewalls of the contact plug are spaced apart from the first CESL by a second CESL (ILD 74 and a liner inside the recess 92 before forming the contact plug 102 have been interpretated as the second CESL so spacing apart the sidewalls of contact plug 102 from first CESL 72-[0061] L1-6-Fig 13A and 13B) ,
wherein, along the first direction, the silicide layer undercuts the second CESL (along the first/horizontal direction, the silicide layer 96 undercuts the liner inside the recess 92 so on the sidewalls of the contact plug 102-[0061] L1-6-Fig 13A and 13B).
Huang39 does not disclose a semiconductor structure comprising:
a dielectric layer,
wherein a portion of the contact plug is disposed over the dielectric layer,
wherein a bottommost surface of the dielectric layer is lower than a topmost surface of the second CESL.
Wu21 teaches a semiconductor structure comprising:
a dielectric layer (Dielectric layer 166 over second CESL 186-Examiner’s annotated Wu21 Fig 1B),
wherein a portion of the contact plug is disposed over the dielectric layer (A portion of the contact plug 188 disposed over the dielectric layer 166-Examiner’s annotated Wu21 Fig 1B);
wherein a bottommost surface of the dielectric layer is lower than a topmost surface of the second CESL (Dielectric layer 166 Bottommost surface being lower than Second CESL 186 Topmost surface-Examiner’s annotated Wu21 Fig 1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Huang39, as taught by Wu21 for the purpose of reducing contact resistance by using a silicide feature (Wu21: [0053]).
PNG
media_image9.png
788
680
media_image9.png
Greyscale
PNG
media_image10.png
612
1007
media_image10.png
Greyscale
Regarding claim 22, Huang39 and Wu21 combination discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein, along the first direction, the silicide layer further undercuts the first CESL (Along the horizontal/first direction, silicide layer 96 undercuts the first CESL 72, especially at the portion 72B in the undercut 94-[0059] L14-16, Fig 12A and 12B).
Regarding claim 23, Huang39 and Wu21 combination discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein, along a second direction perpendicular to the first direction, the contact plug is spaced apart from the second CESL by the silicide layer (vertically spaced apart from the second CESL 74 by the silicide layer 96, so in a direction perpendicular to the first/horizontal direction-Examiner's annotated Fig 16B).
Regarding claim 25, Huang39 and Wu21 combination discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer comprises TiSi, ZrSi, SbSi, BiSi, NiSi, SnSi, MoSi, or a combination thereof. (silicide layer 96 formed with metal such as Titanium or Nickel so comprising TiSi or NiSi-[0059] L 5-8)
Regarding claim 26, Huang39 and Wu21 combination discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein the contact plug comprises titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) ruthenium (Ru), nickel (Ni), cobalt (Co), copper (Cu), molybdenum (Mo),or tungsten (W) (contact plug 102 comprising a liner which may include Titanium, and comprising copper-[0061] L6-10).
Regarding claim 27, Huang39 and Wu21 combination discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein the silicide layer comprises a thickness between about 1 nm and about 10 nm (the silicide layer 96 thickness being between 2nm to 5 nm so between 1nm and 10 nm-[060] L 8-9).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210376139 A1-Huang39) in view of Wu et al (US 20200075421 A1-Wu21), and further in view of Loubet et al. (US 10916627 B2-Loubet27).
Regarding claim 24, Huang39 and Wu21 combination discloses all the elements of claim 21, as noted above.
Huang39 further discloses a semiconductor structure
wherein the first CESL (72 is silicon nitride-[0046] L 1-7, [0057]) and the second CESL (ILD 74 has been interpretated as the second CESL-Examiner's annotated Fig 16A).
Huang39 and Wu21 combination does not disclose a semiconductor structure wherein
the second CESL comprise silicon nitride or silicon oxynitride.
Loubet27 teaches a semiconductor structure wherein
the second CESL (ILD 410 has been interpretated as the second CESL) comprise silicon nitride or silicon oxynitride (ILD material 410 being silicon nitride or silicon oxynitride- C5 L53-57).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Huang39 in view of Wu21, as taught by Loupet27 for the purpose of enabling greater management of leakage and capacitance in the active regions, even as drive currents increase (Loubet27: Column C3 Lines L53-57).
Claim(s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210376139 A1-Huang39) in view of Loubet et al. (US 10916627 B2-Loubet27).
Regarding claim 31, Huang39 discloses all the elements of claim 28, as noted above.
Huang39 further discloses a semiconductor structure
wherein the first CESL (72 is silicon nitride-[0046] L 1-7, [0057]) and the second CESL (ILD 74 has been interpretated as the second CESL-Examiner's annotated Fig 16A).
Huang39 does not disclose a semiconductor structure wherein
the second CESL comprise silicon nitride or silicon oxynitride.
Loubet27 teaches a semiconductor structure wherein
the second CESL (ILD 410 has been interpretated as the second CESL) comprise silicon nitride or silicon oxynitride (ILD material 410 being silicon nitride or silicon oxynitride- C5 L53-57).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Huang39, as taught by Loupet27 for the purpose of enabling greater management of leakage and capacitance in the active regions, even as drive currents increase (Loubet27: Column C3 Lines L53-57).
Response to Arguments
Applicant’s arguments see pages 7-11 of Remarks, filed on 5/06/2026 with respect to claim(s) 1-8, 21-23, 25-27 have been considered. The Remarks appear to assert that Huang et al. (US 20210376139 A1-Huang39) does not teach the newly added limitations; this assertion is addressed in the rejections set forth above.
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations of claims 1 and 21. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Applicant's arguments see pages 7-11 of Remarks, filed on 5/06/2026 with respect to claim(s) 28-30 and 32 have been fully considered but they are not persuasive.
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the claim 28 limitation “wherein the first CESL and the second CESL are disposed over and interfacing the silicide layer”, this assertion is addressed in the rejections set forth above, especially with the Examiner’s annotated Huang39 Fig 12A.
Claims 1 and 21 have been amended to further define the claimed subject matter see pages 2-6 of Amendments to Claims, filed on 5/06/2026.
Claim(s) 1-8, 21-23, 25-27is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210376139 A1-Huang39) in view of Wu et al (US 20200075421 A1-Wu21), as described above.
Therefore, claim(s) 1-8, 21-23, 25-27 stand rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210376139 A1-Huang39) in view of Wu et al (US 20200075421 A1-Wu21).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210376139 A1-Huang39) in view of Wu et al (US 20200075421 A1-Wu21), and further in view of Loubet et al. (US 10916627 B2-Loubet27), as described above.
Therefore, claim(s) 24 stands rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210376139 A1-Huang39) in view of Wu et al (US 20200075421 A1-Wu21), and further in view of Loubet et al. (US 10916627 B2-Loubet27).
Claim(s) 28-30, and 32 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20210376139 A1-Huang39), as described above.
Therefore, claim(s) 28-30, and 32 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20210376139 A1-Huang39).
Claim(s) 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210376139 A1-Huang39) in view of Loubet et al. (US 10916627 B2-Loubet27), as described above.
Therefore, claim(s) 31 stands rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 20210376139 A1-Huang39) in view of Loubet et al. (US 10916627 B2-Loubet27).
Amended claim(s) 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (US 11195928-Lim28) as described above.
Therefore, claims 11-13 stand rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (US 11195928-Lim28).
Claim 15-19 and amended claims 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 11195928-Lim28).in view of Greene et al (US 10790372-“Greene”) as described above.
Therefore, claims 14-20 stand rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 11195928-Lim28).in view of Greene et al (US 10790372-“Greene”) as described above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 06/15/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights