DETAILED ACTION
This Notice is responsive to communication filed on 01/08/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 5/29/2023 and 7/8/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant's election with traverse of Group I and Species 4 in the reply filed on 1/8/2026 is acknowledged. The traversal is on the ground(s) that Applicant This is not found persuasive because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement. The restriction requirement is drawn to species that are independent or distinct because they have mutually exclusive characteristics namely the arrangements, shapes, and cross-section areas of the TIVs.
The requirement is still deemed proper and is therefore made FINAL.
Claims are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 1/8/2026.
Claim Objections
Claim 11 is objected to because of the following informalities: "perform". Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claim 10-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the first distribution layer" in line 3. There is insufficient antecedent basis for this limitation in the claim. Claims 11-15 are indefinite based on their dependency on claim 10.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7-8, 10-11, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (US 20170033062).
Regarding claim 1, Liu teaches a semiconductor package, comprising:
a first redistribution layer Fig. 7: 480-488 (see annotated Fig. 7);
a semiconductor die Fig. 7: 124 disposed on the first redistribution layer Fig. 7: 480-488, wherein an active surface Fig. 7: 130 of the semiconductor die Fig. 7: 124 faces the first redistribution layer Fig. 7: 480-488;
an interlink block Fig. 7: 172+174, disposed on the first redistribution layer Fig. 7: 480-488 and beside the semiconductor die Fig. 7: 124, wherein the interlink block Fig. 7: 172+174 includes an insulating encapsulant Fig. 7: 172 (para. 0042) and first through insulator vias (TIVs) Fig. 7: 174 penetrating through the insulating encapsulant Fig. 7: 172; and
a molding compound Fig. 7: 190, disposed on the first redistribution layer Fig. 7: 480-488 and laterally wrapping around the semiconductor die Fig. 7: 124 and the interlink block Fig. 7: 172+174,
wherein the interlink block Fig. 7: 172+174 is spaced apart from the semiconductor die Fig. 7: 124 with the molding compound Fig. 7: 190 there-between, and the first TIVs Fig. 7: 174 are isolated from the molding compound Fig. 7: 190 by the insulating encapsulant Fig. 7: 172, and
wherein the first TIVs Fig. 7: 174 are electrically connected with the first redistribution layer Fig. 7: 480-488 (para. 0073, connected via Fig. 7: 482).
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Regarding claim 2, Liu teaches the semiconductor package as claimed in claim 1, wherein a material of the insulating encapsulant Fig. 7: 172 is different from a material of the molding compound Fig. 7: 190 (para. 0042 teaches (i.e.) woven glass material for encapsulant, and para. 0046 teaches (i.e.) epoxy resin with filler material for molding compound).
Regarding claim 3, Liu teaches the semiconductor package as claimed in claim 1, wherein the molding compound Fig. 7: 190 fully covers sidewalls of the interlink block Fig. 7: 172+174, and there are interfaces between the insulating encapsulant Fig. 7: 172 of the interlink block Fig. 7: 172+174 and the molding compound Fig. 7: 190 surrounding the insulating encapsulant Fig. 7: 172. Para. 0043-0046 teach the encapsulant 172 and vias 174 are formed separately from and provided before the molding compound 190 is deposited, and the present application teaches the interfaces exist because the interlink blocks are formed and provided before the molding process of the molding compound (para. 0048 of the present application).
Regarding claim 4, Liu teaches the semiconductor package as claimed in claim 1, further comprising a second redistribution layer Fig. 7: 460-468 disposed on a backside surface of the semiconductor die Fig. 7: 124 opposite to the active surface Fig. 7: 130, over the interlink block Fig. 7: 172+174 and over the molding compound Fig. 7: 190, and the semiconductor die Fig. 7: 124 and the first and second redistribution layers are electrically connected through the first TIVs Fig. 7: 174 of the interlink block Fig. 7: 172+174 located there-between (para. 0072-0073).
Regarding claim 7, Liu teaches the semiconductor package as claimed in claim 1, wherein at least one of the first TIVs Fig. 7: 174 in the interlink block Fig. 7: 172+174 is in direct contact to a wiring layer Fig. 7: 482 of the first redistribution layer Fig. 7: 480-488.
Regarding claim 8, Liu teaches the semiconductor package as claimed in claim 1, wherein at least one of the first TIVs Fig. 7: 174 in the interlink block is in direct contact to a topmost via (i.e. via through Fig. 7: 480) of the first redistribution layer Fig. 7: 480-488.
Regarding claim 10, following the 112 rejection, the claim 10 limitation “the first distribution layer” will be interpreted as “the first redistribution layer.” Liu teaches a semiconductor package, comprising:
a first redistribution layer Fig. 7: 480-488 including a plurality of wiring layers Fig. 7: 480,482, 484, 486, 488;
a semiconductor die Fig. 7: 124 overlying the first REdistribution layer Fig. 7: 480-488;
an interlink block Fig. 7: 172+174, disposed beside the semiconductor die Fig. 7: 124 and overlying the first redistribution layer Fig. 7: 480-488, wherein the interlink block Fig. 7: 172+174 includes an encapsulant Fig. 7: 172 and a through insulation via Fig. 7: 174 extending through the encapsulant Fig. 7: 172, and the through insulation via Fig. 7: 174 directly contacts at least one of the plurality of wiring layers Fig. 7: 482 of the first redistribution layer Fig. 7: 480-488; and
a molding compound Fig. 7: 190 disposed between the semiconductor die Fig. 7: 124 and the interlink block Fig. 7: 172+174.
Regarding claim 11, Liu teaches the semiconductor package as claimed in claim 10, wherein the semiconductor die Fig. 7: 124 includes a first semiconductor die and a second semiconductor die perform different functions from the first semiconductor die (para. 0033).
Regarding claim 15, Liu teaches the semiconductor package as claimed in claim 10, wherein the molding compound Fig. 7: 190 laterally wraps the semiconductor die Fig. 7: 124 and the interlink block Fig. 7: 172+174 with interfaces between the interlink block Fig. 7: 172+174 and the molding compound Fig. 7: 190. Para. 0043-0046 teach the encapsulant 172 and vias 174 are formed separately from and provided before the molding compound 190 is deposited, and the present application teaches the interfaces exist because the interlink blocks are formed and provided before the molding process of the molding compound (para. 0048 of the present application).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20170033062) as applied to claim 1 above, and further in view of Mino et al. (US 20120018202).
Regarding claim 6, Liu teaches the semiconductor package as claimed in claim 1, wherein a material of the molding compound Fig. 7: 190 includes first fillers (para. 0046), a material of the insulating encapsulant Fig. 7: 172 includes second fillers (para. 0042), but does not explicitly teach wherein the first fillers have particle sizes larger than those of the second fillers. However, Mino teaches wherein the first fillers (of Fig. 1B: 2B) have particle sizes larger than those of the second fillers (of Fig. 1B: 2A). Mino teaches a first resin encapsulant Fig. 1B: 2A including a filler with particle size of approximately 75µm (para. 0031), and a second resin encapsulant Fig. 1B: 2B including a filler with a particle size of approximately 150µm (para. 0033). Mino teaches the first resin encapsulant 2A protecting metal wires (i.e. vias; para. 0032) has a filler with a smaller particle size than the second resin encapsulant to reduce thermal resistance and improve heat dissipation. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Liu’s and Mino’s teachings for the purpose of reducing thermal resistance in the molding compound and improving heat dissipation (para. 0033).
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20170033062) as applied to claim 1 above, and further in view of Tseng et al. (US 20210104485).
Regarding claim 5, although Liu teaches the substantial features of the claimed invention, Liu fails to explicitly teach the semiconductor package as claimed in claim 4, wherein the second redistribution layer includes a thermal dissipating pattern disposed over the semiconductor die and in contact with a semiconductor substrate of the semiconductor die. However, Tseng teaches the semiconductor package as claimed in claim 4, wherein the second redistribution layer Fig. 16: 180+190 includes a thermal dissipating pattern (para. 0052, “thermal management device”) disposed over the semiconductor die Fig. 16: 100c and in contact with a semiconductor substrate of the semiconductor die Fig. 16: 100c (shown in Fig. 16). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Liu and Tseng for the purpose of facilitating the dissipation of heat from the semiconductor chips (para. 0052).
Regarding claim 14, although Liu teaches the substantial features of the claimed invention, Liu fails to explicitly teach the semiconductor package as claimed in claim 10, further comprising a second redistribution layer having a thermal dissipating pattern, wherein the thermal dissipating pattern is disposed over the semiconductor die and in contact with a semiconductor substrate of the semiconductor die. However, Tseng teaches the semiconductor package as claimed in claim 10, further comprising a second redistribution layer Fig. 16: 180+190 having a thermal dissipating pattern (para. 0052, “thermal management device”), wherein the thermal dissipating pattern is disposed over the semiconductor die Fig. 16: 100c and in contact with a semiconductor substrate of the semiconductor die Fig. 16: 100c (shown in Fig. 16). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Liu and Tseng for the purpose of facilitating the dissipation of heat from the semiconductor chips (para. 0052).
Claims 9 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20170033062) as applied to claims 1 and 10 above, and further in view of Yew et al. (US 9,653,391).
Regarding claim 9, Liu teaches the semiconductor package as claimed in claim 1, further comprising another interlink block Fig. 7: 172+174 (opposite side of semiconductor die) including second TIVs Fig. 7: 174, wherein the first and second TIVs Fig. 7: 174 have substantially a same height (shown in Fig. 7), but Liu fails to explicitly teach wherein each first TIV has a cross-section area size different from that of each second TIV. However, Yew teaches wherein each first TIV Fig. 5: 103 has a cross-section area size different from that of each second TIV Fig. 5: 104 (col. 12, lines 44-47). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Liu’s and Yew’s teachings for the purpose of reducing stress or warpage caused by a coefficient of thermal expansion mismatch between the die, molding, and the RDL, preventing cracks (col. 3, lines 3-6).
Regarding claim 12, Liu teaches the semiconductor package as claimed in claim 10, wherein the interlink block Fig. 7: 172+174 include a first interlink block (left side of semiconductor die) including a first through insulation via Fig. 7: 174, and a second interlink block (right side of semiconductor die) including a second through insulation via Fig. 7: 174, the first interlink block and the second interlink block are arranged beside and around the semiconductor die Fig. 7: 124 (shown in Fig. 7), but Liu fails to explicitly teach wherein the first through insulation via has a cross-section area size different from that of the second through insulation via. However, Yew teaches wherein the first through insulation via Fig. 5: 103 (left side of semiconductor die) has a cross-section area size different from that of the second through insulation via Fig. 5: 104 (right side of semiconductor die) (col. 12, lines 44-47). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Liu’s and Yew’s teachings for the purpose of reducing stress or warpage caused by a coefficient of thermal expansion mismatch between the die, molding, and the RDL, preventing cracks (col. 3, lines 3-6).
Regarding claim 13, Liu teaches the semiconductor package as claimed in claim 10, wherein the through insulation vias Fig. 7: 172+174 include a first through insulation via Fig. 7: 174 and a second through insulation via Fig. 7: 174 inside the interlink block Fig. 7: 172 (both TIVs inside the interlink block on one side of the semiconductor die), but fails explicitly teach wherein the first through insulation via has a cross-section area size different from that of the second through insulation via. However, Yew teaches wherein the first through insulation via Fig. 5: 103 has a cross-section area size different from that of the second through insulation via Fig. 5: 104 (both TIVs on same side of the semiconductor die) (col. 12, lines 44-47). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Liu’s and Yew’s teachings for the purpose of reducing stress or warpage caused by a coefficient of thermal expansion mismatch between the die, molding, and the RDL, preventing cracks (col. 3, lines 3-6).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 February 11, 2026