DETAILED ACTION
This Notice is responsive to communication filed on 05/12/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 05/12/2026 has been acknowledged and entered into the record. Claim objection set forth in the previous Office Action has been overcome by amended claim 11. 112 Rejection set forth in the previous Office Action has been overcome by amended claim 10. Claims 12, and 16-20 have been cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claim(s) 1-4, 7-11, 13, 15, 21, 22, 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20170033062), and further in view of Yew et al. (US 9,653,391).
Regarding claim 1, Liu teaches a semiconductor package, comprising:
a first redistribution layer Fig. 7: 480-488 (see annotated Fig. 7);
a semiconductor die Fig. 7: 124 disposed on the first redistribution layer Fig. 7: 480-488, wherein an active surface Fig. 7: 130 of the semiconductor die Fig. 7: 124 faces the first redistribution layer Fig. 7: 480-488;
an interlink block Fig. 7: 172+174, disposed on the first redistribution layer Fig. 7: 480-488 and beside the semiconductor die Fig. 7: 124, wherein the interlink block Fig. 7: 172+174 includes an insulating encapsulant Fig. 7: 172 (para. 0042) and first through insulator vias (TIVs) Fig. 7: 174 and third TIVs Fig. 7: 174 (Fig. 3b shows multiple TIVs) penetrating through the insulating encapsulant Fig. 7: 172, and
the first TIV has a cross-section area size larger than that of the third TIV; and
a molding compound Fig. 7: 190, disposed on the first redistribution layer Fig. 7: 480-488 and laterally wrapping around the semiconductor die Fig. 7: 124 and the interlink block Fig. 7: 172+174,
wherein the interlink block Fig. 7: 172+174 is spaced apart from the semiconductor die Fig. 7: 124 with the molding compound Fig. 7: 190 there-between, and the first TIVs and the third TIVs Fig. 7: 174 are isolated from the molding compound Fig. 7: 190 by the insulating encapsulant Fig. 7: 172, and
wherein the first TIVs and the third TIVs Fig. 7: 174 are electrically connected with the first redistribution layer Fig. 7: 480-488 and the semiconductor die Fig. 7: 124 (para. 0073, connected via Fig. 7: 482).
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Yew teaches the following claim limitations not disclosed by Liu:
the first TIV Fig. 5: 104 has a cross-section area size larger than that of the third TIV Fig. 5: 103 (col. 12, lines 44-47).
Yew discloses an elongated member 104 (i.e. first TIV) that is configured to electrically connect to a conductive structure, and has a substantially greater cross section area than the via 103 (i.e. third TIV).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Liu with the teachings of Yew in order to have vias of different sizes for the purpose of reducing stress or warpage caused by a coefficient of thermal expansion mismatch between the die, molding and the redistribution layer, preventing cracks in the device (col. 3, lines 3-6).
Regarding claim 2, Liu teaches the semiconductor package as claimed in claim 1, wherein a material of the insulating encapsulant Fig. 7: 172 is different from a material of the molding compound Fig. 7: 190 (para. 0042 teaches (i.e.) woven glass material for encapsulant, and para. 0046 teaches (i.e.) epoxy resin with filler material for molding compound).
Regarding claim 3, Liu teaches the semiconductor package as claimed in claim 1, wherein the molding compound Fig. 7: 190 fully covers sidewalls of the interlink block Fig. 7: 172+174, and there are interfaces between the insulating encapsulant Fig. 7: 172 of the interlink block Fig. 7: 172+174 and the molding compound Fig. 7: 190 surrounding the insulating encapsulant Fig. 7: 172. Para. 0043-0046 teach the encapsulant 172 and vias 174 are formed separately from and provided before the molding compound 190 is deposited, and the present application teaches the interfaces exist because the interlink blocks are formed and provided before the molding process of the molding compound (para. 0048 of the present application).
Regarding claim 4, Liu teaches the semiconductor package as claimed in claim 1, further comprising a second redistribution layer Fig. 7: 460-468 disposed on a backside surface of the semiconductor die Fig. 7: 124 opposite to the active surface Fig. 7: 130, over the interlink block Fig. 7: 172+174 and over the molding compound Fig. 7: 190, and the semiconductor die Fig. 7: 124 and the first and second redistribution layers are electrically connected through the first TIVs and the third TIVs Fig. 7: 174 of the interlink block Fig. 7: 172+174 located there-between (para. 0072-0073).
Regarding claim 7, Liu teaches the semiconductor package as claimed in claim 1, wherein at least one of the first TIVs or at least one of the third TIVs Fig. 7: 174 in the interlink block Fig. 7: 172+174 is in direct contact to a wiring layer Fig. 7: 482 of the first redistribution layer Fig. 7: 480-488.
Regarding claim 8, Liu teaches the semiconductor package as claimed in claim 1, wherein at least one of the first TIVs or at least one of the third TIVs Fig. 7: 174 in the interlink block is in direct contact to a topmost via (i.e. via through Fig. 7: 480) of the first redistribution layer Fig. 7: 480-488.
Regarding claim 9, Liu teaches the semiconductor package as claimed in claim 1, further comprising:
another interlink block Fig. 7: 172+174 (opposite side of semiconductor die) including second TIVs Fig. 7: 174,
wherein the first and second TIVs Fig. 7: 174 have substantially a same height (shown in Fig. 7), and
each first TIV has a cross-section area size different from that of each second TIV.
Yew discloses the following claim limitation not disclosed by Liu:
each first TIV Fig. 5: 104 has a cross-section area size different from that of each second TIV Fig. 5: 103 (col. 12, lines 44-47).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Liu with the teachings of Yew in order to have vias of different sizes for the purpose of reducing stress or warpage caused by a coefficient of thermal expansion mismatch between the die, molding and the redistribution layer, preventing cracks in the device (col. 3, lines 3-6).
Regarding claim 10, Liu teaches a semiconductor package, comprising:
a first redistribution layer Fig. 7: 480-488 including a plurality of wiring layers Fig. 7: 480,482, 484, 486, 488;
a semiconductor die Fig. 7: 124 overlying the first redistribution layer Fig. 7: 480-488;
a first interlink block and a second interlink block Fig. 7: 172+174 (left side and right side of semiconductor die 124), disposed beside the semiconductor die Fig. 7: 124 and overlying the first redistribution layer Fig. 7: 480-488 (Fig. 5 top view shows multiple interlink blocks),
wherein the first interlink block Fig. 7: 172+174 includes a first encapsulant Fig. 7: 172 and a first through insulation via Fig. 7: 174 extending through the first encapsulant Fig. 7: 172,
the second interlink block Fig. 7: 172+174 includes a second encapsulant Fig. 7: 172 and a second through insulation via Fig. 7: 174 extending through the second encapsulant Fig. 7: 172, and
the first through insulation via has a cross-section area size different from that of the second through insulation via, and
the first and second through insulation vias Fig. 7: 174 directly contacting the plurality of wiring layers Fig. 7: 482 of the first redistribution layer Fig. 7: 480-488 are electrically connected with the semiconductor die Fig. 7: 124 through the plurality of wiring layers Fig. 7: 482 (para. 0073, connected via Fig. 7: 482); and
a molding compound Fig. 7: 190, disposed between the semiconductor die Fig. 7: 124 and the first and second interlink blocks Fig. 7: 172+174, and between the first and second encapsulants Fig. 7: 172 of the first and second interlink blocks Fig. 7: 172+174 (see Fig. 5),
wherein materials of the molding compound Fig. 7: 190 and the first and second encapsulants Fig. 7: 172 are different (para. 0042 teaches different materials for the first/second encapsulant; para. 0046 teaches different materials for the molding compound).
Yew teaches the following claim limitations not disclosed by Liu:
the first through insulation via Fig. 5: 104 has a cross-section area size different from that of the second through insulation via Fig. 5: 103 (col. 12, lines 44-47).
Yew discloses an elongated member 104 (i.e. first TIV) including metal, copper, that is configured to electrically connect to a conductive structure, and has a substantially greater cross section area than the via 103 (i.e. third TIV).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Liu with the teachings of Yew in order to have vias of different sizes for the purpose of reducing stress or warpage caused by a coefficient of thermal expansion mismatch between the die, molding and the redistribution layer, preventing cracks in the device (col. 3, lines 3-6).
Regarding claim 11, Liu teaches the semiconductor package as claimed in claim 10, wherein the semiconductor die Fig. 7: 124 includes a first semiconductor die and a second semiconductor die performing different functions from the first semiconductor die (para. 0033).
Regarding claim 13, Liu teaches the semiconductor package as claimed in claim 10, further comprising:
a third interlink block Fig. 7: 172+174 (see Fig. 5) disposed beside the semiconductor die Fig. 7: 124, beside the first and second interlink blocks Fig. 7: 172+174 and overlying the first redistribution layer Fig. 7: 480-488,
wherein the third interlink block Fig. 7: 172+174 includes a third through insulation via Fig. 7: 174 and a fourth through insulation via Fig. 7: 174 inside the third interlink block Fig. 7: 172 (vias are shown in the multiple interlink blocks of fig. 5 all beside the semiconductor die), and
the third through insulation via has a cross-section area size different from that of the fourth through insulation via.
Yew teaches the following claim limitations not disclosed by Liu:
the first through insulation via Fig. 5: 104 has a cross-section area size different from that of the second through insulation via Fig. 5: 103 (col. 12, lines 44-47).
Yew discloses an elongated member 104 (i.e. first TIV) including metal, copper, that is configured to electrically connect to a conductive structure, and has a substantially greater cross section area than the via 103 (i.e. third TIV).
Regarding claim 15, Liu teaches the semiconductor package as claimed in claim 13, wherein the molding compound Fig. 7: 190 laterally wraps the semiconductor die Fig. 7: 124 and the first, second and third interlink blocks Fig. 7: 172+174 (shown in Fig. 5) with interfaces between the first, second and third interlink blocks Fig. 7: 172+174 and the molding compound Fig. 7: 190. Para. 0043-0046 teach the encapsulant 172 and vias 174 are formed separately from and provided before the molding compound 190 is deposited, and the present application teaches the interfaces exist because the interlink blocks are formed and provided before the molding process of the molding compound (para. 0048 of the present application).
Regarding claim 21, Liu teaches a semiconductor package, comprising:
a first redistribution layer Fig. 7: 480-488;
a semiconductor die Fig. 7: 124 disposed on the first redistribution layer Fig. 7: 480-488,
wherein an active surface Fig. 7: 130 of the semiconductor die Fig. 7: 124 faces the first redistribution layer Fig. 7: 480-488;
a first interlink block Fig. 7: 172+174, disposed on the first redistribution layer Fig. 7: 480-488 and beside the semiconductor die Fig. 7: 124,
wherein the first interlink block Fig. 7: 172+174 includes a first encapsulant Fig. 7: 172 and a first through insulator via (TIV), a second TIV and a third TIV Fig. 7: 174 laterally wrapped by the first encapsulant Fig. 7: 172 (Fig. 5 shows multiple TIVs wrapped by the same encapsulant), and
the first TIV has a cross-section area size smaller than that of the second TIV or that of the third TIV, and
the first, second and third TIVs Fig. 7: 174 are electrically connected with the first redistribution layer Fig. 7: 480-488 and the semiconductor die Fig. 7: 124; and
a molding compound Fig. 7: 190, disposed on the first redistribution layer Fig. 7: 480-488 and laterally wrapping around the semiconductor die Fig. 7: 124 and the first interlink block Fig. 7: 172+174,
wherein the first interlink block Fig. 7: 172+174 is spaced apart from the semiconductor die Fig. 7: 124 with the molding compound Fig. 7: 190 there-between, and the first, second and third TIVs Fig. 7: 174 are separated from the molding compound Fig. 7: 190 by the first encapsulant Fig. 7: 172 (shown in Fig. 5).
Yew teaches the following claim limitations not disclosed by Liu:
the first TIV Fig. 5: 103 has a cross-section area size smaller than that of the second TIV or that of the third TIV Fig. 5: 104 (col. 12, lines 44-47).
Yew discloses an elongated member 104 (i.e. second or third TIV) including metal, copper, that is configured to electrically connect to a conductive structure, and has a substantially greater cross section area than the via 103 (i.e. first TIV).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Liu with the teachings of Yew in order to have vias of different sizes for the purpose of reducing stress or warpage caused by a coefficient of thermal expansion mismatch between the die, molding and the redistribution layer, preventing cracks in the device (col. 3, lines 3-6).
Regarding claim 22, Liu discloses the semiconductor package as claimed in claim 21, further comprising a second redistribution layer Fig. 7: 460-468 disposed on a backside surface of the semiconductor die Fig. 7: 124 opposite to the active surface Fig. 7: 130, over the first interlink block Fig. 7: 172+174 and over the molding compound Fig. 7: 190, and the semiconductor die Fig. 7: 124 and the first Fig. 7: 480-488 and second Fig. 7: 460-468 redistribution layers are electrically connected through the first, second and third TIVs Fig. 7: 174 of the first interlink block Fig. 7: 172+174 located there-between (para. 0072-0073).
Regarding claim 24, Liu discloses the semiconductor package as claimed in claim 21, further comprising:
a second interlink block Fig. 7: 172+174 including fourth TIVs Fig. 7: 174 laterally wrapped by a second encapsulant Fig. 7: 172 (see fig. 5 showing multiple interlink blocks with multiple TIVs enclosed in an encapsulant),
wherein the fourth TIVs Fig. 7: 174 have substantially a same height (shown in Fig. 7), and
each fourth TIV has a cross-section area size larger than that of the first TIV and different from that of the second TIV or that of the third TIV.
Yew teaches the following claim limitations not disclosed by Liu:
each fourth TIV Fig. 5: 104 has a cross-section area size larger than that of the first TIV and different from that of the second TIV or that of the third TIV Fig. 5: 104 (col. 12, lines 44-47).
Yew discloses an elongated member 104 (i.e. second or third TIV) including metal, copper, that is configured to electrically connect to a conductive structure, and has a substantially greater cross section area than the via 103 (i.e. first TIV). Yew also teaches (see Fig. 3) the elongated members 104 can have different cross section shapes, heights and areas (col. 6, lines 13-29).
Regarding claim 25, Liu discloses the semiconductor package as claimed in claim 24, further comprising:
a third interlink block Fig. 7: 172+174 including a fifth TIV Fig. 7: 174 and a six TIV Fig. 7: 174 laterally wrapped by a third encapsulant Fig. 7: 172 (see Fig. 5),
wherein the fifth and sixth TIVs Fig. 7: 174 have substantially a same height (shown in Fig. 7), and
the fifth TIV has a cross-section area size larger than that of the sixth TIV.
Yew discloses the following claim limitations not disclosed by Liu:
the fifth TIV Fig. 5: 104 has a cross-section area size larger than that of the sixth TIV Fig. 5: 103 (col. 12, lines 44-47).
Yew discloses an elongated member 104 (i.e. second or third TIV) including metal, copper, that is configured to electrically connect to a conductive structure, and has a substantially greater cross section area than the via 103 (i.e. first TIV).
Regarding claim 26, Liu discloses the semiconductor package as claimed in claim 25, wherein a material of the molding compound Fig. 7: 190 is different from materials of the first, second and third encapsulants Fig. 7: 172 (para. 0042 teaches different materials for the first/second encapsulant; para. 0046 teaches different materials for the molding compound).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20170033062) and Yew et al. (US 9653391) as applied to claim 1 above, and further in view of Mino et al. (US 20120018202).
Regarding claim 6, Liu teaches the semiconductor package as claimed in claim 1:
wherein a material of the molding compound Fig. 7: 190 includes first fillers (para. 0046),
a material of the insulating encapsulant Fig. 7: 172 includes second fillers (para. 0042), and
the first fillers have particle sizes larger than those of the second fillers.
Mino teaches the following claim limitations not disclosed by Liu or Yew:
the first fillers (of Fig. 1B: 2B) have particle sizes larger than those of the second fillers (of Fig. 1B: 2A).
Mino teaches a first resin encapsulant Fig. 1B: 2A including a filler with particle size of approximately 75µm (para. 0031), and a second resin encapsulant Fig. 1B: 2B including a filler with a particle size of approximately 150µm (para. 0033). Mino teaches the first resin encapsulant 2A protecting metal wires (i.e. vias; para. 0032) has a filler with a smaller particle size than the second resin encapsulant to reduce thermal resistance and improve heat dissipation.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Liu’s and Mino’s teachings for the purpose of reducing thermal resistance in the molding compound and improving heat dissipation (para. 0033).
Claims 5, 14, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20170033062) and Yew et al. (US 9653391) as applied to claims 1 and 10 above, and further in view of Chen (US 20240064901).
Regarding claim 5, Liu teaches the semiconductor package as claimed in claim 4, wherein:
the second redistribution layer Fig. 7: 460-468 includes a dielectric layer Fig. 7: 460 (para. 0072) and
a thermal dissipating pattern embedded in the dielectric layer, and
the thermal dissipating pattern is in contact with a semiconductor substrate of the semiconductor die.
Chen teaches the following claim limitations not disclosed by Liu or Yew:
a thermal dissipating pattern Fig. 26: 300+140D+123 embedded in the dielectric layer Fig. 26: 121, and
the thermal dissipating pattern Fig. 26: 300+140D+123 is in contact with a semiconductor substrate of the semiconductor die Fig. 26: 200 (shown in Fig. 26).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Liu and Yew, with the teachings of Chen in order to avoid using additional power consumption for the heat dissipation assembly, and include a control system that turns on or turns off the heat dissipation assembly based on the temperature change of the chip (para. 0003-0004).
Regarding claim 14, Liu teaches the semiconductor package as claimed in claim 10, further comprising:
a second redistribution layer Fig. 7: 460-468 having a dielectric layer Fig. 7: 460 (para. 0072) and
a thermal dissipating pattern embedded in the dielectric layer,
wherein the thermal dissipating pattern is disposed over the semiconductor die and in contact with a semiconductor substrate of the semiconductor die.
Chen teaches the following claim limitations not disclosed by Liu or Yew:
a thermal dissipating pattern Fig. 26: 300+140D+123 embedded in the dielectric layer Fig. 26: 121,
wherein the thermal dissipating pattern Fig. 26: 300+140D+123 is disposed over the semiconductor die Fig. 26: 200 in contact with a semiconductor substrate of the semiconductor die Fig. 26: 200 (shown in Fig. 26).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Liu and Yew, with the teachings of Chen in order to avoid using additional power consumption for the heat dissipation assembly, and include a control system that turns on or turns off the heat dissipation assembly based on the temperature change of the chip (para. 0003-0004).
Regarding claim 23, Liu teaches the semiconductor package as claimed in claim 22, wherein:
the second redistribution layer Fig. 7: 460-468 includes a dielectric layer Fig. 7: 460 (para. 0072) and
a thermal dissipating pattern embedded in the dielectric layer, and
the thermal dissipating pattern is in contact with a semiconductor substrate of the semiconductor die.
Chen teaches the following claim limitations not disclosed by Liu or Yew:
a thermal dissipating pattern Fig. 26: 300+140D+123 embedded in the dielectric layer Fig. 26: 121, and
the thermal dissipating pattern Fig. 26: 300+140D+123 is in contact with a semiconductor substrate of the semiconductor die Fig. 26: 200 (shown in Fig. 26).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Liu and Yew, with the teachings of Chen in order to avoid using additional power consumption for the heat dissipation assembly, and include a control system that turns on or turns off the heat dissipation assembly based on the temperature change of the chip (para. 0003-0004).
Response to Arguments
Applicant’s arguments with respect to claim(s) 10-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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