DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support in the specification for the claim limitations of "a first capacitor contact structure and a second capacitor contact structure, … located on opposite sides of an entirety of the first word line and the second word line collectively", as recited in claim 1 (note: Fig. 1 shows a left one capacitor contact structure located on a portion of a side of a left one word line and a right one capacitor contact structure located on a portion of a side of a right one word line); “the line layer covering outer surfaces of entire of the outer walls”, as recited in claim 3 (Fig. 1B shows a top surface (one of outer surfaces) of each outer wall is exposed from the liner layer).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of "an entirety of the first word line and the second word line collectively", as recited in claim 1, is unclear as to an entirety of which element applicant refers.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-9, as best understood, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tonari et al. (2016/0118388).
As for claim 1, Tonari et al. show in Figs. 10, 12, 14, 25 and related text a memory device, comprising:
a semiconductor substrate 1, having a first active region A and a second active region separated A by a trench isolation structure 2 (Fig. 10);
a first word line 7/8/9 and a second word line7/8/9, embedded in the semiconductor substrate, wherein the first word line and the second word line are spaced from each other in a first direction and from a top view, a length of the first word line and a length of the second word line extend along a second direction and penetrate the first active region and the second active region, wherein the first active region and the second active region are spaced from each other in both the first direction and the second direction, wherein the second direction is orthogonal to the first direction (Fig. 12);
a first capacitor contact structure 22A and a second capacitor contact structure 22B, disposed on the semiconductor substrate and located on opposite sides of an entirety of the first word line and the second word line collectively, wherein the first capacitor contact structure overlaps and is connected to the first active region, the second capacitor contact structure overlaps and is electrically connected to the second active region, and the first capacitor contact structure and the second capacitor contact structure are arranged along the first direction; and
an isolation wall 16F/19, two opposite sides of the isolation wall contacting the first capacitor contact structure and the second capacitor contact structure, and the isolation wall comprises a wall structure 16F/(inner portion of) 19 and a liner layer (outer portion of) 19, wherein the wall structure comprises an inner wall 16F and outer walls (inner portion of) 19 covering two opposite sides of the inner wall, wherein an insulation material of the inner wall has an etch selectivity with respect to an insulation material of the outer walls ([0072]; [0078]).
As for claim 2, Tonari et al. show the isolation wall overlaps the first word line, the second word line, and the trench isolation structure (Fig. 25).
As for claim 3, Tonari et al. show the liner layer (outer portion of) 19 covering outer surfaces of entire of the outer walls (Fig. 25).
As for claim 4, Tonari et al. show the liner layer of the isolation wall is in direct contact with the first capacitor contact structure and the second capacitor contact structure (Fig. 25).
As for claim 5, Tonari et al. show a top surface of the inner wall, top surfaces of the outer walls, and a topmost portion of the liner layer are coplanar and collectively define a top surface of the isolation wall (Fig. 25).
As for claim 6, Tonari et al. show a top surface of the isolation wall is coplanar with a top surface of the first capacitor contact structure and a top surface of the second capacitor contact structure (Fig. 25).
As for claim 7, Tonari et al. show from the top view, a length of a first bit line 12 and from the top view, a length of a second bit line 12 extend above the semiconductor substrate along the first direction, wherein the first bit line intersects the first active region, and the second bit line intersects the second active region (Fig. 14).
As for claim 8, Tonari et al. show wherein the isolation wall is located between the first bit line and the second bit line (Fig. 25).
As for claim 9, Tonari et al. show a top surface of the first capacitor contact structure, a top surface of the second capacitor contact structure, and a top surface of the isolation wall are higher than a top surface of the first bit line and a top surface of the second bit line (Fig. 25).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 10, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Tonari et al. (2016/0118388).
Tonari et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, except the insulation material of the inner wall of the isolation wall comprises silicon nitride, and the insulation material of the outer walls of the isolation wall comprises silicon oxide.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use silicon nitride as the insulation material of the inner wall of the isolation wall and use silicon oxide as the insulation material of the outer walls of the isolation wall, in order to reduce charge traps and leakage, improve thermal and chemical stability and improve interface quality.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Response to Arguments
Applicant's arguments filed January 14, 2026 have been fully considered but they are not persuasive.
Applicant argues that “Tonari at least fails to disclose the features "the isolation wall comprises a wall structure and a liner layer, wherein the wall structure comprises an inner wall and outer walls covering two opposite sides of the inner wall" recited in the amended claim 1” because “the liner layer, the inner wall, and the outer wall are three distinct layer, and more particularly, the outer wall and the liner layer are two different layers. On the contrary, as shown in FIG. 25(A) of Tonari, second side wall 19 is one single layer. Clearly, the configuration of Tonari is different from the configuration in the present application”.
The examiner respectfully disagrees because broad limitation does not require the outer wall and the liner layer to be made from different materials. An observer would not be able to distinguish the border between regions (i.e. “outer walls” and “liner layer”) within a structure made of the same (or homogeneous) materials in a final product. Therefore, the claim limitations of “outer walls” and “liner layer” could be arbitrarily chosen within the layer 19 of Tonari’s device.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM.
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/MEIYA LI/Primary Examiner, Art Unit 2811
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