DETAILED ACTION 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 2. This Non-Final office action is in response to application 18/325,233 , application filed on 05/30/2023 . 3. Claims 1- 20 are currently pending in this application. Information Disclosure Statement 4. The information disclosure statement (IDS) submitted on 05/30/ 2023 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . 6. Claim(s) 1- 2, 5-8, 11-12, 15-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over NAZARATHY et al. ( US PG Pub No. 2017/0192408) in view of STOFFER (US PG Pub No. 2023 / 0083003 ) . 7. With respect to independent claim s 1 , 11 and 20 , NAZARATH Y teaches : an interface device ( see probe, Fig 1 at 112; see I/O interfaces including probes, para 149 ) receiving an output expression ( see observation of optical paths, expression values, para 172 ) , wherein the output expression at least specifies a virtual optical probing function ( function that represents a probe point, para 11 ) of multiple virtual optical probing functions (see multiple probe points and corresponding functions, para 11) ; and a processor in communication with the interface devic e (processor in communication with the probe, para 24-31) , wherein, in response to the output expression, the processor accesses results of at least one simulation of the photonic integrated circuit and executes the virtual optical probing function ( simulations used to determine probing points and probing functions/expressions, para 148-159 ) to calculate and output an optical signal parameter value for the - net b a sed on the results ( see determining and storing tuning parameters, para 148-159 ) . NAZARATH Y appears to be silent regarding: a net in a netlist for a photonic integrated circuit; accessing a storage medium storing the netlist. However, STOFFER teaches: a net in a netlist for a photonic integrated circuit ( see PIC design, path between two optical nets, para 20 ) ; accessing a storage medium storing the netlist ( see netlist, storing netlist, 76-78 ) . It would have been obvious to one of ordinary skill in the art before the time of the invention to have incorporated STOFFER’s netlist design of a photonic circui t into the invention of NAZARATHY because it is well known in the art that circuit simulations pair with their corresponding design netlists in order to improve designs over time. 8. With respect to claim s 2 and 12 , NAZARATH Y teaches : wherein, within the output expression, the virtual optical probing function is defined as one of a function for calculation of power in decibel-milliwatts of an optical signal on the net, a function for calculation of power in milliwatts of the optical signal on the net, a function for calculation of amplitude in volts/meter of the optical signal on the net, a function for calculation of signal phase in degrees of the optical signal on the net, and a function for calculation of signal phase in radians of the optical signal on the net ( tuning voltages, tuning phases, radians/degrees, para 149-158 ) . 9 . With respect to claim s 5 and 15 , NAZARATH Y teaches : wherein the interface device comprises a monitor displaying a graphic user interface including a depiction of at least a section of a schematic diagram of the photonic integrated circuit ( see optimal operating points identified in design, para 399-410 ) , and wherein the optical signal parameter value is output as a notation on the depiction ( see notation of probe point in design, para 399-410 ) . 1 0 . With respect to claim s 6 and 16 , NAZARATH Y teaches : wherein the depiction is customizable to enable different combinations of notations of optical parameter values thereon ( see identification/notation of optical parameter operating points, para 179-199 ) . 1 1 . With respect to claim s 7 and 17 , NAZARATH Y teaches : wherein the processor further performs the at least one simulation of the photonic integrated circuit and stores the results, wherein the at least one simulation includes forward and reverse signal propagation simulation ( reversal of signals, para 389-393 ) . 1 2 . With respect to claim s 8 and 18 , NAZARATH Y teaches : wherein the output expression further indicates a signal propagation direction, and, within the output expression, the signal propagation direction is defined as one of forward signal propagation and reverse signal propagation ( reversal of signals during propagation simulation, para 389-393 ) . Allowable Subject Matter 13 . Claim s 3-4, 9-10 and 13-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 14 . With respect to claims 3 and 13 , the prior art made of record fails to teach the combination of steps recited in claim s 3 and 13 , including the following particular combination of steps as recited in claim 3 and similarly recited in claim 13 , as follows: wherein the output expression further defines an optical signal mode and a simulation type, and wherein, within the output expression, the optical signal mode is defined as one of a transverse electric mode and a transverse magnetic mode and the simulation type is defined as one of a direct current simulation and a transient simulation. 15 . With respect to claims 4 and 14 , the prior art made of record fails to teach the combination of steps recited in claim s 4 and 14 , including the following particular combination of steps as recited in claim 4 and similarly recited in claim 14 , as follows: wherein the interface device comprises a monitor displaying a graphic user interface, wherein the output expression is received through the graphic user interface, and wherein the output expression is as any one of: user-drafted; user-selected from a displayed index listing all output expressions; user-selected from displayed drop-down windows for each output expression component; and user-selected from a displayed drop-down window following activation of a net-specific hyperlink on a displayed circuit diagram. 16 . With respect to claim 9 , the prior art made of record fails to teach the combination of steps recited in claim 9 , including the following particular combination of steps as recited in claim 9 , as follows: wherein storage medium further stores a process design kit including a library of cells and a simulation program, wherein the library of cells includes photonic device cells selectable for inclusion in the design, wherein each photonic device cell includes a component description defining ten pins at each terminal that emits or receives light signals with five of the ten pins being associated with components of forward signal propagation and five of the ten pins being associated with components of reverse signal propagation, and wherein the simulation program is executable by the processor to perform the forward and reverse signal propagation simulation using the ten pins. 17 . With respect to claim 10 , the prior art made of record fails to teach the combination of steps recited in claim 1 0 , including the following particular combination of steps as recited in claim 1 0 , as follows: wherein the net is between two photonic device cells including a light emitting device and a light receiving device, wherein the light emitting device has ten output pins and the light receiving device has ten input pins, and wherein the ten output pins are paired with the ten input pins and include: a pair of pins for transverse electric mode and real component of the forward signal propagation; a pair of pins for transverse electric mode and imaginary component of the forward signal propagation; a pair of pins for transverse magnetic mode and real component of the forward signal propagation; a pair of pins for transverse magnetic mode and imaginary component of the forward signal propagation; and a pair of pins for wavelength of the forward signal propagation; a pair of pins for transverse electric mode and real component of the reverse signal propagation; a pair of pins for transverse electric mode and imaginary component of the reverse signal propagation; a pair of pins for transverse magnetic mode and real component of the reverse signal propagation; a pair of pins for transverse magnetic mode and imaginary component of the reverse signal propagation; and a pair of pins for wavelength of the reverse signal propagation. 18 . With respect to claim 19 , the prior art made of record fails to teach the combination of steps recited in claim 19 , including the following particular combination of steps as recited in claim 19 , as follows: wherein the storage medium stores a process design kit including a library of cells and a simulation program, wherein the library of cells includes photonic device cells selectable for inclusion in the design, wherein each photonic device cell includes a component description defining ten pins at each terminal that emits or receives light signals with five of the ten pins being associated with components of forward signal propagation and five of the ten pins being associated with components of reverse signal propagation, wherein the simulation program is executable by the processor to perform the forward signal propagation simulation and the reverse signal propagation simulation using the ten pins, wherein the net is between two photonic device cells including a light emitting device and a light receiving device, wherein the light emitting device has ten output pins and the light receiving device has ten input pins, and wherein the ten output pins are paired with the ten input pins and include: a pair of pins for transverse electric mode and real component of the forward signal propagation; a pair of pins for transverse electric mode and imaginary component of the forward signal propagation; a pair of pins for transverse magnetic mode and real component of the forward signal propagation; a pair of pins for transverse magnetic mode and imaginary component of the forward signal propagation; and a pair of pins for wavelength of the forward signal propagation; a pair of pins for transverse electric mode and real component of the reverse signal propagation; a pair of pins for transverse electric mode and imaginary component of the reverse signal propagation; a pair of pins for transverse magnetic mode and real component of the reverse signal propagation; a pair of pins for transverse magnetic mode and imaginary component of the reverse signal propagation; and a pair of pins for wavelength of the reverse signal propagation. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov . Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUCHIN PARIHAR/ Primary Examiner, Art Unit 2851