DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 & 13-28 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2022/0165776) by Lin et al (“Lin”) in view of (US-2021/0225916) by Hsieh et al (“Hsieh”).
Regarding claim 1, Lin discloses in FIG. 3 and related text, e.g., a semiconductor device, comprising:
A pixel sensor array (FIG. 3, 200) comprising at least one pixel sensor (326); and
an optical blocking region (302 “metal shield region”; hence, “optical blocking”) adjacent to pixel sensor array, the optical blocking region comprising:
a substrate (324);
a dielectric layer (334) over the substrate; and
a metal layer (336), over the dielectric layer, the metal layer being patterned in the optical blocking region into a nanoscale grid (see metal 336 in region 302; it is formed in the form of a grid; as far as “nano” part thereof, this refers to the scale of semiconductor process; meaning, that the elements involved are measured in nanometers; please note the date of the Lin’s reference (2022); the devices that are formed in 2022 are notoriously well-known to be formed on nanoscale; hence, meeting limitations of nanoscale grid) comprising a plurality of metal structures (see 336 in region 302; multiple “metal structures” are shown) and a plurality of nanoscale openings between the metal structures (see 336 in region 302; 2 openings are shown), wherein the nanoscale grid is and configured to reflect light away from the at least one pixel sensor (302 region is “metal shield” region; hence, “reflect light away”).
Lin does not explicitly state “an optical blocking region adjacent to and completely surrounding pixel sensor array”.
Maybe Lin has it and maybe does not. However, Hsieh fixes the deficiency.
Hsieh discloses in FIGs. 1A-C and related text, e.g., “an optical blocking region (FIG. 1A, 104) adjacent to and completely surrounding pixel sensor array (102)”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Lin with “an optical blocking region adjacent to and completely surrounding pixel sensor array” as taught by Hsieh, in order to allow for the number and variety of reference pixels (see par. 17 and FIG. 1B; 4 pixels are shown; 2 of them have one “light level” and 2 have another “light level”) all around the pixel array, thus guaranteeing an optimum reference indicator over the entire chip.
Regarding claim 2, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, but do not explicitly state “each of the plurality of metal structures has a width in a range from approximately 100 nanometers (nm) to approximately 200 nm”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Lin and Hsieh with “each of the plurality of metal structures has a width in a range from approximately 100 nanometers (nm) to approximately 200 nm”, as a matter of obvious choice in view of march of technology; as is known to any reasonably informed member of the public, semiconductor industry is constantly shrinking the sizes of its devices, from arbitrarily larger sizes to arbitrarily smaller ones, over a period of 12-18 months (colloquially known as “Moore’s Law”, and it is often enough publicly discussed in popular media; hence, “any reasonably informed member of the public”); therefore, as feature sizes shrink, from arbitrarily large numbers to arbitrarily small numbers, skilled artisan would be drawn to the cited feature sizes, simply as a matter of march of technology, with no further consideration needed.
A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 3, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., further comprising: a portion of the metal layer (portion of 336), between the nanoscale grid and the at least one pixel sensor, that is connected to the substrate for grounding (note that 2 connections that 336 makes directly to substrate 324; these portions are between the grid and 326; these portions are also “connected to the substrate for grounding”, since substrate is notoriously well-known to be grounded).
Regarding claim 4, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., further comprising:
an isolation structure (328) around at least one photodiode of the at least one pixel sensor; and a metal grid (unmarked portion of 336 directly above 324; it is marked as 172 in FIG. 1C of Hsieh) over the isolation structure.
Regarding claim 13, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., a semiconductor device, comprising:
A pixel sensor array comprising at least one pixel sensor (see claim 1); and
an optical blocking region adjacent to and completely surrounding the pixel sensor array (see claim 1), the optical blocking region comprising:
a substrate (see claim 1) including a sensing region in the optical blocking region (Lin teaches “reference pixel” for the region in par. 33; Hsieh teaches at least 4 columns of them (see FIG. 1B);
a dielectric layer over the substrate (see claim 1) and including a recessed in the optical blocking region (layer 334 has such recesses in region 302; see FIG. 3); and
a metal layer, over the dielectric layer (see claim 1) and over the sensing region (in combined device), conforming to the recessed pattern (see FIG. 3; it conforms to it, by going into every opening) and configured to prevent light from entering the sensing region and to reflect light away from the at least one pixel sensor (this is the whole point of Hsieh’s reference pixels; see claim 1),
wherein the metal layer additionally forms a metal grid over an isolation structure (as was discussed in claim 4) that at least partially surrounds at least one photodiode of the at least one pixel sensor (see the cited figures of both Lin and Hsieh; they both show it).
Regarding claim 14, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., the metal grid follows the recessed pattern (see FIG. 3 of Lin; the grid is specifically outside the recesses in 334; thus, “follows the recessed pattern”).
Regarding claim 15, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., wherein the substrate includes the recessed pattern under the dielectric layer (see FIG. 3, directly under 342a and directly above 326; there substrate meets the limitations).
Regarding claim 16, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., wherein the recessed pattern in the substrate includes a plurality of high absorption (HA) regions, that are approximately pyramidal (see claim 15; those patterns qualify as “high absorption regions”; see par. 45).
Regarding claim 17, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, but does not explicitly state “wherein each of the HA regions is associated with an angle in a range from approximately 54 degrees to approximately 55 degrees“.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Lin and Hsieh with “wherein each of the HA regions is associated with an angle in a range from approximately 54 degrees to approximately 55 degrees“, in order to achieve a particularly desired amount light reflection (a “result effective variable” [Wingdings font/0xE0] light reflection is the whole point (as pars. 45-46 make clear); hence, finding a proper amount of light reflection is needed; hence, finding proper angle is also needed, since it affects the result, per high school physics) inside the pixel sensor (Lin makes clear the purpose of the HA regions in par. 46 and so on; then it becomes a matter of routine optimization to find the proper angle for a specific design; a POSITA who would search for that proper angle would arrive at stated values, simply through routine optimization).
It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Regarding claim 18, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., wherein the recessed pattern in the substrate includes a plurality of shallow isolation structures (various 328’s are marked as “DTI”; however, they do not go all the way down to the bottom of substrate; hence, they are shallow DTI; hence “shallow isolation structures”; please note that Applicant’s specification uses same language (“shallow DTI”)).
Regarding claim 19, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, except “wherein each of the shallow isolation structures has a depth in a range from approximately 0.5 micrometers ( um) to approximately 6.0 um”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Lin and Hsieh with “wherein each of the shallow isolation structures has a depth in a range from approximately 0.5 micrometers ( um) to approximately 6.0 um”, as a matter of obvious choice in view of march of technology; as is known to any reasonably informed member of the public, semiconductor industry is constantly shrinking the sizes of its devices, from arbitrarily larger sizes to arbitrarily smaller ones, over a period of 12-18 months (colloquially known as “Moore’s Law”, and it is often enough publicly discussed in popular media; hence, “any reasonably informed member of the public”); therefore, as feature sizes shrink, from arbitrarily large numbers to arbitrarily small numbers, skilled artisan would be drawn to the cited feature sizes, simply as a matter of march of technology, with no further consideration needed.
A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 20, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., further comprising:
a portion of the metal layer, adjacent to the at least one pixel sensor, that is connected to the substrate for grounding (see claim 3).
Regarding claim 21, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., a semiconductor device, comprising:
a pixel sensor array comprising at least one pixel sensor, the at least one pixel sensor comprising at least one photodiode (see claim 1; 326 is specifically the photodiode of individual pixel);
a substrate including the at least one photodiode (see claim 1);
an isolation structure (324) in the substrate and surrounding the at least one photodiode (it is a grid);
an optical blocking region (see claim 1) adjacent to the isolation structure (see FIG. 3), the optical blocking region being adjacent and completely surrounding the pixel sensor array (see claim 1) and comprising a sensing region in the substrate (see claim 13) and a recessed pattern in the substrate (see claim 15; the claim does not explicitly state that the “recessed pattern in the substrate has to be in “the optical blocking region”; this specific limitation can be read two ways; some Examiners give “grammatical 112 indefinite” for this; this Examiner just demonstrates alternative reading of limitations; alternatively, if Applicant wishes to argue, see US-2021/0384247, FIG. 12, 476; these are vias, which go into substrate in order to make electrical connection (pars. 63, 67); hence, “optical blocking region”, “recessed pattern in the substrate”, and motivation to combine [Wingdings font/0xE0] to make electrical connection, to reduce noise and the dark current (par. 63); also note that if Applicant wishes to argue, then Applicant specifically contradicts claim 22; maybe this thing warrants 112, indefinite rejection; please review);
a dielectric layer (see claim 1) over the isolation structure and the recessed pattern (see FIG. 3); and
a metal layer over the dielectric layer (see claim 1) and over the sensing region (it is above everything), the metal layer conforming to the recessed pattern in the optical blocking region (see claim 13) and configured to prevent light from entering the sensing region and to reflect light away from the at least one pixel sensor (see claim 13).
Regarding claim 22, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., wherein the recessed pattern comprises a plurality of high absorption (HA) regions formed in the substrate that are approximately pyramidal (see claim 16; also, please note that this wording of claim 22, specifically precludes the other reading of claim 21 (section in bold italics); recessed pattern has to be outside optical blocking region, in order to be “high absorption”).
Regarding claim 23, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., wherein each of the plurality of HA regions is associated with an angle in a range from approximately 54 degrees to approximately 55 degrees (see claim 17).
Regarding claim 24, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., wherein the recessed pattern comprises a plurality of shallow isolation structures in the substrate (see claim 18).
Regarding claim 25, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., substantially the entire claim structure, as recited in above claims, except “wherein each of the plurality of shallow isolation structures has a width in a range from approximately 100 nanometers (nm) to approximately 400 nm”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Lin and Hsieh with “wherein each of the plurality of shallow isolation structures has a width in a range from approximately 100 nanometers (nm) to approximately 400 nm”, as a matter of obvious choice in view of march of technology; as is known to any reasonably informed member of the public, semiconductor industry is constantly shrinking the sizes of its devices, from arbitrarily larger sizes to arbitrarily smaller ones, over a period of 12-18 months (colloquially known as “Moore’s Law”, and it is often enough publicly discussed in popular media; hence, “any reasonably informed member of the public”); therefore, as feature sizes shrink, from arbitrarily large numbers to arbitrarily small numbers, skilled artisan would be drawn to the cited feature sizes, simply as a matter of march of technology, with no further consideration needed.
A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 26, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., wherein the dielectric layer conforms to the recessed pattern (see FIG. 3).
Regarding claim 27, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., wherein the metal layer comprises an electrical pad over an electrical pad region (note: this appears to be an attempt to claim the process steps of FIG. 5E, and par. 98 of Specification, where one metal layer is formed on “optical black” region and “electrical pad” region; however, it is shown to be separate structures in the end (318 and 336); hence, these limitations, if Examiner understands them correctly, are not patentable in a claim drawn to device).
Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Alternatively, in order to remove all arguments, it would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Lin and Hsieh with “wherein the metal layer comprises an electrical pad over an electrical pad region”, in order to simplify the processing steps of making device, by reducing a number of manufacturing steps, by forming two separate structures in a single manufacturing step (it is a notoriously well-known way to simplify the processing steps [Wingdings font/0xE0] just do two separate structures simultaneously).
Regarding claim 28, the combined device of Lin and Hsieh disclose in cited figures and related text, e.g., wherein the metal layer comprises a grounding node (see claim 3; also, see FIG. 1C of Hsieh, 174E; it is also a grounding node), adjacent to the at least one photodiode (see figures of Lin and Hsieh; both meet limitations), that is electrically connected to the substrate (see figures of Lin and Hsieh).
Response to Arguments
Applicant’s arguments with respect to above claims have been considered but are moot because the arguments do not apply to the current rejection.
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
09/30/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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