DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US-2022/0165776) by Lin et al (“Lin”).
Regarding claim 1, Lin discloses in FIG. 3 and related text, e.g., a semiconductor device, comprising:
at least one pixel sensor (326); and
an optical blocking region (302), adjacent to the at least one pixel sensor, comprising:
a substrate (324);
a dielectric layer (332 and/or 334 read on the limitation) over the substrate; and
a metal layer (336), over the dielectric layer, including a nanoscale grid (see metal 336 in region 302; it is formed in the form of a grid; as far as “nano” part thereof, this refers to the scale of semiconductor process; meaning, that the elements involved are measured in nanometers; please note the date of the Lin’s reference (2022); the devices that are formed in 2022 are notoriously well-known to be formed on nanoscale; hence, meeting limitations of nanoscale grid) and configured to reflect light away from the at least one pixel sensor (302 region is “metal shield” region; hence, “reflect light away”).
Regarding claim 3, Lin discloses in FIG. 3 and related text, e.g., further comprising: a portion of the metal layer (portion of 336), between the nanoscale grid and the at least one pixel sensor, that is connected to the substrate for grounding (note that 2 connections that 336 makes directly to substrate 324; these portions are between the grid and 326; these portions are also “connected to the substrate for grounding”, since substrate is notoriously well-known to be grounded).
Regarding claim 4, Lin discloses in FIG. 3 and related text, e.g., further comprising:
an isolation structure (328) around at least one photodiode of the at least one pixel sensor; and a metal grid (unmarked portion of 336 directly above 324) over the isolation structure.
Claims 13-15, 18, 20-21, 24, 26 & 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by (US-2021/0384247) by Cheng et al (“Cheng”).
Regarding claim 13, Cheng discloses in FIG. 12 and related text, e.g., a semiconductor device, comprising:
at least one pixel sensor (406); and
an optical blocking region (directly in-between 402a and 402b), adjacent to the at least one pixel sensor, comprising:
a substrate (404);
a dielectric layer (436 and/or 438) over the substrate and including a recessed pattern (404 is recessed in the area of 476); and
a metal layer (472), over the dielectric layer, conforming to the recessed pattern (see FIG. 12) and configured to reflect light away from the at least one pixel sensor (472 is metal; any light that hits it, will not reach 406, but will reflect away, per physics; hence “reflects light away”), wherein the metal layer additionally forms a metal grid over an isolation structure (unmarked portions of 472 over various 434’s, which are in grid form) that at least partially surrounds at least one photodiode of the at least one pixel sensor (the whole of 470 (including the 472 and 434 are formed in grid form; see par. 62, etc.).
Regarding claim 14, Cheng discloses in FIG. 12 and related text, e.g., the metal grid follows the recessed pattern (see 476; the portion of metal grid, follow the pattern).
Regarding claim 15, Cheng discloses in FIG. 12 and related text, e.g., wherein the substrate includes the recessed pattern under the dielectric layer (see 476; it is under 436/438).
Regarding claim 18, Cheng discloses in FIG. 12 and related text, e.g., wherein the recessed pattern in the substrate includes a plurality of shallow isolation structures (various 434’s are marked as “DTI”; however, they do not go all the way down to the bottom of substrate 404; hence, they are shallow DTI; hence “shallow isolation structures”; please note that Applicant’s specification uses same language (shallow DTI)).
Regarding claim 20, Cheng discloses in FIG. 12 and related text, e.g., further comprising:
a portion of the metal layer, adjacent to the at least one pixel sensor, that is connected to the substrate for grounding (see 476 and par. 63).
Regarding claim 21, Cheng discloses in FIG. 12 and related text, e.g., a semiconductor device, comprising:
A substrate (404) including at least one photodiode (406);
an isolation structure (434) in the substrate and surrounding the at least one photodiode (it is a grid);
an optical blocking region (between 402a and 402b; it is covered in metal 472), comprising a recessed pattern in the substrate (see 476), adjacent to the isolation structure (434);
a dielectric layer (436 and/or 438) over the isolation structure and the recessed pattern; and a metal layer (472) over the dielectric layer.
Regarding claim 24, Cheng discloses in FIG. 12 and related text, e.g., wherein the recessed pattern comprises a plurality of shallow isolation structures in the substrate (see claim 18).
Regarding claim 26, Cheng discloses in FIG. 12 and related text, e.g., wherein the dielectric layer (436 and/or 438) conforms to the recessed pattern (it goes right up to it on both sides; hence “conforms to the recessed pattern”), and wherein the metal layer conforms to the recessed pattern in the optical blocking region (472 conforms to the pattern by following it).
Regarding claim 28, Cheng discloses in FIG. 12 and related text, e.g., wherein the metal layer comprises a grounding node (476), adjacent to the at least one photodiode, that is electrically connected to the substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over (US-2022/0165776) by Lin et al (“Lin”).
Regarding claim 2, Lin discloses in FIG. 3 and related text, e.g., substantially the entire claim structure, as recited in above claims, including wherein the nanoscale grid comprises a plurality of metal structures (the 336 structures shown in FIG. 3 are located next to specific 326; the pixels are notoriously-well known to be in an array form; hence, there are 336 structures next to other 326’s elsewhere in the array; hence, “plurality of metal structures”).
Lin does not explicitly state that “each metal structure has a width in a range from approximately 100 nanometers (nm) to approximately 200 nm”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Lin with “each metal structure has a width in a range from approximately 100 nanometers (nm) to approximately 200 nm”, as a matter of obvious choice in view of march of technology; as is known to any reasonably informed member of the public, semiconductor industry is constantly shrinking the sizes of its devices, from arbitrarily larger sizes to arbitrarily smaller ones, over a period of 12-18 months (colloquially known as “Moore’s Law”, and it is often enough publicly discussed in popular media; hence, “any reasonably informed member of the public”); therefore, as feature sizes shrink, from arbitrarily large numbers to arbitrarily small numbers, skilled artisan would be drawn to the cited feature sizes, simply as a matter of march of technology, with no further consideration needed.
A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claims 19, 25 & 27 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2021/0384247) by Cheng et al (“Cheng”).
Regarding claim 19, Cheng discloses in FIG. 12 and related text, e.g., substantially the entire claim structure, as recited in above claims, except “wherein each of the shallow isolation structures has a depth in a range from approximately 0.5 micrometers ( um) to approximately 6.0 um”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Cheng with “wherein each of the shallow isolation structures has a depth in a range from approximately 0.5 micrometers ( um) to approximately 6.0 um”, as a matter of obvious choice in view of march of technology; as is known to any reasonably informed member of the public, semiconductor industry is constantly shrinking the sizes of its devices, from arbitrarily larger sizes to arbitrarily smaller ones, over a period of 12-18 months (colloquially known as “Moore’s Law”, and it is often enough publicly discussed in popular media; hence, “any reasonably informed member of the public”); therefore, as feature sizes shrink, from arbitrarily large numbers to arbitrarily small numbers, skilled artisan would be drawn to the cited feature sizes, simply as a matter of march of technology, with no further consideration needed.
A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 25, Cheng discloses in FIG. 12 and related text, e.g., substantially the entire claim structure, as recited in above claims, except “wherein each of the plurality of shallow isolation structures has a width in a range from approximately 100 nanometers (nm) to approximately 400 nm”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Cheng with “wherein each of the plurality of shallow isolation structures has a width in a range from approximately 100 nanometers (nm) to approximately 400 nm”, as a matter of obvious choice in view of march of technology; as is known to any reasonably informed member of the public, semiconductor industry is constantly shrinking the sizes of its devices, from arbitrarily larger sizes to arbitrarily smaller ones, over a period of 12-18 months (colloquially known as “Moore’s Law”, and it is often enough publicly discussed in popular media; hence, “any reasonably informed member of the public”); therefore, as feature sizes shrink, from arbitrarily large numbers to arbitrarily small numbers, skilled artisan would be drawn to the cited feature sizes, simply as a matter of march of technology, with no further consideration needed.
A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 27, Cheng discloses in FIG. 12 and related text, e.g., wherein the metal layer comprises an electrical pad over an electrical pad region (note: this appears to be an attempt to claim the process steps of FIG. 5E, and par. 98 of Specification, where one metal layer is formed on “optical black” region and “electrical pad” region; however, it is shown to be separate structures in the end (318 and 336); hence, these limitations, if Examiner understands them correctly, are not patentable in a claim drawn to device).
Note that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Alternatively, in order to remove all arguments, it would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Cheng with “wherein the metal layer comprises an electrical pad over an electrical pad region”, in order to simplify the processing steps of making device, by reducing a number of manufacturing steps, by forming two separate structures in a single manufacturing step (it is a notoriously well-known way to simplify the processing steps [Wingdings font/0xE0] just do two separate structures simultaneously).
Claims 16-17 & 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2021/0384247) by Cheng et al (“Cheng”) in view of (US-2022/0165776) by Lin et al (“Ling”).
Regarding claim 16, Cheng discloses in FIG. 12 and related text, e.g., substantially the entire claim structure, as recited in claims, but does not disclose wherein the recessed pattern in the substrate includes a plurality of high absorption (HA) regions, that are approximately pyramidal.
Lin discloses in FIG. 3 and related text, e.g., wherein the recessed pattern in the substrate includes a plurality of high absorption (HA) regions (330), that are approximately pyramidal (see FIG. 3).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Cheng with “wherein the recessed pattern in the substrate includes a plurality of high absorption (HA) regions, that are approximately pyramidal” as taught by Lin, in order to “increase the absorption of incident light for a pixel sensor” (par. 46).
Regarding claim 17, the combined device of Cheng and Lin disclose in cited figures and related text, e.g., substantially the entire claim structure, as recited in claims, but does not explicitly state “wherein each of the HA regions is associated with an angle in a range from approximately 54 degrees to approximately 55 degrees“.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Cheng and Lin with “wherein each of the HA regions is associated with an angle in a range from approximately 54 degrees to approximately 55 degrees“, in order to achieve a particularly desired amount light reflection (a “result effective variable” [Wingdings font/0xE0] light reflection is the whole point; hence, finding a proper amount of light reflection is needed; hence, finding proper angle is also needed, since it affects the result, per high school physics) inside the pixel sensor (Lin makes clear the purpose of the HA regions in par. 46 and so on; then it becomes a matter of routine optimization to find the proper angle for a specific design; a POSITA who would search for that proper angle would arrive at stated values, simply through routine optimization).
It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Regarding claim 22, the combined device of Cheng and Lin disclose in cited figures and related text, e.g., wherein the recessed pattern comprises a plurality of high absorption (HA) regions formed in the substrate that are approximately pyramidal (see claim 16).
Regarding claim 23, the combined device of Cheng and Lin disclose in cited figures and related text, e.g., wherein each of the plurality of HA regions is associated with an angle in a range from approximately 54 degrees to approximately 55 degrees (see claim 17).
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
03/21/26
/Mounir S Amer/Primary Examiner, Art Unit 2818