DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 6, 9, 14, 17, and 18 have been amended.
Claims 1-20 have been examined.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 22, 2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 6,295,601 by Steele (hereinafter referred to as “Steele”) in view of US Publication No. 2011/0173394 by Gara et al. (hereinafter referred to as “Gara”).
Regarding claims 1, 9, and 17, taking claim 1 as representative, Steele discloses:
a computer-implemented method for synchronizing processing work in a computing system, the method comprising: executing, by a first processor, a first memory operation that specifies a first category, wherein the first memory operation stores data in a memory that is physically remote from the first processor (Steele discloses, at col. 10, lines 4- 38, using trap barriers to ensure correct operation, which discloses synchronizing processing work in a computing system. Steele also discloses, at Figure 4 and related description, executing an instruction that includes a trap barrier class identifier. As disclosed at col. 8, lines 38-52, the instruction can be a load/store instruction. Steele discloses, at Figure 1 and related description, a memory subsystem that is physically remote from the microprocessor. Steele also discloses, at claim 26, an embodiment using media storing instructions.);
executing a first barrier instruction that specifies the first category (Steele discloses, at Figure 5, a barrier instruction that includes a class identifier.);
determining that data associated with memory operations that specify the first category, including the first memory operation, is visible in the memory (Steele discloses, at Figure 6 and related description, determining whether instructions that are executing and that specify a particular class of barrier might trap, which discloses, in the case of memory operations, determining whether the data specified by the memory operation is visible in memory.); and
setting a … [signal] by the first processor, to enable a first process to execute on a …processor while a second memory operation …is pending (Steele discloses, at Figure 6 and related description, clearing, which discloses setting, the “might trap” signal to enable a first process to execute. This occurs while other operations are pending, i.e., those that don’t specify the particular class of barrier associated with the first process, which discloses a second memory operation. See also Figure 3 and related description, which discloses concurrent pipelined execution of multiple instructions.),
wherein the …[signal] indicates that data stored by all memory operations that specify the first category, including the first memory operation, is visible in the memory (Steele discloses, at Figure 6 and related description, setting the signal indicates that none of the instructions associated with the class will trap, which discloses, in the case of memory operations, that all data is visible in memory.), and
the first process accesses the data associated with the first memory operation (Steele discloses, at Figure 3, executing instructions. In the case of a memory instruction, once the instruction is complete, other instructions can use data associated with the memory instruction, which discloses the first process accessing the data.).
Steele does not explicitly disclose the aforementioned setting is of a flag, that the aforementioned enabling is for a second processor, and the aforementioned second memory operation is included in a second process executing on the second processor.
However, in the same field of endeavor (e.g., instruction control) Gara discloses:
one processor setting a flag to enable execution by a second processor (Gara discloses, at ¶ [0050] et seq., one core, i.e., processor, sets a flag to indicate to another core that data is valid, i.e., available for use by the other core.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Steele to include using a flag, as disclosed by Gara, because doing so is an efficient way to convey status information, e.g., instruction completion or data availability.
Regarding claims 2 and 10, taking claim 2 as representative, Steele, as modified, discloses the elements of claim 1, as discussed above. Steele also discloses:
wherein the second memory operation specifies a second category that is different from the first category (Steele discloses, at Figure 7 and related description, multiple trap barrier counts, which discloses multiple different categories.).
Regarding claims 3 and 11, taking claim 3 as representative, Steele, as modified, discloses the elements of claim 1, as discussed above. Steele also discloses:
wherein the second memory operation does not specify a category (Steele discloses, at col. 13, lines 43-53, instructions that do not include a class field.).
Regarding claims 4 and 12, taking claim 4 as representative, Steele, as modified, discloses the elements of claim 1, as discussed above. Steele also discloses:
wherein the second memory operation does not specify a category, and wherein the second memory operation is deemed to specify a default category that is different from the first category (Steele discloses, at col. 13, lines 43-53, instructions that do not include a class field but are nevertheless assigned classes, which disclose being assigned default classes.).
Regarding claims 5 and 13, taking claim 5 as representative, Steele, as modified, discloses the elements of claim 1, as discussed above. Steele also discloses:
wherein the second memory operation specifies a default category that is different from the first category (Steele discloses, at Figure 7 and related description, multiple trap barrier counts, which discloses a different default category.).
Regarding claims 6, 14, and 18, taking claim 6 as representative, Steele, as modified, discloses the elements of claim 1, as discussed above. Steele also discloses:
executing the second memory operation that specifies the second category; executing a second barrier instruction that specifies the second category (Steele discloses, at Figure 7 and related description, executing instructions that specify different classes. As disclosed at col. 8, lines 38-52, the instructions can be load/store instructions.);
determining that data associated with memory operations that specify the second category, including the second memory operation, is visible in the memory (Steele discloses, at Figure 3, executing instructions. In the case of a memory instruction, this includes determining that data associated with the instruction is visible in memory.); and
subsequent to determining that the data associated with the second memory operation is visible in the memory, … enable a third process to execute on the …processor, wherein the third process accesses the data associated with the second memory operation (Steele discloses, at Figure 3, executing instructions. In the case of a memory instruction, once the instruction is complete, other instructions can use data associated with the memory instruction, which discloses enabling a third process to execute on a processor to access the data. As disclosed at col. 8, lines 38-52, the instructions can be load/store instructions.).
Steele does not explicitly disclose setting a flag by a first processor and that the aforementioned enabling is for a second processor.
However, in the same field of endeavor (e.g., instruction control) Gara discloses:
one processor setting a flag to enable execution by a second processor (Gara discloses, at ¶ [0050] et seq., one core, i.e., processor, sets a flag to indicate to another core that data is valid, i.e., available for use by the other core.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Steele to include using a flag, as disclosed by Gara, because doing so is an efficient way to convey status information, e.g., instruction completion or data availability.
Regarding claims 7, 15, and 19, taking claim 7 as representative, Steele, as modified, discloses the elements of claim 1, as discussed above. Steele also discloses:
executing the second memory operation that does not specify a category (Steele discloses, at col. 13, lines 43-53, instructions that do not include a class field.);
assigning a default category to the second memory operation (Steele discloses, at col. 13, lines 43-53, instructions that do not include a class field but are nevertheless assigned classes, which disclose being assigned default classes.);
executing a second barrier instruction that specifies the default category (Steele discloses, at Figure 5, barrier instructions that include class identifiers.);
determining that data associated with memory operations that specify the default category, including the second memory operation, is visible in the memory (Steele discloses, at Figure 3, executing instructions. In the case of a memory instruction, this includes determining that data associated with the instruction is visible in memory.); and
subsequent to determining that the data associated with the second memory operation is visible in the memory, … enable a second process to execute on the processor, wherein the first process accesses the data associated with the second memory operation (Steele discloses, at Figure 3, executing instructions. In the case of a memory instruction, once the instruction is complete, other instructions can use data associated with the memory instruction, which discloses enabling a second process to execute on a processor to access the data. As disclosed at col. 8, lines 38-52, the instructions can be load/store instructions.).
Steele does not explicitly disclose setting a flag by a first processor and that the aforementioned enabling is for a second processor.
However, in the same field of endeavor (e.g., instruction control) Gara discloses:
one processor setting a flag to enable execution by a second processor (Gara discloses, at ¶ [0050] et seq., one core, i.e., processor, sets a flag to indicate to another core that data is valid, i.e., available for use by the other core.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Steele to include using a flag, as disclosed by Gara, because doing so is an efficient way to convey status information, e.g., instruction completion or data availability.
Regarding claims 8, 16, and 20, taking claim 8 as representative, Steele, as modified, discloses the elements of claim 1, as discussed above. Steele also discloses:
executing the second memory operation that does not specify a category (Steele discloses, at col. 13, lines 43-53, instructions that do not include a class field.);
executing a second barrier instruction that does not specify a category (Steele discloses, at col. 15, lines 43-48, a barrier instruction that does not include a class field.);
determining that data associated with all pending memory operations, including the second memory operation, is visible in the memory (Steele discloses, at Figure 3, executing instructions. In the case of a memory instruction, this includes determining that data associated with the instruction is visible in memory.); and
subsequent to determining that the data associated with the second memory operation is visible in the memory, … to enable a second process to execute on the processor, wherein the first process accesses the data associated with the second memory operation (Steele discloses, at Figure 3, executing instructions. In the case of a memory instruction, once the instruction is complete, other instructions can use data associated with the memory instruction, which discloses enabling a second process to execute on a processor to access the data. As disclosed at col. 8, lines 38-52, the instructions can be load/store instructions.).
Steele does not explicitly disclose setting a flag by a first processor and that the aforementioned enabling is for a second processor.
However, in the same field of endeavor (e.g., instruction control) Gara discloses:
one processor setting a flag to enable execution by a second processor (Gara discloses, at ¶ [0050] et seq., one core, i.e., processor, sets a flag to indicate to another core that data is valid, i.e., available for use by the other core.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Steele to include using a flag, as disclosed by Gara, because doing so is an efficient way to convey status information, e.g., instruction completion or data availability.
Response to Arguments
On page 11 of the response filed December 22, 2025 (“response”), the Applicant argues, “Amended independent claim 1 recites the limitations of executing, by a first processor, a first memory operation that specifies a first category, wherein the first memory operation stores data in a memory that is physically remote from the first processor. Neither of the references cited by the Examiner teaches or suggests these limitations. Therefore, neither any single reference nor the logical combination of the cited references teaches or suggests each and every limitation of amended claim 1. Gara discloses techniques for processing store instructions in a parallel computing system. See Gara at Abstract. In Gara, a processor core sets a flag bit on data in a shared cache memory device updated by a store instruction. See id. at TT [0044], [0050]. The flag bit indicates whether corresponding data is valid or not. See id. A messaging unit (MU) looks at the flag bit based on a memory location or address specified in the store instruction, validates the updated data, and sends the updated data to other processor cores or other computing nodes that the MU does not belong to. See id. In the rejections, the Examiner relies on Gara to teach the limitations of setting a flag, recited in prior claim 1. See Final Office Action at 4. Further, the Examiner relies on Gara to teach the limitations that the setting of the flag enables a process to execute on a second processor. See id. Importantly, the Examiner's arguments no longer apply to amended claim 1. In particular, Steele Gara not disclose any techniques for executing, by a first processor, a first memory operation that specifies a first category, where the first memory operation stores data in a memory that is physically remote from the first processor, recited in amended claim 1. Instead, Gara discloses store instructions that update data in a shared cache memory device. Consequently, Gara cannot be properly interpreted as teaching or suggesting the above limitations of amended claim 1. A careful review of the remaining reference cited by the Examiner shows that this reference also does not teach or suggest the above limitations of amended claim 1.”
Though fully considered, the Examiner respectfully disagrees. Steele discloses, e.g., at Figure 1 and related description, a memory subsystem that is physically remote from the microprocessor. This discloses the added limitations of storing data in a memory that is physically remote from the first processor. Accordingly, the Applicant’s arguments are deemed unpersuasive. As Gara is not cited for these teachings, the Applicant’s arguments relating to Gara are moot.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/Primary Examiner, Art Unit 2183
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