DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed on 02/17/2026, with respect to Chen (US 2021/0082874) have been fully considered and are persuasive. The previous of rejection has been withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/17/2026 had been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 8-9 and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 2021/0375819).
Regarding claim 1, Chen teaches a method see figs. 2, 4 and 5, comprising:
bonding a first wafer (20) with a second wafer (22) through wafer-on-wafer bonding (see par. 21 and figs. 2A/2B), wherein the second wafer (22) comprises a first plurality of device dies (46) therein;
bonding a second plurality of device dies (46) on the second wafer (22) through chip-on-wafer bonding (refer to 54) (see fig. 4A/4B; par. 24); and
performing a gap-filling process to fill gaps between the second plurality of device dies with gap-filling regions (56), wherein the gap-filling regions and the second plurality of device dies collectively form a reconstructed wafer (100) (see fig. 5).
Regarding claim 2, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Chen teaches the first wafer comprises a carrier, and the method further comprises:
bonding a supporting substrate (60) on the second plurality of device dies (46) through wafer-on-wafer bonding, wherein the supporting substrate (60) and the first wafer (20) are on opposing sides of the second wafer (see fig. 6); and removing the first wafer (see fig. 7).
Regarding claim 4, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 8 of Chen teaches after the first wafer (20) is removed, etching a dielectric layer (41) in the second wafer to form an opening (see fig. 8, par. 33), with a metal pad (40) in the second wafer being exposed; and forming an electrical connector (66) on the metal pad (40) (see fig. 8).
Regarding claim 8, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Figs. 2-3 of Chen teaches the second wafer (22) comprises a semiconductor substrate (24), and through-vias (26) extending into the semiconductor substrate (24) (see fig. 2), and wherein the method further comprises: before the second plurality of device dies are bonded on the second wafer, thinning the semiconductor substrate to reveal the through-vias (see fig. 3).
Regarding claim 9, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Chen teaches sawing the reconstructed wafer to form a plurality of packages. (see fig. 8; par. 35).
Regarding claim 12, Chen teaches method comprising:
bonding a device wafer (22) to a carrier (20) through fusion bonding (see par. 21, figs. 2A/2B), wherein the device wafer (22) comprises integrated circuits (23) therein (see par. 16 and figs. 1A/1B);
bonding a plurality of device dies (46) on the device wafer (22) through chip-on-wafer (54) bonding (see fig. 4A);
performing a gap-filling process to fill gaps between the plurality of device dies with gap-filling regions (see fig. 5);
bonding a supporting substrate (60) to the gap-filling regions and the plurality of device dies (46);
removing the carrier (20) from the device wafer (22) (see fig. 7); and
forming electrical connectors (66) on the device wafer (22), wherein the electrical connectors (66) are electrically connected to the integrated circuits (22) in the device wafer (22) (see fig. 8).
Regarding claim 13, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Chen teaches the supporting substrate (60) comprises a blank silicon substrate (see par. 31).
Regarding claim 14, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Chen teaches after the gap-filling process and before the supporting substrate is bonded to the gap-filling regions: depositing a bond layer (58) on the gap-filling regions and the plurality of device dies (46) (see fig. 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2021/0375819) as applied to claim 1 above, and further in view of Lee (US 10068877).
Regarding claim 3, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above except for the removing the first wafer comprises a grinding process.
Lee teaches a same field of an endeavor wherein the removing the first wafer (236) comprises a grinding process (see fig. 5f) (see col. 13, lines 13-16).
Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include a step of removing the first wafer comprises a grinding process as taught by Lee in the teaching of Chen so that it provides an alternative way of removing the first wafer.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “ after the gap-filling process, performing a bevel-filling process to fill bevel recesses that are close to edge regions of the reconstructed wafer.” Claims 6-7 include all the limitations of the claim 5.
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “trimming edge portions of the reconstructed wafer to remove portions of the reconstructed wafer, with the trimmed portions being free from circuits.”
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “before the second plurality of device dies are bonded on the second wafer, performing an edge trimming process to remove an edge portion of the second wafer.”
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “before the supporting substrate is bonded, etching a portion of the gap-filling regions, wherein the etched portion being deposited on an edge of the carrier.”
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest “before the plurality of device dies are bonded to the carrier, performing an edge trimming process to remove edge portions of the device wafer.” Claim 17 includes all the limitations of the claim 16.
Claims 18-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 18, the prior art of record alone or in combination neither teaches nor makes obvious the invention of a structure comprising: “a bevel-recess filling region on a side of, and contacting, the gap-filling region; a bond layer contacting the bevel-recess filling region, the gap-filling region, and the semiconductor substrate; and a supporting substrate bonding to the second device die through the bond layer, wherein an entirety of the supporting substrate is formed of a homogeneous material” in combination of all of the limitations of claim 18. Claims 19-20 include all of the limitations of claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Niki Tram Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-4:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIKI H NGUYEN/ Primary Examiner, Art Unit 2818
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