DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 12/12/2025, responding to the Office action mailed on 9/15/2025, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 8759885 B1) in view of Chern (US 20100223585 A1).
Re Claim 1 Jain teaches a semiconductor device, comprising:
a first region (502, FIG. 5) and a second region (FIG. 5 repeated and placed next to the first region, page 2, par 4 states, “During semiconductor device design, the design tool selects one or more standard cells from the cell library based on the logic design and the process parameters (i.e., size and width of the standard cell) and places the cells in rows and columns.”) disposed adjacent to each other and having a boundary therebetween (FIG. 5 shows a cell boundary; the cells can be vertically stacked),
wherein the first region comprises:
a first active region (504c, page 8 last par), a second active region (504a) and a third active region (504e) extending in a first direction (horizontal), wherein a width of the first active region (504c) measured along a second direction (vertical) is different from a width of the third active region (504e) measured along the second direction, and the second direction is different from the first direction (FIG. 5, 1st direction is horizontal, and 2nd direction is vertical on image); and
a first gate electrode (506c, page 8 last par), a second gate electrode (506a) and a third gate electrode (506e) extending in the second direction and disposed across the first active region (504c), the second active region (504a) and the third active region (504e) respectively,
wherein from a top view, the first active region (504c) has a first edge (lower edge) and a second edge (upper edge) opposite to each other, the first edge of the first active region (lower edge of 504) is aligned with an edge (lower edge) of the second active region (504a), and the second edge of the first active region (top of 504c) is aligned with an edge (top edge) of the third active region (504e).
Jain does not teach a width of the first active region measured along a second direction is different from a width of the second active region measured along the second direction, and the second direction is different from the first direction.
Chern teaches a width of the first active region (214) [0011] measured along a second direction (vertical in FIG. 6 which is a top view [0021]) is different from a width of the second active region (210) measured along the second direction (vertical), and the second direction is different from the first direction (first direction is horizontal, FIG. 6).
The ordinary artisan would have been motivated to modify Chern in combination with Jain in the above manner for the motivation of forming the active regions of optimal width to help control the stress in device channels which controls the drive currents which will enable the device to function with reduced performance drift allowing the device to function at an optimal level. [0003] states, “The disclosure relates generally to integrated circuits, and more particularly to metal-oxide-semiconductor (MOS) devices, and even more particularly to a dummy pattern design for reducing the performance drift of the MOS devices caused by differences in stresses applied on the MOS devices.” A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chern into the structure of Jain.
Re Claim 2 Jain in view of Chern teaches the semiconductor device of claim 1, wherein the second region (Jain, reuse 502, FIG. 5, page 2, par 4 states, “During semiconductor device design, the design tool
selects one or more standard cells from the cell library based on the logic design and the process parameters (i.e., size and width of the standard cell) and places the cells in rows and columns.”) comprises:
a fourth active region (504c, FIG. 5), a fifth active region (504a) and a sixth active region (504e) extending in the first direction (horizontally) and having different widths (504c and 504e have different vertical widths); and
a fourth gate electrode (506b), a fifth gate electrode (506a) and a sixth gate electrode (506d) extending in the second direction (vertically) and disposed across the fourth active region (504c), the fifth active region (504a) and the sixth active region (504e) respectively (FIG. 5, parts from 1st region can be reused as the cell pattern can be stacked, page 2, par 4).
Re Claim 3 Jain in view of Chern teaches the semiconductor device of claim 2, wherein the fourth active region (Jain, 504c) has a third edge (bottom edge of 504c) and a fourth edge (top of 504c) opposite to each other, the third edge (bottom) of the fourth active region (504c) is aligned with an edge (bottom) of the fifth active region (504a), and the fourth edge (top) of the fourth active region (504c) is aligned with an edge (top) of the sixth active region (504e, FIG. 5).
Re Claim 5 Jain in view of Chern teaches the semiconductor device of claim 3, but does not explicitly teach from the top view, the first active region, the second active region and the third active region are arranged asymmetrically to the fourth active region, the fifth active region and the sixth active region with respect to the boundary between the first region and the second region.
Jain shows the top view (FIG. 5), the first active region (504c), the second active region (504a) and the third active region (504e) are arranged asymmetrically to the fourth active region (504c), the fifth active region (504a) and the sixth active region (504e) with respect to the boundary between the first region and the second region (cells can be vertically stacked, so the parts can stacked, and the regions will by asymmetrical when stacking 502 vertically. page 2, par 4 ).
The ordinary artisan would have been motivated to modify Jain in combination with Jain in view of Chern in the above manner for the motivation of designing the semiconductor device with asymmetrical regions so regions can be easily stacked and repeated. It has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jain into the structure of Jain in view of Chern.
Re Claim 6 Jain in view of Chern teaches the semiconductor device of claim 1, wherein the first gate electrode (Jain, 506b), the second gate electrode (506a) and the third gate electrode (506d) have the same width (FIG. 5).
Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 8759885 B1) in view of Chern (US 20100223585 A1) as applied to claims 1-3 above, and further in view of Jung (US 20220310586 A1).
Re Claim 4 Jain in view of Chern teaches the semiconductor device of claim 3, but does not teach wherein from the top view, the first active region, the second active region and the third active region are arranged symmetrically to the fourth active region, the fifth active region and the sixth active region with respect to the boundary between the first region and the second region.
Jung teaches from the top view (FIG. 1), the first active region (SC2) [0023], the second active region (SC1) and the third active region (SC3) are arranged symmetrically to the fourth active region (SC5), the fifth active region (SC4 and the sixth active region (SC6) with respect to the boundary between the first region and the second region (use horizontal cell boundary between R1 and R2 ).
The ordinary artisan would have been motivated to modify Jung in combination with Jain in view of Chern in the above manner for the motivation of designing the semiconductor device with symmetrical region sets to help the device function optimally. [0004] states, “In particular, as the demand for reliability of the miniaturized semiconductors devices increases, there is a need for a layout design capable for improving electrical characteristics of semiconductor devices and securing the reliability of the miniaturized semiconductor devices.” It has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jung into the structure of Jain in view of Chern.
Re Claim 7 Jain in view of Chern teaches the semiconductor device of claim 1, but does not teach dielectric walls extending in the second direction, and configured to separate the first active region, the second active region and the third active region from each other.
Jung teaches dielectric walls (DB, FIG. 6, [0120] states, “The plurality of diffusion breaks DB may be filled with an insulator.”) extending in the second direction (vertically), and configured to separate the first active region (RX2, SC102) [0031], the second active region (RX4, FC101) [0032] and the third active region (RX2, SC104) from each other.
The ordinary artisan would have been motivated to modify Jung in combination with Jain in view of Chern in the above manner for the motivation of adding a dielectric/insulator layer around the active body regions to ensure region integrity and that the current signals are shorted between bodies and ensure the semiconductor device functions optimally. As semiconductor devices continue to get smaller, it is getting harder to not have components shorted. [0003] states, “It is known that reducing the size of a semiconductor device can improve the price competitiveness of the semiconductor device. However, the reduction in size of the semiconductor device may cause a short channel effect.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jung into the structure of Jain in view of Chern.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 8759885 B1) in view of Chern (US 20100223585 A1) and Jung (US 20220310586 A1) as applied to claims 1 and 7 above, and further in Azuma (US 20030222319 A1) and Chang (US 20120306000 A1).
Re Claim 8 Jain in view of Chern and Jung teaches the semiconductor device of claim 7, but does not teach spacers extending in the second direction on sidewalls of each of the first gate electrode, the second gate electrode, the third gate electrode and the dielectric walls.
Azuma teaches spacers (26), Fig. 8a) [0038] extending in the second direction (would be vertical direction from top view) on sidewalls of each of the first gate electrode (24) [0036], the second gate electrode (repeat for 2nd and 3rd gate electrodes), and the third gate electrode.
The ordinary artisan would have been motivated to modify Azuma in combination with Jain in view of Chern and Jung in the above manner for the motivation of add dielectric layers around the gate electrodes in an optimal manner to allow the device to be as small as possible as and still function at a peak level as the industry demands scaling down device seizes. [0002] states, “With the increasing miniaturization of semiconductor elements in recent years, a demand has risen for technologies to achieve the following: reduction of the gate length of the transistor, reduction of the thickness of the gate oxide film, reduction of the film thickness of the electrode side wall spacer, and shallowing of junctions.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Azuma into the structure of Jain in view of Chern and Jung.
Jain in view of Chern and Jung and Azuma does not teach the spacers on the dielectric walls.
Chang teaches the spacers (702, FIG. 7A &B) [0029] dielectric walls (502 layer that extends undivided in vertical direction, FIG. 7A).
The ordinary artisan would have been motivated to modify Chang in combination with Jain in view of Chern and Jung and Azuma in the above manner for the motivation of optimally joining the spacer layer to the dielectric sidewalls to ensure semiconductor device integrity. [0002] states, “During the course of the device fabrication, the space between line ends tends to undesirably grow larger due to processes such as dry or wet etches that erode short edges faster than long edges. This eventual growth in end-to-end spacing is anticipated in the initial design and layout of the gate pattern. Spaces in between gates are filled by dielectric during the course of fabrication, either spacer material, liner material or middle-of-the-line dielectric material.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chang into the structure of Jain in view of Chern and Jung and Azuma.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 8759885 B1) in view of Chern (US 20100223585 A1) as applied to claim 1 above, and further in view of Thong (CN 114649344 A).
Re Claim 9 Jain in view of Chern teaches the semiconductor device of claim 1, but does not teach a first metal contact, a second metal contact and a third metal contact extending in the second direction and adjacent to the first gate electrode, the second gate electrode and the third gate electrode respectively; and
a first metal line, a second metal line and a third metal line extending in the first direction, and disposed across the first gate electrode, the second gate electrode and the third gate electrode respectively.
Thong teaches a first metal contact (443 in SB0, BLK0, page 18, par 4), a second metal contact (443 in SB1, BLK0) and a third metal contact (443, SB0, BLK1) extending in the second direction (would extend in vertical direction from top view) and adjacent to the first gate electrode (260 below 443 in SB0, BLK0), the second gate electrode (260 below 443 in SB1, BLK0) and the third gate electrode (260 below 443, SB0, BLK1) respectively (page 14, par 2, Figure 4A) (from top view); and
a first metal line (444 in SB0, BLK0), a second metal line (444 in SB1, BLK0) and a third metal line (444, SB0, BLK1) extending in the first direction (horizontal), and disposed across the first gate electrode, the second gate electrode and the third gate electrode respectively (Figure 4A, 444 and 260 will have overlap from top view).
The ordinary artisan would have been motivated to modify Thong in combination with Jain in view of Chern in the above manner for the motivation of adding metal contacts and lines around the gates to optimize the electrical signals to help the semiconductor device reach peak performance. Page 2 par 3 states, “The memory device typically has a plurality of memory cells for storing a information (e.g., data) and a data line that carries the information (in the form of an electrical signal) back and forth to the memory cell.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Thong into the structure of Jain in view of Chern.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 8759885 B1) in view of Chern (US 20100223585 A1) as applied to claim 1 above, and further in view of Paul (US 20200035686 A1).
Re Claim 10 Jain in view of Chern teaches the semiconductor device of claim 1, but does not teach first nanosheets are vertically stacked in the first active region, second nanosheets are vertically stacked in the second active region and third nanosheets are vertically stacked in the third active region, and the first nanosheets are wider than the second nanosheets or the third nanosheets.
Paul teaches teach first nanosheets (620) are vertically stacked in the first active region (center region in 125, Figure 6B), second nanosheets are vertically stacked in the second active region (620 in left region of 125, Figure 6B) and third nanosheets are vertically stacked in the third active region (620 in right region of125, Figure 6B), and the first nanosheets are wider than the second nanosheets or the third nanosheets.
The ordinary artisan would have been motivated to modify Paul in combination with Jain in view of Chern in the above manner for the motivation of adding the nanosheet layers in the active regions and making the 1st active regions nano sheets wider to allow for optimal channel size while still forming a device that is not over-sized and requires as little change as possible to the manufacturing process of the device. [0003] states, “The various devices consume area in the circuit layout, resulting in a minimum cell area. Generally, reducing the cell area requires an advancement in the process used that allows smaller devices to be fabricated. It would be useful to reduce cell area without requiring a fundamental change in the fabrication processes.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Paul into the structure of Jain in view of Chern.
Claims 11-14 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 8759885 B1) in view of Thong (CN 114649344 A) and Chern (US 20100223585 A1).
Re Claim 11 Jain teaches a semiconductor device, comprising:
a first region (502, FIG. 5) and a second region (502 repeated and placed next to the first region, page 2, par 4 states, “During semiconductor device design, the design tool selects one or more standard cells from the cell library based on the logic design and the process parameters (i.e., size and width of the standard cell) and places the cells in rows and columns.”) disposed adjacent to each other and having a boundary (FIG. 5 shows a cel boundary around entire first and second regions) therebetween, wherein the first region comprises:
a first active region (504c, page 8 last par), a second active region (504a) and a third active region (504e) extending in a first direction;
a first gate electrode (506c, page 8 last par), a second gate electrode(506a) and a third gate (506e) electrode extending in a second direction and disposed across the first active region (504c), the second active region (504a) and the third active region (504e) respectively; and
wherein the first active region (504c), the second active region (504a) and the third active region (504e) have a first width, a second width and a third width measured along the second direction respectively(vertical from top view), and
the first width is greater than the third width (504c has a greater width in the vertical direction from a top view compared to 504e).
Jain does not teach a first metal contact, a second metal contact and a third metal contact extending in the second direction and across the first active region, the second active region and the third active region respectively,
wherein the first metal contact, the second metal contact and the third metal contact have a first length, a second length and a third length measured along the second direction respectively, and
the first length is greater than the third length, and the third length is greater than the second length.
Thong teaches a first metal contact (443), a second metal contact (441) and a third metal contact (442) extending in the second direction and across the first active region, the second active region and the third active region respectively,
wherein the first metal contact (443), the second metal contact (441) and the third metal contact (442) have a first length, a second length and a third length measured along the second direction respectively (Figure 4A), and
the first length is greater than the third length, and the third length is greater than the second length (Figure 4A, 442 will be wider in vertical direction than 441 from top view, and 443 wider than 442).
The ordinary artisan would have been motivated to modify Thong in combination with Jain in the above manner for the motivation of adding the metal lines to the semiconductor device to function ideally, and having the metal contacts be different lengths will help one in the art to easily optimize the electrical signals in the semiconductor device since the metal lines carry the data to and from the cells. Page 2 par 3 states, “The memory device typically has a plurality of memory cells for storing a information (e.g., data) and a data line that carries the information (in the form of an electrical signal) back and forth to the memory cell.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Thong into the structure of Jain.
Jain in view of Thong does not teach the first width is greater than the second width.
Chern teaches the first width (vertical width of 214 [0011] in FIG. 6) is greater than the second width (vertical width of 210).
The ordinary artisan would have been motivated to modify Chern in combination with Jain in view of Thong in the above manner for the motivation of forming the active regions of optimal width to help control the stress in device channels which controls the drive currents which will enable the device to function at a peak level and reduce performance drift in the device. [0003] states, “The disclosure relates generally to integrated circuits, and more particularly to metal-oxide-semiconductor (MOS) devices, and even more particularly to a dummy pattern design for reducing the performance drift of the MOS devices caused by differences in stresses applied on the MOS devices.” A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chern into the structure of Jain in view of Thong.
Re Claim 12 Jain in view of Thong and Chern teaches the semiconductor device of claim 11, wherein from a top view, the first active region (Jain, 504c) has a first edge (lower edge) and a second edge (top edge) opposite to each other, the first edge of the first active region (lower edge of 504c) is aligned with an edge of the second active region (lower edge of 504a), and the second edge of the first active region (top edge of 504c) is aligned with an edge of the third active region (top edge of 504e).
Re Claim 13 Jain in view of Thong and Chern teaches the semiconductor device of claim 11, wherein the second region comprises:
a fourth active region (Jain, 504c, FIG. 5), a fifth active region (504a) and a sixth active region (504e) having different widths and extending in the first direction (lower half of 504e has a different width in horizontal direction vs 504c in horizontal direction); and
a fourth gate electrode(506b), a fifth gate electrode (506a) and a sixth gate electrode (506d) extending in the second direction (vertical) and disposed across the fourth active region, the fifth active region and the sixth active region respectively (FIG. 5, 502 can be used for 1st and 2nd regions and reused/repeated; page 2, par 4 states, “During semiconductor device design, the design tool selects one or more standard cells from the cell library based on the logic design and the process parameters (i.e., size and width of the standard cell) and places the cells in rows and columns.”).
Re Claim 14 Jain in view of Thong and Chern teaches the semiconductor device of claim 13, wherein from a top view, the fourth active region (Jain, 504c) has a third edge (bottom) and a fourth edge (top of 504c) opposite to each other, the third edge (bottom) of the fourth active region (504c) is aligned with an edge (lower) of the fifth active region (504a), and the fourth edge (top) of the fourth active region (504c) is aligned with an edge (top) of the sixth active region (504e, FIG. 5).
Re Claim 18 Jain teaches a semiconductor device, comprising:
a first region (502. FIG. 5) and a second region (reuse 502, page 2, par 4 states, “During semiconductor device design, the design tool selects one or more standard cells from the cell library based on the logic design and the process parameters (i.e., size and width of the standard cell) and places the cells in rows and columns.”) disposed adjacent to each other and having a boundary (FIG. 5 shows a cell boundary) therebetween, wherein the first region comprises:
at least three active regions (504c, 504a, 504e) extending in a first direction (horizontally) and having different channel widths (504c is wider in the vertical direction compared to 504e), wherein the active regions comprise a first active region (504c), a second active region (504a) and a third active region (504e), the first active region (504c) is located between the second active region (504a) and the third active region (504e) in the first direction (horizontal, FIG. 5), a channel width of the first active region (504c) is different from a channel width (measured in vertical distance in FIG. 5) of the third active region (504e);
at least three gate electrodes (506b, 506a, 506d) extending in a second direction and disposed across the active regions respectively (FIG. 5);
Jain does not teach at least three metal contacts extending in the second direction and across the active regions respectively; and
at least three metal lines extending in the first direction and across the gate electrodes respectively,
wherein a contact length of one of the metal contacts farther away from the boundary between the first and second regions is shorter than a contact length of another of the metal contacts closer to the boundary between the first and second regions.
Thong teaches at least three metal contacts (443, 441, 442) extending in the second direction (vertical from top view) and across the active regions (260, page 14, last par, Fig. 4A) respectively; and
at least three metal lines (444 in SB0, BLK0, 444 in SB1, BLK0, and 444, SB0, BLK1) extending in the first direction (horizontal) and across the gate electrodes respectively (Figure 4A, 444 and 260 will have overlap from top view),
wherein a contact length of one of the metal contacts (441) farther away from the boundary between the first and second regions is shorter than a contact length of another of the metal contacts (443) closer to the boundary between the first and second regions (Fig. 4A, use 451 as boundary, 443 is closer to 451 in horizontal direction, and 441 is a shorter length).
The ordinary artisan would have been motivated to modify Thong in combination with Jain in the above manner for the motivation of adding the metal lines to the semiconductor device to function ideally, and having the metal contacts be different lengths will help one in the art to easily optimize the current in the semiconductor device since it is the metal contacts that traffic the electrical signal through the semiconductor device. Page 2 par 3 states, “The memory device typically has a plurality of memory cells for storing a information (e.g., data) and a data line that carries the information (in the form of an electrical signal) back and forth to the memory cell.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Thong into the structure of Jain.
Jain in view of Thong does not teach a channel width of the first active region is different from a channel width of the second active region.
Chern teaches a channel width of the first active region (214) [0011] is different from a channel width (FIG. 6 is top down view [0021], horizontal AND vertical directions) of the second active region (210).
The ordinary artisan would have been motivated to modify Chern in combination with Jain in view of Thong in the above manner for the motivation of forming the active regions of optimal width to help control the stress in device channels which controls the drive currents which will enable the device to function at a peak level and reduce the performance drift of the device. [0003] states, “The disclosure relates generally to integrated circuits, and more particularly to metal-oxide-semiconductor (MOS) devices, and even more particularly to a dummy pattern design for reducing the performance drift of the MOS devices caused by differences in stresses applied on the MOS devices.” A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chern into the structure of Jain in view of Thong.
Re Claim 19 Jain in view of Thong and Chern teaches the semiconductor device of claim 18, wherein from a top view (Jain, FIG. 5), the first active region (504c) has a first edge (bottom) and a second edge (top) opposite to each other, the first edge (bottom) of the first active region (504c) is aligned with an edge (bottom) of the second active region (504a), and the second edge (top) of the first active region (504c) is aligned with an edge (top) of the third active region (504e).
Claims 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 8759885 B1) in view of Thong (CN 114649344 A) and Chern (US 20100223585 A1) as applied to claims 11 and 18 above, and further in view of Paul (US 20200035686 A1).
Re Claim 15 Jain in view of Thong and Chern teaches the semiconductor device of claim 11, but does not teach the first nanosheets are vertically stacked in the first active region, second nanosheets are vertically stacked in the second active region and third nanosheets are vertically stacked in the third active region, and the first nanosheets are wider than the second nanosheets and the third nanosheets.
Paul teaches teach the first nanosheets (620) are vertically stacked in the first active region (center region in 125, Figure6B), second nanosheets are vertically stacked in the second active region (620 in left region of 125, Figure 6B) and third nanosheets are vertically stacked in the third active region (620 in right region of125, Figure 6B), and the first nanosheets are wider than the second nanosheets or the third nanosheets.
The ordinary artisan would have been motivated to modify Paul in combination with Jain in view of Thong and Chern in the above manner for the motivation of adding the nanosheet layers in the active regions and making the 1st active regions nano sheets wider to allow for current optimization between the semiconductor device channels while still forming a device that is not over-sized and requires as little change as possible to the manufacturing process of the device. [0003] states, “The various devices consume area in the circuit layout, resulting in a minimum cell area. Generally, reducing the cell area requires an advancement in the process used that allows smaller devices to be fabricated. It would be useful to reduce cell area without requiring a fundamental change in the fabrication processes.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Paul into the structure of Jain in view of Thong and Chern.
Re Claim 20 Jain in view of Thong and Chern teaches the semiconductor device of claim 18 but does not teach the first nanosheets are vertically stacked in the first active region, second nanosheets are vertically stacked in the second active region and third nanosheets are vertically stacked in the third active region, and the first nanosheets are wider than the second nanosheets or the third nanosheets.
Paul teaches teach the first nanosheets (620) are vertically stacked in the first active region (center region in 125, Figure 6B), second nanosheets are vertically stacked in the second active region (620 in left region of 125, Figure 6B) and third nanosheets are vertically stacked in the third active region (620 in right region of125, Figure 6B), and the first nanosheets are wider than the second nanosheets or the third nanosheets.
The ordinary artisan would have been motivated to modify Paul in combination with Jain in view of Thong and Chern in the above manner for the motivation of adding the nanosheet layers in the active regions and making the 1st active regions nano sheets wider to allow for current optimization between the semiconductor device channels while still forming a device that is not over-sized and requires as little change as possible to the manufacturing process of the device. [0003] states, “The various devices consume area in the circuit layout, resulting in a minimum cell area. Generally, reducing the cell area requires an advancement in the process used that allows smaller devices to be fabricated. It would be useful to reduce cell area without requiring a fundamental change in the fabrication processes.”.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Paul into the structure of Jain in view of Thong and Chern.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 8759885 B1) in view of Thong (CN 114649344 A) and Chern (US 20100223585 A1) as applied to claim 11 above, and further in view of Jung (US 20220310586 A1).
Re Claim 16 Jain in view of Thong and Chern teaches the semiconductor device of claim 11, but does not teach dielectric walls extending in the second direction, and configured to separate the first active region, the second active region and the third active region from each other.
Jung teaches dielectric walls (DB, FIG. 6, [0120] states, “The plurality of diffusion breaks DB may be filled with an insulator.”) extending in the second direction (vertically), and configured to separate the first active region (RX2, SC102) [0031], the second active region (RX4, FC101) [0032] and the third active region (RX2, SC104) from each other.
The ordinary artisan would have been motivated to modify Jung in combination with Jain in view of Thong and Chern in the above manner for the motivation of adding a dielectric/insulator layer around the active body regions to ensure region integrity and that the current signals are shorted between bodies and ensure the semiconductor device functions optimally. [0004] states, “In particular, as the demand for reliability of the miniaturized semiconductors devices increases, there is a need for a layout design capable for improving electrical characteristics of semiconductor devices and securing the reliability of the miniaturized semiconductor devices.” It has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Jung into the structure of Jain in view of Thong and Chern.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Jain (US 8759885 B1) in view of Thong (CN 114649344 A) and Chern (US 20100223585 A1) and Jung (US 20220310586 A1) as applied to claims 11 and 16 above, and further in view of Azuma (US 20030222319 A1) and Chang (US 20120306000 A1).
Re Claim 17 Jain in view of Thong and Chern and Jung teaches the semiconductor device of claim 16 but does not teach spacers extending in the second direction on the sidewalls of the first gate electrode, the second gate electrode, the third gate electrode and the dielectric walls.
Azuma teaches spacers (26), Fig. 8a) [0038] extending in the second direction (would be vertical direction from top view) on sidewalls of each of the first gate electrode (24) [0036], the second gate electrode (repeat for 2nd and 3rd gate electrodes), and the third gate electrode.
The ordinary artisan would have been motivated to modify Azuma in combination with Jain in view of Thong and Chern and Jung in the above manner for the motivation of add dielectric layers around the gate electrodes to ensure the current is not leaked from the electrodes and the device remains to function at an optimal level as the industry demands scaling down device seizes. [0002] states, “With the increasing miniaturization of semiconductor elements in recent years, a demand has risen for technologies to achieve the following: reduction of the gate length of the transistor, reduction of the thickness of the gate oxide film, reduction of the film thickness of the electrode side wall spacer, and shallowing of junctions.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Azuma into the structure of Jain in view of Thong and Chern and Jung.
Jain in view of Thong and Chern and Jung and Azuma does not teach the spacers on the dielectric walls.
Chang teaches the spacers (702, FIG. 7A &B) [0029] dielectric walls (502 layer that extends undivided in vertical direction, FIG. 7A).
The ordinary artisan would have been motivated to modify Chang in combination with Jain in view of Thong and Chern Jung and Azuma in the above manner for the motivation of joining the spacer layer to the dielectric sidewalls to ensure semiconductor device integrity and the body is structurally steady to ensure device integrity. [0002] states, “During the course of the device fabrication, the space between line ends tends to undesirably grow larger due to processes such as dry or wet etches that erode short edges faster than long edges. This eventual growth in end-to-end spacing is anticipated in the initial design and layout of the gate pattern. Spaces in between gates are filled by dielectric during the course of fabrication, either spacer material, liner material or middle-of-the-line dielectric material.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Chang into the structure of Jain in view of Thong and Chern and Jung and Azuma.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/20/26
Prosecution Insights