DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1-3, 5-15, is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Cheng et al., US 2021/0183844 A1.
Claim 1. Cheng et al., disclose a method for forming a package structure (such as the steps in figs. 1, 2, 5), comprising:
-forming an interconnect structure (items 164) in a substrate (item 160);
-bonding a chip (110/120) over the substrate and electrically connected to the interconnect structure;
-bonding a plurality of dies (item 130) over the substrate and adjacent to the chip;
-supplying a molding material (item 132) to a gap (item S1) between the chip and the dies (this limitation would read through [0014] wherein is disclosed a space around the first semiconductor devices 110 and the second semiconductor devices 120 are partially occupied, thus a volume of an encapsulant to be filled in this space (e.g., the encapsulant 132 as illustrated with reference to FIG. 2C);
-and after supplying the molding material to the gap between the chip and the dies, thinning down the substrate (this limitation would read [0020] wherein is disclosed for instance, the planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process or combinations thereof).
Claim 2. Cheng et al., disclose the method as claimed in claim 1, further comprising: forming a plurality of bump structures (item 168, fig. 5) on the exposed interconnect structure, wherein a bottom surface of the interconnect structure is exposed after thinning down the substrate, and the bump structures are connected to the bottom surface of the interconnect structure (as seen in the structure of fig. 5, [0023]).
Claim 3. Cheng et al., disclose the method as claimed in claim 1, further comprising: forming a bonding film over the substrate; and forming a plurality of bonding pads in the bonding film, wherein the bonding pads are distributed more densely in a first region overlapping the chip than a second region overlapping the dies (as seen in the structure of fig. 5, [0023], item 124).
Claim 5. Cheng et al., disclose the method as claimed in claim 1, wherein the dies comprise a plurality of thermal-dissipation dies (item 130) that are electrically isolated from the chip.
Claim 6. Cheng et al., disclose the method as claimed in claim 5, wherein the thermal-dissipation dies are symmetrically arranged around the chip (this limitation would read [0029] wherein is disclosed semiconductor package 10 includes the first semiconductor device 110 and a plurality of the second semiconductor devices 120 arranged along a side of the first semiconductor device 110, and further includes at least one of the dummy dies 130 (e.g., two of the dummy dies 130) located aside these second semiconductor devices 120).
Claim 7. Cheng et al., disclose the method as claimed in claim 1, further comprising: forming a plurality of trenches on a first surface of a substrate; filling a conductive material to form a plurality of through-substrate via (TSV) structures in the substrate; forming a dielectric layer over the first surface of the substrate; forming a plurality of metallization patterns in the dielectric layer, wherein the metallization patterns are electrically connected to the TSV structures.
Claims 8-15. Cheng et al., a method for forming a package structure (such as the steps in figs. 1, 2, 5), comprising:
-forming a plurality of through-substrate via (TSV) structures (item 166) in a substrate (item 160);
-bonding a chip (item 110/120) over a first surface of the substrate and electrically connected to a first plurality of the TSV structures;
-bonding a thermal-dissipation die (item 270) over the first surface of the substrate and adjacent to the chip, wherein the thermal-dissipation die overlaps a second plurality of the TSV structures in a normal direction perpendicular to the first surface (as seen in the structure of fig. 2);
-supplying a molding material (item 132) to a gap (item S1) between the chip and the thermal-dissipation die;
-and thinning down the substrate from a second surface opposite the first surface after supplying the molding material to the gap between the chip and the thermal-dissipation die (this limitation would read [0020] wherein is disclosed for instance, after removing the top portion of the encapsulant 132, the exposed top surfaces of the conductive pillars 116, the polymer layer 118 and the conductive pillars 128 may be substantially coplanar with each other).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 4, is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al., US 2021/0183844 A1, in view of Kim, US 2021/0225772 A1.
Claim 4. Cheng et al., disclose the method as claimed in claim 3, wherein forming the interconnect structure in the substrate.
Cheng et al., appear to not specify all the details with respect to the through-substrate via (TSV) structures, most likely wherein a width of the TSV structures gradually decreases from the first surface to the second surface.
However, in a similar package, fig. 2 of Kim shows through-silicon-vias (TSVs) 112, wherein a width of the TSV structures gradually decreases from the first surface to the second surface. Therefore, it would have been obvious to one having skill in the art before the effective filing date of the claimed invention to modify the device of Cheng et al., in view of Kim, including providing at least one width of the TSV structures gradually decreases from the first surface to the second surface, in order to improve performance and integration, while simultaneously managing several critical manufacturing and reliability challenges inherent to TSV technology. As noted, smaller TSVs reduce the physical distance for signals to travel between stacked chips, which significantly improves chip integration, increases data transfer rates, and enhances overall system performance.
Allowable Subject Matter
6. Claims 16-20 are allowed.
Reasons for Allowance
7. The following is an examiner's statement of reasons for allowance:
8. Regarding claims 16-20, the prior art failed to disclose or reasonably suggest wherein a width of the TSV structures gradually decreases from the first surface to the second surface; a chip bonded to the first surface of the substrate and located over the TSV structures, wherein a bottom surface of the chip is closer to the first surface than the second surface; a plurality of dies bonded to the first surface of the substrate and located adjacent to the chip; a molding material between the chip and the dies, wherein the molding material is located over the first surface and the bottom surface of the chip; and a plurality of bump structures connected to the TSV structures on the second surface.
Response to Arguments
9. Applicant's arguments filed 03/02/2026 have been fully considered but they are not persuasive.
Applicant respectfully submits that the Examiner has not provided any evidence showing that Cheng and Kim disclose that thinning down the substrate from a second surface opposite the first surface after supplying the molding material to the gap between the chip and the thermal-dissipation die. As amended, claim 8 includes the feature corresponding to the above-emphasized feature in the original claim 1, and therefore Applicant respectfully submits that claim 8 is allowable.
This argument is not persuasive. It is noted that the steps from the structure of figs. 2B through 2D, which is/are similar to applicant’s figs. 1C-1E. Therefore, the reference meets the limitation of “thinning down the substrate from a second surface opposite the first surface after supplying the molding material to the gap between the chip and the thermal-dissipation die” as in the claim.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/ Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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