Prosecution Insights
Last updated: July 17, 2026
Application No. 18/327,557

LEAKAGE ANALYSIS ON SEMICONDUCTOR DEVICE

Non-Final OA §102
Filed
Jun 01, 2023
Priority
Jan 16, 2019 — provisional 62/793,350 +2 more
Examiner
TAT, BINH C
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1061 granted / 1215 resolved
+19.3% vs TC avg
Moderate +14% lift
Without
With
+14.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
22 currently pending
Career history
1239
Total Applications
across all art units

Statute-Specific Performance

§101
5.7%
-34.3% vs TC avg
§103
1.8%
-38.2% vs TC avg
§102
87.9%
+47.9% vs TC avg
§112
0.1%
-39.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1215 resolved cases

Office Action

§102
CTNF 18/327,557 CTNF 74962 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. DETAILED ACTION This office action is in response restriction/election filed on 05/21/26. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97(b) (3). Accordingly, the information disclosure statement is being considered by the examiner. Summary of claims Claims 1-33 are pending. Claims 1-7 and 21-33 are rejected. Claims 8-20 are cancelled. Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). Claims 1-7 and 21-33 provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of US Patent 11714949. Although the conflicting claims are not identical, they are not patentably distinct from each other. This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented. As claims 1-7 and 21-33 the scope of the claimed limitation of the instant application is essentially the same as claimed limitations of claims 1-20 of US Patent 11714949. Claims 1-7 and 21-33 provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of US Patent 11030381. Although the conflicting claims are not identical, they are not patentably distinct from each other. This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented. As claims 1-7 and 21-33 the scope of the claimed limitation of the instant application is essentially the same as claimed limitations of claims 1-20 of US Patent 11030381. Claims 1-7 and 21-33 provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of US Patent 11720738. Although the conflicting claims are not identical, they are not patentably distinct from each other. This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented. As claims 1-7 and 21-33 the scope of the claimed limitation of the instant application is essentially the same as claimed limitations of claims 1-20 of US Patent 11720738. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-4, 21-24 and 31-33 rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Tam et al. (US Pub. 2015/0067624) . As to claims 1 the prior art teach a method performed by a computer system, comprising: searching leakage current values of associated with cell abutment cases which are associated with terminal types of abutted cells of a semiconductor device (see fig 1-4 paragraph 0018-0021); determining leakage probabilities according to the cell abutment cases (see fig 2-4 paragraph 0020-0024); calculating expected boundary leakages between the abutted cells based on the leakage probabilities and the leakage current values (see fig 2-5 paragraph 0026-0030); and generating a layout of the semiconductor device according to the expected boundary leakages, wherein two of the leakage probabilities correspond to two of the cell abutment cases, respectively, and the two of the leakage probabilities are different from each other when the two of the cell abutment cases are different from each other (see fig 4-6 paragraph 0032-0042). As to claim 2 and 22 the prior art teach wherein one of the two of the leakage probabilities corresponds to a source-source abutment of the two of the cell abutment cases (see fig 4-6 paragraph 0041-0045). As to claim 3 and 23, the prior art teach wherein another one of the two of the leakage probabilities is larger than the one of the two of the leakage probabilities (see fig 4-6 paragraph 0043-0046). As to claim 4 and 24 the prior art teaches wherein one of the two of the leakage probabilities corresponds to two cell edges of the abutted cells, a voltage difference between the two cell edges is zero, and another one of the two of the leakage probabilities is larger than the one of the two of the leakage probabilities (see fig 3-6 paragraph 0030-0038). As to claim 21 the prior art teaches a method performed by a computer system, comprising: searching leakage current values of associated with cell abutment cases which are associated with terminal types of abutted cells of a semiconductor device (see fig 1-4 paragraph 0018-0021); determining leakage probabilities according to the cell abutment cases (see fig 2-4 paragraph 0020-0024); calculating expected boundary leakages between the abutted cells based on the leakage probabilities and the leakage current values; generating a layout of the semiconductor device according to the expected boundary leakages (see fig 2-5 paragraph 0026-0030); and determining the leakage current values according to cell edge types of the abutted cells, wherein two of the leakage probabilities correspond to two of the cell abutment cases, respectively, and the two of the leakage probabilities are different from each other when the two of the cell abutment cases are different from each other (see fig 4-6 paragraph 0032-0042). As to claim 31 the prior art teaches a method performed by a computer system, comprising: searching leakage current values of associated with cell abutment cases which are associated with terminal types of abutted cells of a semiconductor device (see fig 1-4 paragraph 0018-0021); determining leakage probabilities according to the cell abutment cases (see fig 2-4 paragraph 0020-0024); calculating expected boundary leakages between the abutted cells based on the leakage probabilities and the leakage current values (see fig 2-5 paragraph 0026-0030); generating a layout of the semiconductor device according to the expected boundary leakages, wherein two of the leakage probabilities correspond to two of the cell abutment cases, respectively, the two of the leakage probabilities are different from each other when the two of the cell abutment cases are different from each other, wherein determining the leakage probabilities according to the cell abutment cases comprising: determining one of the leakage probabilities according to a first boundary portion of the abutted cells (see fig 4-6 paragraph 0032-0042); and determining another one of the leakage probabilities according to a second boundary portion of the abutted cells (see fig 4-6 paragraph 0040-0044). As to claim 32 the prior art teaches wherein the first boundary portion and the second boundary portion are abutted with each other and different from each other (see fig 4-6 paragraph 0042-0045). As to claim 33 the prior art teaches wherein the first boundary portion and the second boundary portion correspond to a first region and a second region, respectively, a first conductive type of the first region is different from a second conductive type of the second region, and the first region and the second region are abutted with each other (see fig 4-6 paragraph 0043-0047) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 5-7 and 25-30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BINH C TAT/Primary Examiner, Art Unit 2851 Application/Control Number: 18/327,557 Page 2 Art Unit: 2851 Application/Control Number: 18/327,557 Page 3 Art Unit: 2851 Application/Control Number: 18/327,557 Page 5 Art Unit: 2851 Application/Control Number: 18/327,557 Page 6 Art Unit: 2851 Application/Control Number: 18/327,557 Page 7 Art Unit: 2851 Application/Control Number: 18/327,557 Page 9 Art Unit: 2851
Read full office action

Prosecution Timeline

Jun 01, 2023
Application Filed
Jun 16, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12675628
SEMICONDUCTOR STRUCTURE OF CELL ARRAY WITH ADAPTIVE THRESHOLD VOLTAGE
4y 3m to grant Granted Jul 07, 2026
Patent 12675629
METHOD AND SYSTEM FOR MANUFACTURING A SEMICONDUCTOR DEVICE
4y 0m to grant Granted Jul 07, 2026
Patent 12670310
SYSTEM AND METHOD FOR DIAGNOSING DESIGN RULE CHECK VIOLATIONS
2y 0m to grant Granted Jun 30, 2026
Patent 12665443
System and Method for Purchasing Wireless Battery Charge for Electronic Devices
3y 11m to grant Granted Jun 23, 2026
Patent 12664340
INTERACTIVELY PRESENTING FOR MINIMUM OVERLAP SHAPES IN AN IC DESIGN
3y 7m to grant Granted Jun 23, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+14.2%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1215 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month