Attorney’s Docket Number: 20223955/ 2406 I.4746US01
Filing Date: 06/01/2023
Claimed Foreign Priority Date: none
Applicants: Wu et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Election filed on 01/26/2026.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Group Invention I, drawn to a method of making a semiconductor structure, in the reply filed on 01/26/2026, is acknowledged. Applicant cancelled claims 17-20, added new claims 21-24, and indicated that claims 1-16 and 21-24 read on the elected Group invention. The examiner agrees. Accordingly, pending in this application are claims 1-16 and 21-24.
Drawings
The drawings are objected to because of multiple discrepancies between depictions of intermediate method steps, thus affecting the clarity of the invention:
- Figs. 2D, 3D, 4D, 5D, 6D, 7D, 8D, and 9D depict cross-section views of a FinFET along the y2--y2’ cutline, with substrate 202 and fin 206 dimensions that are inconsistent with thicknesses of the same features along other cross-section views. For example, the thickness of substrate 202 in Fig. 2D should be similar to the thickness of 202 in Figs. 2B or 2C, while the height of fin 206 above substrate 202 in Fig. 2D should be similar to the height of 206 above 202 in Fig. 2B
- Figs. 5A, 6A, 7A, 8A, and 9A depict top views of a FinFET. However, S/D regions 402 and STI 204 therebetween should not be visible in these top views, because they are covered at least by ILD 502. Only channel portions of fins 206 and STI 204 exposed by trenches 504 should be visible.
- Figs. 6E, 7E, 8E, and 9E depict cross-section views of a FinFET along the x2--x2’ cutline, wherein fins 206 are depicted with their initial height and covered by ILD 502. However, a cutline along x2--x2’ (i.e., between gate trenches 504 or later metal gates 900) should instead depict fins 206 as substantially recessed (e.g., Specification, Par. [0025]: between 20% and 90% of FH1), with epi source/drain regions 402 formed thereupon, and further covered by ILD 502, as depicted according to their cross-section views along the y2--y2’ cutline, in Figs. 6D, 7D, 8D, and 9D, respectively.
- Figs. 7A, 8A, and 9A are missing gate spacers 304.
- Fig. 7D: replace the cross-section view labeling y1--y1’ with y2--y2’
- Figs. 8B and 9B: replace the cross-section view labeling x1--x1’ with x--x’ in accordance with the labeling of Figs. 8A and 9A respectively.
- Fig. 9C: replace the leftmost thickness label D2 with D1, as D2 is the thickness of etched STI 204 below metal gate 904 (see, e.g., Par. [0042])
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. No new matter should be added. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US2021/0125833).
Regarding Claim 1, Lin (see, e.g., Figs. 1-15 and par. [0019]-[0064]) shows all aspects of the instant invention, including a method, comprising:
- forming a first semiconductor structure (e.g., semiconductor fin 64A) extending from a substrate (e.g., substrate 50) in a first direction (e.g., vertical direction), wherein the first semiconductor structure has a height along the first direction and the first semiconductor structure extends lengthwise along a second direction (see, e.g., Fig. 1: A--A direction) that is different than the first direction (see, e.g., Fig. 3)
- forming a second semiconductor structure (e.g., semiconductor fin 64B) that extends from the substrate in the first direction, wherein the second semiconductor structure extends lengthwise along the second direction (see, e.g., Fig. 3)
- forming an isolation structure (e.g., isolation region 62) over the substrate and extending between the first semiconductor structure and the second semiconductor structure in a third direction (see, e.g., Fig. 1: B--B direction) that is different than the second direction (see, e.g., Fig. 4)
- forming a dummy gate structure (e.g., dummy gate structure 75) on the substrate over the first semiconductor structure and the isolation structure, wherein the dummy gate structure extends lengthwise along the third direction (see, e.g., Figs. 5A-B)
- removing the dummy gate structure to form a trench (e.g., recess 88) exposing an upper surface of the isolation structure (see, e.g., Figs. 13A-B)
- etching the isolation structure exposed in the trench to recess the isolation structure (e.g., etch of 62 defining concave upper surface 62U2) (see, e.g., Fig. 14A)
- after etching the isolation structure, forming a metal gate structure (e.g., metal gate structure 97) in the trench and on the recessed isolation structure (see, e.g., Figs. 15A-B).
Regarding Claim 2, Lin (see, e.g., Figs. 10-11 and Par. [0050]) shows:
- after forming the dummy gate structure, recessing the first semiconductor structure and epitaxially growing a source/drain (e.g., epi source/drain region 80) in the recessed first semiconductor structure.
Regarding Claim 3, Lin (see, e.g., Figs. 11-13 and Par. [0047],[0055]) shows:
- forming gate spacers (e.g., gate spacers 87) on the dummy gate structure (see, e.g., Figs. 11A-B).
- wherein the forming the trench (e.g., 88) forms the trench defined between the gate spacer (see, e.g., Figs. 13A-B)
Regarding Claim 4, Lin (see, e.g., Figs. 14A-B and Par. [0056]) discloses that a passivation gas is used to tune the etching selectivity of the second etching process, so as to advantageously reduce or avoid damage to the gate spacers 87. Therefore, Lin shows that the etching the isolation structure is a selective etch that leaves the gate spacers (e.g., 87) substantially unetched (see, e.g., Figs. 13A vs. 14A).
Regarding Claim 6, Lin (see, e.g., Figs. 14A-B and Par. [0056]-[0057]) discloses that the etching process resulting in the recessing of top surface of isolation region 62 can be a plasma etching process, which is a readily known in the semiconductor manufacturing art as an exemplary anisotropic etching process (see, e.g., Par. [0040]). Accordingly, Lin shows that the etching the isolation structure (e.g., 62) is an anisotropic etch (e.g., plasma etching process).
Regarding Claim 9, Lin (see, e.g., Figs. 13A-B,14A-B and Par. [0055]-[0057]) shows that wherein the height of the first semiconductor structure in the first direction is measured from a top surface of the isolation structure and wherein after the etching the isolation structure, the first semiconductor structure has an increased height in the first direction measured from the top surface of the isolation structure (see, e.g., Figs. 13A-B: height of 64 from pre-etch top surface 62U1 vs. Figs. 14A-B: height of 64 from post-etch top surface 62U2).
Claims 1-4, 9-10, 12-13, 16, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US2015/0270401).
Regarding Claim 1, Huang (see, e.g., Figs. 18-21 and Par. [0038]-[0044]) shows all aspects of the instant invention, including a method, comprising:
- forming a first semiconductor structure (e.g., one of fin-shaped strips 21,23) extending from a substrate (e.g., substrate 20) in a first direction (e.g., vertical direction), wherein the first semiconductor structure has a height along the first direction and the first semiconductor structure extends lengthwise along a second direction (e.g., fin length direction) that is different than the first direction (see, e.g., Fig. 18)
- forming a second semiconductor structure (e.g., another one of fin-shaped strips 21,23) that extends from the substrate in the first direction, wherein the second semiconductor structure extends lengthwise along the second direction (see, e.g., Fig. 18)
- forming an isolation structure (e.g., STI region 22) over the substrate and extending between the first semiconductor structure and the second semiconductor structure in a third direction (e.g., gate direction) that is different than the second direction (see, e.g., Fig. 18)
- forming a dummy gate structure (e.g., comprising dummy gate 32 and dummy oxide 30) on the substrate over the first semiconductor structure and the isolation structure, wherein the dummy gate structure extends lengthwise along the third direction (see, e.g., Fig. 19)
- removing the dummy gate structure to form a trench (e.g., recess 58) exposing an upper surface of the isolation structure (see, e.g., Fig. 20: region 22A of STI is exposed by the first etch)
- etching the isolation structure exposed in the trench to recess the isolation structure (e.g., region 22A of STI is further recessed by a second etch to expose the material of semiconductor strip 21) (see, e.g., Figs. 21A-B)
- after etching the isolation structure, forming a metal gate structure (e.g., metal gate 52 of gate stack 54) in the trench and on the recessed isolation structure (see, e.g., Figs. 12A and Par. [0027],[0044]).
Regarding Claim 2, Huang (see, e.g., Fig. 19-20 and Par. [0040]-[0041]) shows:
- after forming the dummy gate structure, recessing the first semiconductor structure (e.g., recesses 38) and epitaxially growing a source/drain (e.g., epi source/drain region 40) in the recessed first semiconductor structure.
Regarding Claim 3, Huang (see, e.g., Fig. 19 and Par. [0040]) shows:
- forming gate spacers (e.g., gate spacers 36) on the dummy gate structure (see, e.g., Fig. 19).
- wherein the forming the trench (e.g., 58) forms the trench defined between the gate spacer (see, e.g., Fig. 20)
Regarding Claim 4, Huang (see, e.g., Figs. 21A-B and Par. [0043]-[0044]) shows that the recessing of exposed STI region 22A between gate spacers 36 at least partially exposes semiconductor strip 21 without any noticeable modification to the arrangement of gate spacers 36. Therefore, Lin shows that the etching the isolation structure is a selective etch that leaves the gate spacers (e.g., 36) substantially unetched (see, e.g., Fig. 20 vs. 21).
Regarding Claim 9, Huang (see, e.g., Figs. 18, 21 and Par. [0043]-[0044]) shows that wherein the height of the first semiconductor structure in the first direction is measured from a top surface of the isolation structure (see, e.g., Fig. 18: height of feature 23) and wherein after the etching the isolation structure, the first semiconductor structure has an increased height in the first direction measured from the top surface of the isolation structure (see, e.g., Figs. 21A-B: increased height of feature 24 comprising feature 23 and a portion of feature 21).
Regarding Claim 10, Huang (see, e.g., Figs. 18-21 and Par. [0038]-[0044]) shows all aspects of the instant invention, including a method, comprising:
- forming a first fin and a second fin (e.g., two adjacent fin-shaped strips 21,23) that extend above a substrate (e.g., substrate 20) (see, e.g., Fig. 18)
- forming an isolation region (e.g., STI region 22) between the first fin and the second fin, wherein the first fin and second fin have a first fin height (e.g., height of feature 23) above the isolation region (see, e.g., Fig. 18)
- forming a gate stack (e.g., comprising dummy gate 32 and dummy oxide 30) over the first fin, the second fin, and the isolation region (see, e.g., Fig. 19)
- growing an epitaxial source/drain feature (e.g., epi source/drain region 40) in a source/drain region of the first fin (see, e.g., Fig. 20)
- after the growing, removing the gate stack to form a trench (see, e.g., Fig. 20 and Par. [0042]: gate stack removed to define recess 58 between gate spacers 36)
- selectively etching the isolation region within the trench between the first fin and the second fin (see, e.g., Fig. 20 vs. 21, and Par. [0043]-[0044]: etching of exposed STI region 22A in recess 58 does not induce any noticeable modification to the arrangement of surrounding features), wherein after the selectively etching the first fin has a second fin height above the isolation region within the trench, the second fin height greater than the first fin height (see, e.g., Figs. 21A-B: increased height of feature 24 comprising feature 23 and a portion of feature 21).
Regarding Claim 12, Huang (see, e.g., Fig. 20 and Par. [0042]) shows:
- depositing an interlayer dielectric material (ILD) (e.g., ILD 46) after growing the epitaxial source/drain feature.
Regarding Claim 13, Huang (see, e.g., Figs. 21B and Par. [0044]) discloses that only the fin portion exposed in trench 58 exhibits an increased height due to the recessing of exposed STI region 22A, while all other portions of the fin are masked by buffer oxide layer 42, CESL 44, and ILD 46. Therefore, Huang shows that wherein after the selectively etching the isolation region within the trench, a portion of the first fin under the ILD maintains the first fin height.
Regarding Claim 16, Huang (see, e.g., Figs. 12A and Par. [0027],[0044]) shows forming a metal gate structure (e.g., metal gate 52 of gate stack 54) on the first fin and the second fin.
Regarding Claim 21, Huang (see, e.g., Figs. 18-21 and Par. [0038]-[0044]) shows all aspects of the instant invention, including a method, comprising:
- forming a first active region and a second active region (e.g., two adjacent fin-shaped strips 21,23) having an isolation region (e.g., STI region 22) disposed between the first active region and the second active region (see, e.g., Fig. 18)
- forming a dummy gate stack (e.g., comprising dummy gate 32 and dummy oxide 30) over the first active region, the second active region, and the isolation region (see, e.g., Fig. 19)
- providing spacer elements (e.g., gate spacers 36) along the dummy gate stack (see, e.g., Fig. 19)
- removing the dummy gate stack to form a trench (see, e.g., Fig. 20 and Par. [0042]: gate stack removed to define recess 58 between gate spacers 36)
- recessing the isolation region between the first active region and the second active region within the trench (e.g., region 22A of STI is further recessed to expose the material of semiconductor strip 21) by an etching process selective to isolation region without substantial etching of the spacer elements (see, e.g., Fig. 20 vs. 21, and Par. [0043]-[0044]: etching of exposed STI region 22A in recess 58 does not induce any noticeable modification to the arrangement of surrounding features)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US2015/0270401).
Regarding Claim 5, while Huang is silent about an etch particular selectivity ratio between a material of the gate spacers 36 and a material of the isolation structure 22, he clearly suggests that a high etching selectivity is achieved between the materials, because only the exposed STI region 22A undergoes substantial recessing while gate spacers 36 remain unaffected (see, e.g., Figs. 21A-B and Par. [0043]-[0045]). Therefore, Huang recognizes the etching selectivity ratio between the gate spacer and isolation materials as a result effective variable.
Accordingly, the specific etch selectivity ratio between a material of the gate spacers and a material of the isolation structure claimed by the applicant, i.e, about 1:10, is only considered to be the “optimum” selectivity ratio disclosed by Huang that a person having ordinary skill in the art would have been able to obtain using routine experimentation based, among other things, on the gate spacer and isolation materials, etching type, etchant chemistry, etc. (see In re Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained as long as an etching process is performed to solely recess an exposed STI region between gate spacers, thus forming a channel region of a finFET with improved overall mobility and electrical performance, as suggested by Huang.
Regarding Claim 11, Huang (see, e.g., Fig. 19) shows forming gate spacers (e.g., gate spacers 36) on the gate stack. Furthermore, while Huang is silent about an particular etch selectivity ratio of isolation region 22 to gate spacers 36, he clearly suggests that a high etching selectivity is achieved between the materials, because only the exposed STI region 22A undergoes substantial recessing while gate spacers 36 remain unaffected (see, e.g., Figs. 21A-B and Par. [0043]-[0045]). Therefore, Huang recognizes the etching selectivity ratio between the gate spacer and isolation materials as a result effective variable. Also, see comments stated above in Par. 29 with regards to Claim 5, which are considered repeated here, as applied to the etch selectivity of the isolation region to the gate spacers being at least above 10:1.
Claims 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US2015/0270401) in view of Su et al. (US2021/0036130).
Regarding Claim 8, Huang (see, e.g., Figs. 21A-B and Par. [0043]-[0045]) shows that recessing an exposed STI region 22A between gate spacers 36 results in an improved channel region 24. However, Huang is silent about a step of: after etching the isolation structure and prior to forming the metal gate structure, etching the first semiconductor structure to decrease a dimension in the third direction.
Su (see, e.g., Figs. 9 and 14 and Par. [0017]), on the other hand and in the same field of endeavor, teaches that a fin-thinning process can be performed to thin the width of semiconductor strips 126/226 after the removal of dummy gate stack 30, in order to improve the gate control of the resulting FinFET and to reduce the fin-width variation.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the step as claimed in the method of Huang, as taught by Su, to improve the gate control of the resulting FinFET and to reduce the fin-width variation. Therefore, Huang in view of Su teaches that after etching the isolation structure and prior to forming the metal gate structure, etching the first semiconductor structure to decrease a dimension in the third direction.
Regarding Claim 14, Huang (see, e.g., Figs. 21A-B and Par. [0043]-[0045]) shows that selectively etching an exposed STI region 22A between gate spacers 36 results in an improved channel region 24. However, Huang is silent about a step of trimming a width of the first fin within the trench. Also, see comments stated above in Par. 33-34 with regards to Claim 14, which are considered repeated here. Therefore, Huang in view of Su teaches that after the selectively etching, trimming a width of the first fin within the trench.
Claims 6 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US2015/0270401) in view of Chiang (US2018/0301558).
Regarding Claim 6, while Huang (see, e.g., Par. [0031],[0043]-[0044]) discloses that top surfaces of STI region 22 can be recessed by chemical etching, he is silent about the etching the isolation structure being an anisotropic etch. Chiang (see, e.g., Par. [0021]), on the other hand and in the same field of endeavor, teaches that isolation structures 120 can be recessed by a selective wet etch or a selective dry etch, wherein the selective dry etch can be performed anisotropically.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed, to have the step of etching the isolation structure being an anisotropic etch in the method of Huang, because it is known in the semiconductor manufacturing art that isolation structures can be selectively recessed by an anisotropic dry etch process, as suggested by Chiang, and applying a known method step for its conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 22, while Huang (see, e.g., Figs. 21A-B and Par. [0031], [0043]-[0045]) discloses that top surfaces of STI region 22 can be recessed by a chemical etching process resulting in recesses with substantially vertical sidewalls, he is silent about the recessing the isolation region being an anisotropic etching having a substantially vertical direction. Chiang (see, e.g., Par. [0020]-[0021]), on the other hand and in the same field of endeavor, teaches that isolation structures 120 can be recessed by a selective wet etch or a selective dry etch, wherein the selective dry etch can be performed by an anisotropic etching having a substantially vertical direction (see, e.g., Figs. 3A-3B: recesses 122 have substantially vertical sidewalls with no lateral under-etch of isolation material 120). Also, see comments stated above in Par. 38 with regards to Claim 6, which are considered repeated here. Therefore, Huang in view of Chiang teaches that the recessing the isolation region is an anisotropic etching having a substantially vertical direction.
Allowable Subject Matter
Claims 7, 15, and 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose methods of manufacturing FinFETs by a gate replacement process, and comprising steps of recessing an STI, similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814