DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 12/9/2025 that has been entered, wherein claims 1-15 and 21-25 are pending and claims 16-20 are canceled.
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-15 and 21-25 in the reply filed on 12/9/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/20/2024, 4/3/2025, 9/12/2025 and 12/1/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9 and 11-15 and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Suga et al. (US 2003/0164394 A1) as cited in the IDS of 9/12/2025 in view of Yamada et al. (JP S63-293952 A).
Regarding claim 1, Suga teaches a method of forming a bonded assembly(Fig. 1), the method comprising:
providing a first packaging substrate(2c in process chamber 6, ¶0032-33) and a second packaging substrate(2c in cleaning chamber 5, ¶0032-33) in a low-oxygen ambient(¶0014);
providing a first semiconductor package(2a in process chamber 6, ¶0032-33, wherein “chip” is known in the art as a semiconductor element, see Yamada, ¶0001) and a second semiconductor package(2a in cleaning chamber 5, ¶0032-33) in the low-oxygen ambient(¶0014);
performing a first plasma package-treatment process(3, ¶0034) on the first semiconductor package(2a in process chamber 6, ¶0032-33) in the low-oxygen ambient(¶0014) while performing a first substrate-treatment process(3, ¶0034) on the first packaging substrate(2c in process chamber 6, ¶0032-33) in a low-oxygen ambient(¶0014); and
performing a second plasma package-treatment process(3, ¶0034) on the second semiconductor package(2a in cleaning chamber 5, ¶0032-33) while performing a second substrate-treatment process(3, ¶0034) on the second packaging substrate(2c in cleaning chamber 5, ¶0032-33) and while bonding(¶0049, wherein the bonding and the next cleaning proceed simultaneously) the first semiconductor package(2a in process chamber 6, ¶0032-33) to the first packaging substrate(2c in process chamber 6, ¶0032-33).
Suga is not relied on to teach low-oxygen ambient(¶0014) having an oxygen partial pressure that is lower than 17 kPa. Suga does teach the plasma package-treatment process(3, ¶0034) is performed at atmospheric-pressure plasma(¶0016).
Yamada teaches a method of forming a bonded assembly(Figs. 1-3), wherein a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa(10^-4 to 10^-1 torr =1.3 X 10^-5 to 0.012 kPa). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Suga, to include a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa, as taught by Yamada, so that solder balls can be formed with high reliability without using flux(¶0001).
Regarding claim 2, Suga teaches the method of Claim 1, further comprising bonding the second semiconductor package(2a in cleaning chamber 5, ¶0032-33) to the second packaging substrate(2c in cleaning chamber 5, ¶0032-33) after bonding the first semiconductor package(2a in process chamber 6, ¶0032-33) to the first packaging substrate(2c in process chamber 6, ¶0032-33).
Regarding claim 3, Suga teaches the method of Claim 2, further comprising:
providing a third packaging substrate(2c, ¶0032-33, ¶0049) in the low-oxygen ambient(¶0014);
providing a third semiconductor package(2a, ¶0032-33, ¶0049) in the low-oxygen ambient(¶0014); and
performing a third plasma package-treatment process(3, ¶0034) on the third semiconductor package(2a, ¶0032-33, ¶0049) and performing a third substrate-treatment process(3, ¶0034) on the third packaging substrate(2c, ¶0032-33, ¶0049) while bonding(¶0049, wherein the bonding and the next cleaning proceed simultaneously) the second semiconductor package(2a in cleaning chamber 5, ¶0032-33) to the second packaging substrate(2c in cleaning chamber 5, ¶0032-33).
Regarding claim 4, Suga teaches the method of Claim 1, wherein the first packaging substrate(2c in process chamber 6 corresponding to 2a, ¶0032-33) and the second packaging substrate(2c in cleaning chamber 5 corresponding to 2b, ¶0032-33) are portions of a wafer(2c, ¶0032-33) that are laterally spaced apart among one another.
Regarding claim 5, Suga teaches the method of Claim 1, wherein:
the first semiconductor package(2a in process chamber 6, ¶0032-33) comprises first package-side bonding structures(22, ¶0040) to which first solder material portions(¶0040) are attached; and
the first plasma package-treatment process(3, ¶0034) cleans the first solder material portions(¶0040, ¶0016).
Regarding claim 6, Suga teaches the method of Claim 5, wherein:
the first packaging substrate(2c in process chamber 6, ¶0032-33) comprise first substrate-side bonding structures(¶0016, ¶0033 portion to be bonded); and
the first substrate-treatment process(3, ¶0034) cleans the first substrate-side bonding structures(¶0016, ¶0033 portion to be bonded).
Regarding claim 7, Suga teaches the method of Claim 5, wherein the first semiconductor package(2a in process chamber 6, ¶0032-33) is bonded to the first packaging substrate(2c in process chamber 6, ¶0032-33) by the first solder material portions(¶0040, ¶0016) in the low-oxygen ambient(¶0014).
Suga does not explicitly state the first semiconductor package(2a in process chamber 6, ¶0032-33) is bonded to the first packaging substrate(2c in process chamber 6, ¶0032-33) by reflowing the first solder material portions(¶0040, ¶0016). However, Suga does teach the first solder material portions(¶0040, ¶0016) is thermally bonded(¶0040). Reflowing solder via heat is a well-known method to thermally bonded solder material(see Yamada ¶0001). Accordingly, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first semiconductor package is bonded to the first packaging substrate by reflowing the first solder material portions since it has been held to be within the general skill of a worker to apply a known technique to a known device/method to yield predictable results, MPEP2143 (D).
Regarding claim 8, Suga teaches the method of Claim 1, wherein:
the low-oxygen ambient(¶0014) is provided within a process chamber(5, ¶0032) comprising a chamber enclosure that comprises a chamber opening(entrance, ¶0032) and a door(9, ¶0032) configured to fit the chamber opening(entrance, ¶0032);
the first packaging substrate(2c in process chamber 6, ¶0032-33), the second packaging substrate(2c in cleaning chamber 5, ¶0032-33), the first semiconductor package(2a in process chamber 6, ¶0032-33), and the second semiconductor package(2a in cleaning chamber 5, ¶0032-33) are loaded into the process chamber(5, ¶0032) while the door(9, ¶0032) is open; and
the first plasma package-treatment process(3, ¶0034) and the first substrate-treatment process(3, ¶0034) are performed while the door(9, ¶0032) is closed.
Regarding claim 9, Suga teaches the method of Claim 1, wherein:
the low-oxygen ambient(¶0014) is provided in an apparatus(5, ¶0032) configured to sequentially transport the first semiconductor package(2a in process chamber 6, ¶0032-33) and the second semiconductor package(2a in cleaning chamber 5, ¶0032-33) over a plasma nozzle(14, ¶0034);
the first plasma package-treatment process(3, ¶0034) is performed while the first semiconductor package(2a in process chamber 6, ¶0032-33) is positioned over the plasma nozzle(14, ¶0034), the second semiconductor package(2a in cleaning chamber 5, ¶0032-33) is moved over the plasma nozzle after performing the first plasma package-treatment process(3, ¶0034).
Regarding claim 11, Suga teaches a method of forming a bonded assembly(Fig. 1), the method comprising:
providing a wafer(2c, ¶0032-33) comprising a first packaging substrate(2c in process chamber 6 corresponding to 2a, ¶0032-33) and a second packaging substrate(2c in cleaning chamber 5 corresponding to 2b, ¶0032-33) in a low-oxygen ambient(¶0014);
performing a first plasma package-treatment process(3, ¶0034) on a first semiconductor package(2a in process chamber 6, ¶0032-33, wherein “chip” is known in the art as a semiconductor element, see Yamada, ¶0001) in the low-oxygen ambient(¶0014) while performing a first substrate-treatment process(3, ¶0034) on the first packaging substrate(2c in process chamber 6 corresponding to 2a, ¶0032-33) in the low-oxygen ambient(¶0014); and
performing a second plasma package-treatment process(3, ¶0034) on a second semiconductor package(2b in cleaning chamber 5, ¶0032-33) while performing a second substrate-treatment process(3, ¶0034) on the second packaging substrate(2c in cleaning chamber 5 corresponding to 2b, ¶0032-33) and while bonding(¶0049, ¶0033 wherein the bonding and the next cleaning proceed simultaneously) the first semiconductor package(2a in process chamber 6, ¶0032-33) to the first packaging substrate(2c in process chamber 6 corresponding to 2a, ¶0032-33).
Suga is not relied on to teach low-oxygen ambient(¶0014) having an oxygen partial pressure that is lower than 17 kPa. Suga does teach the plasma package-treatment process(3, ¶0034) is performed at atmospheric-pressure plasma(¶0016).
Yamada teaches a method of forming a bonded assembly(Figs. 1-3), wherein a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa(10^-4 to 10^-1 torr =1.3 X 10^-5 to 0.012 kPa). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Suga, to include a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa, as taught by Yamada, so that solder balls can be formed with high reliability without using flux(¶0001).
Regarding claim 12, Suga teaches the method of Claim 11, further comprising bonding(¶0033) the second semiconductor package(2b in cleaning chamber 5, ¶0032-33) to the second packaging substrate(2c in cleaning chamber 5 corresponding to 2b, ¶0032-33) after bonding the first semiconductor package(2a in process chamber 6, ¶0032-33) to the first packaging substrate(2c in process chamber 6 corresponding to 2a, ¶0032-33).
Regarding claim 13, Suga teaches the method of Claim 12.
Suga does not explicitly teach the wafer(2c, ¶0032-33) comprises a third packaging substrate therein; and the method comprises performing a third plasma package-treatment process on a third semiconductor package and performing a third substrate-treatment process on the third packaging substrate while bonding the second semiconductor package(2b in cleaning chamber 5, ¶0032-33) to the second packaging substrate(2c in cleaning chamber 5 corresponding to 2b, ¶0032-33).
However Suga does teach first semiconductor package(2a in process chamber 6, ¶0032-33) and the second semiconductor package(2b in cleaning chamber 5, ¶0032-33) are both bonded to the wafer(2c, ¶0032-33) and bonding a third semiconductor package to the wafer(2c, ¶0032-33) would be a simple duplication of steps. A third semiconductor package to the wafer(2c, ¶0032-33) would result in the wafer(2c, ¶0032-33) comprises a third packaging substrate therein; and the method comprises performing a third plasma package-treatment process on a third semiconductor package and performing a third substrate-treatment process on the third packaging substrate while bonding the second semiconductor package(2b in cleaning chamber 5, ¶0032-33) to the second packaging substrate(2c in cleaning chamber 5 corresponding to 2b, ¶0032-33). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the wafer comprises a third packaging substrate therein; and the method comprises performing a third plasma package-treatment process on a third semiconductor package and performing a third substrate-treatment process on the third packaging substrate while bonding the second semiconductor package to the second packaging substrate, because such duplication would have been considered a mere duplication of parts and has no patentable significance unless a new and unexpected result is produced. MPEP 2144.04 (VI)(B).
Regarding claim 14, Suga teaches the method of Claim 11, wherein:
the first semiconductor package(2a in process chamber 6, ¶0032-33) comprises first package-side bonding structures(22, ¶0040) to which first solder material portions(¶0040) are attached; and
the first plasma package-treatment process(3, ¶0034) cleans the first solder material portions(¶0040, ¶0016).
Regarding claim 15, Suga teaches the method of Claim 14, wherein:
the first packaging substrate(2c in process chamber 6 corresponding to 2a, ¶0032-33) first substrate-side bonding structures(¶0016, ¶0033 portion to be bonded); and
the first substrate-treatment process(3, ¶0034) cleans the first substrate-side bonding structures(¶0016, ¶0033 portion to be bonded),
wherein the first semiconductor package(2a in process chamber 6, ¶0032-33) is bonded to the first packaging substrate(2c in process chamber 6 corresponding to 2a, ¶0032-33) by first solder material portions(¶0040) in the low-oxygen ambient(¶0014).
Suga does not explicitly state the first semiconductor package(2a in process chamber 6, ¶0032-33) is bonded to the first packaging substrate(2c in process chamber 6, ¶0032-33) by reflowing the first solder material portions(¶0040, ¶0016). However, Suga does teach the first solder material portions(¶0040, ¶0016) is thermally bonded(¶0040). Reflowing solder via heat is a well-known method to thermally bonded solder material(see Yamada ¶0001). Accordingly, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first semiconductor package is bonded to the first packaging substrate by reflowing the first solder material portions since it has been held to be within the general skill of a worker to apply a known technique to a known device/method to yield predictable results, MPEP2143 (D).
Regarding claim 21, Suga teaches a method of forming a plurality of bonded assemblies(Fig. 1), the method comprising:
providing a wafer(2c, ¶0032-33) comprising a first packaging substrate(2c in process chamber 6 corresponding to 2a, ¶0032-33) and a second packaging substrate(2c in cleaning chamber 5 corresponding to 2b, ¶0032-33) in a low-oxygen ambient(¶0014);
performing a first bonding process(¶0033, bonding of 2a to 2c) of a first semiconductor package(2a in process chamber 6, ¶0032-33, wherein “chip” is known in the art as a semiconductor element, see Yamada, ¶0001) to the first packaging substrate(2c in process chamber 6 corresponding to 2a, ¶0032-33); and
simultaneously(¶0049, ¶0033 wherein the bonding and the next cleaning proceed simultaneously) with the performance of the first bonding process(¶0033, bonding of 2a to 2c), performing a second plasma treatment process(3, ¶0034) on a second semiconductor package(2b in cleaning chamber 5, ¶0032-33) and a second substrate-treatment process(3, ¶0034) on the second packaging substrate(2c in cleaning chamber 5 corresponding to 2b, ¶0032-33).
Suga is not relied on to teach low-oxygen ambient(¶0014) having an oxygen partial pressure that is lower than 17 kPa. Suga does teach the plasma treatment process(3, ¶0034) is performed at atmospheric-pressure plasma(¶0016).
Yamada teaches a method of forming a bonded assembly(Figs. 1-3), wherein a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa(10^-4 to 10^-1 torr =1.3 X 10^-5 to 0.012 kPa). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Suga, to include a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa, as taught by Yamada, so that solder balls can be formed with high reliability without using flux(¶0001).
Regarding claim 22, Suga teaches the method of Claim 21, wherein the first bonding process(¶0033, bonding of 2a to 2c) is performed at a dedicated first bonding station(6, ¶0032), and the second plasma treatment process(3, ¶0034) is performed at a dedicated second plasma treatment station(5, ¶0032), wherein the first bonding station(6, ¶0032) and the second plasma treatment station(5, ¶0032) are configured to operate independently(¶0049).
Regarding claim 23, Suga teaches the method of Claim 21, further comprising:
initiating the second plasma treatment process(3, ¶0034) on the second semiconductor package(2b in cleaning chamber 5, ¶0032-33) before the first bonding process(¶0033, bonding of 2a to 2c) of the first semiconductor package(2a in process chamber 6, ¶0032-33) is completed(¶0049, ¶0033 wherein the bonding and the next cleaning proceed simultaneously); and
initiating a second bonding process(¶0033, bonding of 2b to 2c) for the second semiconductor package(2b in cleaning chamber 5, ¶0032-33) after the second plasma treatment process is completed(3, ¶0034).
Suga does not explicitly state the second bonding process(¶0033, bonding of 2b to 2c) is initiated before the first bonding process(¶0033, bonding of 2a to 2c) is completed. However Suga does teach optimizing the flow of a series of operations(¶0049) and shortening the time between the second bonding process(¶0033, bonding of 2b to 2c) and the first bonding process(¶0033, bonding of 2a to 2c) so that the second bonding process(¶0033, bonding of 2b to 2c) is initiated before the first bonding process(¶0033, bonding of 2a to 2c) is completed would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention in order to have efficient cleaning, desirable bonding, efficient and smooth flow of a series of operations while shortening the tact time for a mass production(¶0049).
Regarding claim 24, Suga teaches the method of Claim 21, wherein the second substrate-treatment process(3, ¶0034) on the second packaging substrate(2c in cleaning chamber 5 corresponding to 2b, ¶0032-33) is initiated and completed prior to the second semiconductor package(2b in cleaning chamber 5, ¶0032-33) being transported to a position facing the second packaging substrate(2c in cleaning chamber 5 corresponding to 2b, ¶0032-33), thereby preparing the second packaging substrate(2c in cleaning chamber 5 corresponding to 2b, ¶0032-33) for plasma treatment and subsequent bonding(¶0032-33).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Suga et al. (US 2003/0164394 A1) as cited in the IDS of 9/12/2025 and Yamada et al. (JP S63-293952 A) as applied to claim 1 above, further in view of Kim et al. (US 2020/0075517 A1).
Regarding claim 10, Suga, in view of Yamada, teaches the method of Claim 1, but are not relied on to teach the first semiconductor package(2a in process chamber 6, ¶0032-33) comprises a fan-out package including one a semiconductor chip and an interposer.
Kim teaches a method of making a forming a bonded assembly(Fig. 5) wherein the first semiconductor package(2220, 2301, 2290 ¶0050-51) comprises a fan-out package including one a semiconductor chip(2220, ¶0050) and an interposer(2301, ¶0051). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Yamada so that the first semiconductor package comprises a fan-out package including one a semiconductor chip and an interposer, as taught by Kim, in order to decrease the difficulty in directly mounting the fan-in semiconductor package on a mainboard(¶0051).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Suga et al. (US 2003/0164394 A1) as cited in the IDS of 9/12/2025 and Yamada et al. (JP S63-293952 A) as applied to claim 1 above, further in view of Ma et al. (US 2024/0339430 A1).
Regarding claim 25, Suga, in view of Yamada, teaches the method of Claim 21, but are not relied on to teach the first bonding process(¶0033, bonding of 2a to 2c) is a thermocompression bonding process; and
the first semiconductor package(2a in process chamber 6, ¶0032-33) and the first packaging substrate(2c in process chamber 6 corresponding to 2a, ¶0032-33) are not in contact with any flux material during the thermocompression bonding process.
Ma teaches a method of forming a plurality of bonded assemblies(Figs. 1-2) wherein the first bonding process(205, ¶0049) is a thermocompression bonding process(¶0042); and the first semiconductor package(200, ¶0042) and the first packaging substrate(300, ¶0042) are not in contact with any flux material(¶0001, ¶0005) during the thermocompression bonding process(¶0042). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Suga, so that the first bonding process is a thermocompression bonding process; and the first semiconductor package and the first packaging substrate are not in contact with any flux material during the thermocompression bonding process, as taught by Ma, in order to remove impurities, such as organic containments and metal oxides, on the first semiconductor package and the first packaging substrate(¶0001) and to ensure good contact between the die and the substrate during bonding(¶0002).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Inoue et al. (JP 2004154898 A) Teaches a method of forming a bonded assembly.
Yamauchi (US 2004/0169020 A1) Teaches a method of forming a bonded assembly.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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/LAURA M DYKES/Examiner, Art Unit 2892