DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-8, 10-11, 13, 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al (US 2022/0068668) in view of Wang et al (US 2003/02219987).
With respect to Claim 1, Suzuki et al discloses a method of forming a bonded assembly (Figures 1-2), the method comprising: providing a substrate (Figure 1, 2) and a semiconductor chip (Figure 1, 3); disposing the semiconductor chip on the substrate (Figure 1); performing a plasma treatment process (Figure 13) on a surface of a chip bonding pad (Figure 1, 3c) on the semiconductor chip in the low-oxygen ambient (paragraph 91, 0.5%) by directing a plasma jet (Figure 13) to the chip bonding pad (Figure 2, S4); and attaching a bonding wire to the semiconductor chip and to the substrate (Figure 2, S5) such that a first end of the bonding wire is attached to the surface and a second end of the bonding wire is attached to a substrate bonding pad on the substrate (Figure 13). See Figures 1-2 and 13, and corresponding text, especially paragraphs 34-47 and 60-75.
Suzuki et al differs from the Claims at hand in that Suzuki does not disclose that the chip bonding pad comprises a “a copper-containing surface”.
Wang et al is relied upon to disclose the use of copper as a chip bonding pad material. See paragraph 8 of Wang et al.
It would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to use copper as the material of the chip bonding pad in the method of Suzuki et al, for its known benefit in the art in forming chip bonding pads as disclosed by Suzuki et al. The use of a known material, copper, for its known benefit, forming chip bonding pads would have been prima facie obvious to one of ordinary skill in the art.
With respect to Claim 2, the combined references make obvious the limitation “ the chip bonding pad comprises an electroplated copper material containing copper atoms at an atomic percentage in a range from 95 % to 99.9999% and the copper-containing surface is a surface of the electroplated copper material”. See paragraph 8 of Wang et al.
With respect to Claim 4, Suzuki et al disclose wherein the plasma jet (Figure 103g) is generated by a plasma treatment system having a plasma nozzle (Figure 13, 103a) that is directed toward the chip bonding pad. See Figure 13 and corresponding text, especially paragraphs 82-93 of Suzuki et al.
With respect to Claim 5, the combined references make obvious the limitation as Suzuki et al disclose wherein the plasma nozzle (Figure 14, 103a) is directed at the copper-containing surface (Wang et al, paragraph 8) along a downward non-horizontal (Figure 14 of Suzuki et al, upside down) direction while the copper containing surface is oriented along a horizontal direction during the plasma treatment process. See Figure 14 and corresponding text, especially paragraphs 82-93 of Suzuki et al.
With respect to Claim 6, and the limitation “wherein the plasma nozzle is laterally offset from an edge of a bonding capillary by a lateral offset distance greater than 1mm while attaching the bonding wire to the substrate; and the plasma nozzle is vertically offset from a horizontal plane including a top surface of the substrate by a vertical offset distance greater than 0.1 mm while attaching the bonding wire to the substrate”, it would have been obvious for one of ordinary skill in the art to arrive at the limitation, as rearrangement of parts in order to optimize a process, is prima facie obvious in the absence of unobvious results. See In re Japikse, 86 USPQ 70 (CCPA 1950).
With respect to Claim 7, Suzuki et al discloses wherein the bonding wire is bonded to the semiconductor chip and to the substrate during the plasma treatment process. See Figure 13 and corresponding text, especially paragraphs 82-93 of Suzuki et al.
With respect to Claim 8, Suzuki et al discloses wherein the plasma jet cleans an exposed surface of the substrate bonding pad during the plasma treatment process. See Figure 13 and corresponding text, especially paragraphs 82-93 of Suzuki et al.
With respect to Claim 10, Suzuki et al disclose wherein the substrate is one of a packaging substrate, a leadframe, and a wafer including a two-dimensional array of semiconductor dies. See paragraph 2 of Suzuki et al.
With respect to Claim 11, Suzuki et al discloses the use of a layer stack of multiple metal layers containing a gold layer as a topmost layer to form bonding pads. See paragraph 43 of Suzuki et al. It would have been obvious for one of ordinary skill in the art, before the effective date of the invention to use a layer stack of multiple metal layers containing a gold layer as a topmost layer, for its known benefit in the art to form bonding pads.
With respect to Claim 13, Claim 13 is rejected for the reasons as discussed with respect to Claim 1. Moreover, Suzuki et al discloses wherein the plasma treatment process is performed in a low-oxygen (paragraph 91 of Suzuki et al) ambient having an oxygen partial pressure that is lower than 17 kPa (paragraph 63 of Suzuki et al); the low-oxygen ambient is provided in a process chamber having a chamber enclosure (Figure 5 and corresponding text of Suzuki et al) ; and the substrate and the semiconductor chip are located within the chamber enclosure during the plasma treatment process and during attachment of the bonding wire to the semiconductor chip and to the substrate (Figure 2, S3, S4 and S5, and corresponding text).
With respect to Claim 14, Claim 14 is rejected for the reasons as discussed above with respect to Claims 1, 2, 4 and 13. Moreover, Suzuki et al discloses performing a plasma treatment process in the low-oxygen ambient by directing a plasma jet to a first chip bonding pad selected from the chip bonding pads (Figure 9 of Suzuki et al) ; bonding a first end of a bonding wire to the first chip bonding pad; and bonding a second end of the bonding wire to a substrate bonding pad on the substrate (Figures 5-6 and corresponding text of Suzuki et al).
With respect to Claim 16, and the limitation “wherein the first end of the bonding wire is bonded to the first chip bonding pad during the plasma treatment process”, would have been obvious to one of ordinary skill in the art, before the effective date of the invention, as transposition of process steps or performing process steps simultaneously would have been prima facie obvious in the absence of unobvious results. See Ex parte Rubin, 128 USPQ 440 (Bd. App. 1959).
Claims 3, 15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al (US 2022/0068668) in view of Wang et al (US 2003/02219987 as applied to claims 1-2, 4-8, 10-11, 13- 14 and 16 above, and further in view of Lee et al (2019/0157237).
Suzuki et al and Wang et al are relied upon as discussed above .
However, neither reference discloses “the bonding wire is attached to the copper-containing surface through a metal ball having a same material composition as the bonding wire; and the bonding wire is attached to the substrate bonding pad through a stich having the same material composition as the bonding wire”.
Lee et al discloses a wire-bonding method for connecting a die and a substrate which uses a ball and stitch, wherein “the bonding wire is attached to the copper-containing surface through a metal ball having a same material composition as the bonding wire; and the bonding wire is attached to the substrate bonding pad through a stich having the same material composition as the bonding wire”. See Figures 1 A and 4A-4B. and corresponding text, especially paragraphs 38-39, wherein the ball, stitch and wire are copper.
With respect to Claims 3 and 15 , it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to use a bonding wire attachment method which uses a ball and stitch in the process of Suzuki et al and Wang et al, for its known benefit of attaching a bonding wire as disclosed by Lee et al. The use of a known method, for its known benefit, attaching a bonding wire would have been prima facie obvious to one of ordinary skill in the art.
Claim 18 is rejected is rejected for the reasons as discussed above with respect to Claim 14.
Suzuki et al and Wang et al are relied upon as discussed above.
However, neither Suzuki et al nor Wang et al disclose “ attaching a first end of a bonding wire to the copper-containing surface of the chip bonding pad through a metal ball having a same material composition as the bonding wire; and attaching a second end of the bonding wire to a substrate bonding pad of the substrate through a stitch”.
Lee et al discloses a wire-bonding method for connecting a die and a substrate which uses a ball and stitch, to connect one end of a wire to a bonding pad. See Figures 1 A and 4A-4B, and corresponding text, especially paragraphs 38-39, wherein the ball, stitch and wire are copper.
With respect to Claim 18, it would have been obvious to one of ordinary skill in the art, before the effective date of the invention, to use a bonding wire attachment method which uses a ball and stitch in the process of Suzuki et al and Wang et al, to attach each end of the wire to a bonding pad as disclosed by Suzuki et al and Wang et al, for its known benefit of obtaining a wire bond with improved adhesion. See paragraph 5 of Lee et al.
With respect to Claim 19, the combined references make obvious the limitation “ the chip bonding pad comprises an electroplated copper material containing copper atoms at an atomic percentage in a range from 95 % to 99.9999% and the copper-containing surface is a surface of the electroplated copper material”. See paragraph 8 of Wang et al.
With respect to Claim 20, and the limitation “wherein the first end of the bonding wire is attached to the copper-containing surface of the chip bonding pad during the plasma treatment process; and the second end of the bonding wire is attached to the substrate bonding pad during the plasma treatment process ”, would have been obvious to one of ordinary skill in the art, before the effective date of the invention, as transposition of process steps or performing process steps simultaneously would have been prima facie obvious in the absence of unobvious results. See Ex parte Rubin, 128 USPQ 440 (Bd. App. 1959). See Figure 2 of Suzuki et al and corresponding text.
Claims 9, 12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al (US 2022/0068668) in view of Wang et al (US 2003/02219987) as applied to claims 1-2, 4-8, 10-11, 13- 14 and 16 above, and further in view of Chen et al (2015/0270232).
Suzuki et al and Wang et al are relied upon as discussed above .
However, neither Suzuki et al or Wang et al disclose the semiconductor chip comprises a composite chip including an assembly of at least one semiconductor die and an interposer including redistribution metal interconnects embedded in redistribution dielectric layers; and the chip bonding pad is located on the redistribution dielectric layers, or truncating the wires.
Chen et al is relied upon to disclose a composite chip including an assembly of at least one semiconductor die (Figure 3D) and an interposer (paragraph 10) including redistribution metal interconnects (Figure 3D, 408) embedded in redistribution dielectric layers (Figure 3D, 110) ; and the chip bonding pad (Figure 3D, 404)is located on the redistribution dielectric layers. See Figure 3D and corresponding text, especially paragraphs 40-48.
With respect to Claims 9 and 17, it would have been obvious for one of ordinary skill in the art, before the effective date of the invention, to use the method of Suzuki et al and Wang et al, to form the package of Chen et al, for its known benefit in the art of attaching bonding wires to a substrate to form a package.
With respect to Claim 12, Claim 12 is rejected for the reasons as discussed in Claim 1. Moreover, Suzuki et al discloses the bonding wire is attached to the semiconductor chip and to the substrate by: attaching a first end of an in-process bonding wire to the copper-containing surface of the chip bonding pad; attaching a portion of the in-process bonding wire to a surface of the substrate bonding pad. See Figure 6 and corresponding text of Suzuki et al.
However, Suzuki et al and Wang et al do not disclose “ truncating the in-process bonding wire such that a remaining portion of the in-process bonding wire constitutes the bonding wire that extends between the copper-containing surface and the surface of the substrate bonding pad”.
Chen et al pertains to the same field and discloses truncating the excess wire after attaching the substrate and the die. See paragraphs 15 and 17.
It would have been obvious for one of ordinary skill in the art, before the effective date of the invention, to truncate the wire in the process of Suzuki et al and Wang et al, for its known benefit of removing the excess wire after the substrate and die have been connected by the wire as disclosed by Chen et al. The use of a known process, cutting excess wire, for its known benefit, would have been prima facie obvious to one of ordinary skill in the art.
Conclusion
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AGG
April 9, 2026
/ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812
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