DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Prior Art Rejections, filed 12/23/2025, with respect to the rejections of claims 11 and 18 been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kang, Byung Hu et al. (Pub No. US 20230361036 A1) (hereinafter, Kang) in view of Lee, Kyenhee et al. (Pub No. US 20240387552 A1) (hereinafter, Lee).
6. Applicant’s arguments, see Prior Art Rejections, filed 12/23/2025, with respect to claim 1 have been fully considered and are persuasive. The rejection of claim 1 has been withdrawn.
7. Applicant’s arguments, see Drawings, filed 12/23/2025, with respect to the objection of the Drawings have been fully considered and are persuasive. The objection of the Drawings has been withdrawn.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 11-14 and 18-21 are rejected under 35 U.S.C. 103 as being unpatentable Kang, Byung Hu et al. (Pub No. US 20230361036 A1) (hereinafter, Kang), and further in view of Lee, Kyenhee et al. (Pub No. US 20240387552 A1) (hereinafter, Lee).
Kang, Fig 13, Embodiment of a cross-section in ZY-plane of semiconductor device
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Re Claim 11, (Currently Amended) Kang teaches a structure comprising:
a plurality of gate-replacing structures (Dummy gate electrode/cell separation pattern/Gate Electrodes; DGE/DB2/DB3/DB4/GE; Figs 13/20; ¶[0132]) having equal lengths and a uniform pitch (Per figure 13 DGE and DB have uniform pitch and length), (See Fig 20 below)
Kang, Fig 20, Embodiment of a cross-section in ZX-plane of semiconductor device
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wherein the plurality of gate-replacing structures are selected from the group consisting of dielectric isolation regions, dummy replacement gate stacks, active replacement gate stacks and combinations thereof (Combination of dummy gate electrode/cell separation pattern; DGE/DB2/DB3/DB4; Fig 13; ¶[0132]) ;
a deep contact plug (Power through vias; PTSV2; Fig 2; ¶[0030]) between two neighboring ones (Between DB/DGE; Fig 13) of the plurality of gate-replacing structures;
a CFET device (Logic cell comprising of PMOSFET and NMOSFET; LC; Figs 1/4; ¶[0027]; Note: Fig 4 is a cross section in ZY-plane of logic cell LC), wherein the deep contact plug extends from a top surface level (Bottom surface of metal layer M1; Fig 4; ¶[0034]) of to a bottom surface level (Bottom of substrate 100; Fig 4) of the CFET device; (See Fig 2 below)
Kang, Fig 2, Embodiment of semiconductor device with power tap cell and power through vias
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a front-side via (Power rails and/or upper via; PR1/PR2/V1; Fig 4; ¶[0025]) over the deep contact plug and higher than the CFET device (Power rails PR and upper via V1 extend higher than CFET device to top surface of metal layer M1; Fig 4) ; and
a back-side via (Lower via; LV; Fig 4; ¶[0076]) under the deep contact plug and lower than the CFET device, wherein the front-side via is electrically connected (Deep contact plug PTSV1/PTSV2 extends from backside to frontside; Fig 4) to the back-side via through the deep contact plug. (See Fig 4 below)
Kang, Fig 4, Embodiment of semiconductor device with backside and frontside vias
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However, Kang does not teach wherein the CFET device comprises:
a first transistor of a first conductivity type; and
a second transistor of a second conductivity type opposite to the first conductivity type, wherein the second transistor overlaps the first transistor;
In the same field of endeavor, Lee teaches wherein the CFET device (Fig 3) comprises:
a first transistor (First transistor; P1; Fig 3; ¶[0034]) of a first conductivity type (P-type conductivity; ¶[0035]); and
a second transistor (Second transistor; N1; Fig 3; ¶[0034]) of a second conductivity type (N-type conductivity; ¶[0035]) opposite to the first conductivity type, wherein the second transistor overlaps (P1/P2 overlaps N1/N2 overlap; Fig 3) the first transistor.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a CFET device comprising a first transistor of a first conductivity type and a second transistor of a second conductivity type opposite to the first conductivity type, wherein the second transistor overlaps the first transistor, as taught by Lee for the CFET structure as taught by Kang. One would have been motivated to do this with a reasonable expectation of success in order to modify the n-type and p-type transistors from a horizontal arrangement to the vertical arrangement and therefore maximize transistor density enhance drive current through increased total effective channel width, and improve electrostatic control over the channel.
Re Claim 12, (Original) Kang teaches the structure of claim 11, wherein in a top view of the structure, the deep contact plug (Power through vias; PTSV1; Fig 20; ¶[0030]) is elongated, with a first lengthwise direction (Z-direction length of PTSV1; Fig 20) of the deep contact plug being parallel to second lengthwise directions (Z-direction length of DGE; Fig 20) of the plurality of gate-replacing structures (Dummy gate electrode/cell separation pattern/Gate Electrodes; DGE/DB2/DB3/DB4; Figs 13/20; ¶[0132]) .
Re Claim 13, (Original) Kang teaches the structure of claim 11, wherein the plurality of gate-replacing structures (Dummy gate electrode/cell separation pattern; DGE/DB2/DB3/DB4; Fig 13; ¶[0132]) comprise a dummy gate stack (Dummy gate electrode; DGE; Fig 13; ¶[0132]; Per ¶[0047] dummy gate electrodes may be formed through a replacement process) and a dielectric region (Cell separation pattern; DB2/DB3/DB4; Fig 13; ¶[0132]),
and wherein the deep contact plug (Power through vias; PTSV1; Fig 13; ¶[0030]) is between the dielectric region and the dummy gate stack,
and wherein in a top view (ZY-plane; Fig 13) of the structure, the dummy gate stack and the dielectric region have a same length (DGE is same length of DB; Fig 13).
Re Claim 14, (Original) Kang teaches the structure of claim 11, wherein the plurality of gate-replacing structures (Dummy gate electrode/cell separation pattern; DGE/DB2/DB3/DB4; Fig 13; ¶[0132]) comprise:
the dummy replacement gate stacks (Dummy gate electrode; DGE; Fig 13; ¶[0132]; Per ¶[0047] dummy gate electrodes may be formed through a replacement process); and
the dielectric isolation regions (Cell separation pattern; DB2/DB3/DB4; Fig 13; ¶[0132]), wherein the dielectric isolation regions have equal widths (Equal in pitch/width per Fig 13) as the dummy replacement gate stacks.
Re Claim 18, (Currently Amended) Kang teaches a structure comprising:
a power tap cell (Power tap cell; PTC; Fig 2; ¶[0029]) comprising:
a first power line (Power rail; PR1; Fig 8; ¶[0025]) having a first lengthwise direction (Y-direction length; Fig 8);
a plurality of gate-replacing structures (Dummy gate electrode/cell separation pattern/Gate Electrodes; DGE/DB2/DB3/DB4/GE; Figs 13/20; ¶[0132]) having second lengthwise directions (Z-direction length; Fig 13) perpendicular to the first lengthwise direction,
wherein the plurality of gate-replacing structures are selected from the group consisting of dielectric isolation regions, dummy replacement gate stacks, and combinations thereof (Combination of dummy gate electrode/cell separation pattern; DGE/DB2/DB3/DB4; Fig 13; ¶[0132]), and wherein the plurality of gate-replacing structures have a uniform pitch (Uniform pitch in Y-direction; Fig 13);
a plurality of deep contact plugs (Power through vias; PTSV1/PTSV2; Fig 2; ¶[0030]), each being between two neighboring ones (Between DB/DGE; Fig 13) of the plurality of gate-replacing structures, wherein the plurality of deep contact plugs have third lengthwise directions (Z-direction length; Fig 13) parallel to the second lengthwise directions; and
a second power line (Power rail; PR2; Fig 8; ¶[0025]) having the first lengthwise direction, wherein the first power line is electrically connected (Logic cell defined by first and second power rails, as well as power through vias; ¶¶[0026, 0030])to the second power line through the plurality of deep contact plugs.
However, Kang does not teach a plurality of CFET devices, wherein the plurality of deep contact plugs extend at least from top surface levels to bottom surface levels of the plurality of CFET devices, and wherein each of the plurality of CFET devices comprises:
a first transistor of a first conductivity type; and
a second transistor of a second conductivity type opposite to the first conductivity type, wherein the second transistor overlaps the first transistor.
However, Lee teaches a plurality of CFET devices (P-type and N-type transistors; P1/P2/N1/N2; Fig 3; ¶[0034]; Note: CFET devices also includes source/drain regions 150A1-150A4), wherein the plurality of deep contact plugs (Contact vias; 180b/190b/190c; Fig 5A; ¶[0034]) extend at least from top surface levels to bottom surface levels (Top levels up 150A1 to 150A4; Fig 5A) of the plurality of CFET devices, and wherein each of the plurality of CFET devices comprises:
a first transistor (First transistor; P1; Fig 3; ¶[0034]) of a first conductivity type (P-type conductivity; ¶[0035]); and
a second transistor (Second transistor; N1; Fig 3; ¶[0034]) of a second conductivity type (N-type conductivity; ¶[0035]) opposite to the first conductivity type, wherein the second transistor overlaps (P1/P2 overlaps N1/N2 overlap; Fig 3) the first transistor.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a plurality of CFET devices, wherein the plurality of deep contact plugs extend at least from top surface levels to bottom surface levels of the plurality of CFET devices, and wherein each of the plurality of CFET devices comprises: a first transistor of a first conductivity type; and a second transistor of a second conductivity type opposite to the first conductivity type, wherein the second transistor overlaps the first transistor, as taught by Lee for the CFET structure as taught by Kang. One would have been motivated to do this with a reasonable expectation of success in order to modify the n-type and p-type transistors from a horizontal arrangement to the vertical arrangement and therefore maximize transistor density enhance drive current through increased total effective channel width, and improve electrostatic control over the channel. Furthermore, the vertical arrangements of the transistors requires contact plugs which extend from the bottom to top surfaces of the transistors within the CFET structure.
Re Claim 20, (Currently Amended) Kang teaches the structure of claim 19, wherein the plurality of CFET devices (Logic cells comprising of PMOSFET and NMOSFET; LC; Figs 1/4/13; ¶[0027]; Note: Fig 4 is a cross section in ZY-plane of logic cell LC) comprise a plurality of replacement gate stacks (Dummy gate electrode/cell separation pattern/Gate Electrodes; DGE/DB2/DB3/DB4/GE; Figs 13/20; ¶[0132]),
and wherein the plurality of gate-replacing structures and the plurality of replacement gate stacks (Gate electrodes; GE; Figs 13/20; ¶[0045]) are aligned to straight lines that have the uniform pitch (Per ¶[0045] dummy gate electrodes and gate electrodes have a substantially equal pitch).
Re Claim 21, (New) Kang does not teach the structure of claim 11, wherein the first transistor and the second transistor are aligned to a straight line, wherein the structure further comprises a plurality of dielectric layers, and wherein interfaces between neighboring ones of the plurality of dielectric layers are perpendicular to the straight line.
In the same field of endeavor, Lee teaches the structure of claim 11, wherein the first transistor (First transistor; P1; Fig 3; ¶[0034]) and the second transistor (Second transistor; N1; Fig 3; ¶[0034]) are aligned to a straight line (Straight line in y-direction; Fig 3),
wherein the structure further comprises a plurality of dielectric layers (Spacers; 146B; Fig 3; ¶[0044]), and wherein interfaces (Interfaces between spacers 146B and transistors P1/N1 are along x-direction; Fig 3) between neighboring ones of the plurality of dielectric layers are perpendicular to the straight line.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the first transistor and the second transistor aligned to a straight line, wherein the structure further comprises a plurality of dielectric layers, and wherein interfaces between neighboring ones of the plurality of dielectric layers are perpendicular to the straight line, as taught by Lee for the CFET structure as taught by Kang. One would have been motivated to do this with a reasonable expectation of success in order to provide high density wiring by stacking the transistors vertically. Further, the dielectric spacers are perpendicular to the vertical direction in order to isolate electrical current between the channel and source/drain regions.
10. Claims 15-16 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kang, Byung Hu et al. (Pub No. US 20230361036 A1) (hereinafter, Kang) in view of Lee, Kyenhee et al. (Pub No. US 20240387552 A1) (hereinafter, Lee) as applied to claims 11 and 18 above, and further in view of Yu, Li-Zhen et al. (Pub No. US 20210408274 A1) (hereinafter, Yu).
Yu, Fig 14, Cross-section showing interlayer dielectric, gate spacers, and isolation layers
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Re Claim 15, (Original) Kang in view of Lee does not teach the structure of claim 11 further comprising a pair of gate spacers contacting opposing sidewalls of one of the dielectric isolation regions.
In the same field of endeavor, Yu teaches the structure of claim 11 further comprising a pair of gate spacers (Dielectric gate spacers; 38; Fig 14; ¶[0129]) contacting opposing sidewalls of one of the dielectric isolation regions (Isolation structures; 46/48; Fig 14; ¶[0129]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a pair of gate spacers contacting opposing sidewalls of one of the dielectric isolation regions, as taught by Yu for the CFET structure as taught by Kang in view of Lee. One would have been motivated to do this with a reasonable expectation of success because positioning the gate spacers to be adjacent to the dielectric isolation regions allows the gate electrodes to be electrically isolated while optimizing integratinon density by maintaining a semiconductor structure of the nanoscale dimension, i.e. greater than 1 nm and less than 1 micron, as suggested by Yu (¶[0131]).
Re Claim 16, (Original) Kang in view of Lee does not teach the structure of claim 15 further comprising an inter-layer dielectric over and in contact with the pair of gate spacers and the dielectric isolation regions.
In the same field of endeavor, Yu teaches the structure of claim 15 further comprising an inter-layer dielectric (Planarization dielectric layer; 70; Fig 14; ¶[0130]) over and in contact with the pair of gate spacers (Dielectric gate spacers; 38; Fig 14; ¶[0129]) and the dielectric isolation regions (Isolation structures; 46/48; Fig 14; ¶[0129]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used an inter-layer dielectric over and in contact with the pair of gate spacers and the dielectric isolation regions, as taught by Yu for the CFET structure as taught by Kang in view of Lee. One would have been motivated to do this with a reasonable expectation of success in order to fill in the opening above the gate spacers and dielectric isolation regions with a planarization layer, such that recess cavities may be formed through the planarization layer to connect to the active regions of the transistor structure, as suggested by Yu (¶¶[0133-0134]).
Yu, Fig 28C: Deep contact plugs with overlapping frontside and backside vias
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Re Claim 22, (New) Kang in view of Lee does not teach the structure of claim 18, further comprising:
a front-side via overlapping and contacting one of the plurality of deep contact plugs;
and a backside via overlapped by, and contacting, the one of the plurality of deep contact plugs.
In the same field of endeavor, Yu teaches the structure of claim 18, further comprising:
a front-side via (Connector-side contact via structure; 88; Fig 28C; ¶[0143]) overlapping and contacting one of the plurality of deep contact plugs (One of the plurality of conductor via structures; 180; Fig 28C; ¶[0139]);
and a backside via (Backside vias; 120; Fig 28C; ¶[0150]) overlapped by, and contacting, the one of the plurality of deep contact plugs.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a front-side via overlapping and contacting one of the plurality of deep contact plugs and a backside via overlapped by, and contacting, the one of the plurality of deep contact plugs, as taught by Yu for the CFET structure as taught by Kang in view of Lee. One would have been motivated to do this with a reasonable expectation of success in order to provide high density wiring and facilitate packaging (Yu; ¶[0001]).
Allowable Subject Matter
11. Claims 1-10 are allowed.
12. Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 1, the closest prior art Lee, Kyenhee et al. (Pub No. US 20240387552 A1) (hereinafter, Lee) and Lin, Zhi-Chang et al. (Pub No. US 20210134797 A1) (hereinafter, Lin) either singularly or in combination fails to anticipate or render obvious
“A method comprising:
forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly;
forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi- layer stack, wherein two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between;
forming a first source/drain region and a second source/drain region in the multi-layer stack, wherein the second source/drain region overlaps the first source/drain region;
replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks;
replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region;
replacing a second one of the plurality of replacement gate stacks with a second dielectric isolation region:
forming a deep contact plug in the space, wherein the deep contact plug is between, and immediately neighboring, the first dielectric isolation region and the second dielectric isolation region;
forming a front-side via over the deep contact plug; and
forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, Lee in view of Lin anticipates all of the limitations except "replacing a second one of the plurality of replacement gate stacks with a second dielectric isolation region." Although prior art discloses a deep contact plug between a first and second dielectric isolation region, the second dielectric isolation was not found to replace a replacement gate stack.
Regarding claim 17, the closest prior art Kang, Byung Hu et al. (Pub No. US 20230361036 A1) (hereinafter, Kang), Cheng, Kangguo et al. (Pub No. US 20230187551 A1) (hereinafter, Cheng), and Yu, Li-Zhen et al. (Pub No. US 20210408274 A1) (hereinafter, Yu) either singularly or in combination fails to anticipate or render obvious:
“The structure of claim 11 further comprising:
a first source/drain region and a second source/drain region overlapping the first source/drain region;
an additional deep contact plug extending through the second source/drain region, wherein the additional deep contact plug electrically connects the second source/drain region to the first source/drain region;
an additional front-side via over the second source/drain region; and
an additional back-side via under the first source/drain region, wherein the additional front-side via is electrically connected to the additional back-side via through the additional deep contact plug and the first source/drain region,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, referring to Fig 1 of Cheng, Cheng anticipates all of the limitations except "wherein the additional front-side via is electrically connected to the additional back-side via through the additional deep contact plug and the first source/drain region." While Yu teaches a deep contact plug connecting a front-side and back-side via, it does not connect to a source/drain region. Given that Yu teaches away from the claimed invention, it is not rendered obvious to combine the reference of Yu with Kang in view of Cheng.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Jo, Gun Ho et al. (Pub No. KR 20240124740 A) discloses a FinFET structure comprising of source/drain regions surrounded by channel regions, wherein the FinFET structure comprises of contact plugs connected to backside and frontside vias.
[2] Peng, Shih-Wei (Pub No. US 20220123023 A1) discloses a CFET device comprising of vertically stacked channel layers and source/drain regions, comprising of deep contact plugs connected to source/drain regions and backside and frontside vias.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
/T.E.D./
Examiner
Art Unit 2817