DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/11/2026 has been entered.
Response to Amendment
The present amendment, filed on or after 5/28/2026, has been entered. The Applicant has amended claim 16. Claims 9-11 were canceled previously. Accordingly, claims 1-8, 12-23 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 16-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jhan (US 2021/0257480 A1) in view of Peng (US 2021/0225692 A1).
Regarding claim 16, Jhan teaches a semiconductor device (semiconductor device 200, Figs. 13A-D, [0015]) comprising:
a first plurality of fins (substrate portions/semiconductor fins 203, labeled as fins in Illustrative Fig. 1, which is an annotated versions of Figs. 13A-B, [0041]) extending from a substrate (substrate 202, Illustrative Fig. 1, [0014]);
a shallow trench isolation (STI) layer (STI features 220, Illustrative Fig. 1, [0041]) between adjacent fins (fins, Illustrative Fig. 1) of the first plurality of fins (fins, Illustrative Fig. 1);
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an insulating fin (dielectric fins 228, Illustrative Fig. 1, [0040]) between the adjacent fins (fins, Illustrative Fig. 1) of the first plurality of fins (fins, Illustrative Fig. 1) and over the STI layer (STI features 220, Illustrative Fig. 1), wherein the insulating fin (dielectric fins 228, Illustrative Fig. 1) comprises a nitride liner (dielectric layer 224, Illustrative Fig. 1, [0031]: “the dielectric layers 224 … may include SiN, .…”), a fill material (dielectric layer 226, Illustrative Fig. 1) over the nitride liner (dielectric layer 224, Illustrative Fig. 1), and a capping layer (high-K dielectric layer 230, Illustrative Fig. 1) on the nitride liner (dielectric layer 224, Illustrative Fig. 1), and the fill material (dielectric layer 226, Illustrative Fig. 1), wherein the nitride liner (dielectric layer 224, Illustrative Fig. 1) comprises silicon nitride ([0031]: “the dielectric layers 226 … may include… SOx”), the fill material comprises (dielectric layer 226, Illustrative Fig. 1) an oxide ([0031]: ”… the second dielectric layer 222, which may be formed of silicon oxide”), and the capping layer (high-K dielectric layer 230, Illustrative Fig. 1) comprises hafnium oxide ([0025]: “the high-K dielectric layer 230 may include HfO2, …”), zirconium oxide, zirconium aluminum oxide, hafnium aluminum oxide, hafnium silicon oxide, or aluminum oxide, wherein topmost surfaces (topmost surface of fins, Illustrative Fig. 1) of the first plurality of fins (fins, Illustrative Fig. 1) are disposed above a topmost surface (topmost surface of STI, Illustrative Fig. 1) of the STI layer (STI features 220, Illustrative Fig. 1), and wherein the topmost surfaces of the first plurality of fins (topmost surface of fins, Illustrative Fig. 1) are disposed above a bottommost surface (bottommost surface of insulating fin, Illustrative Fig. 1) of the insulating fin (dielectric fins 228, Illustrative Fig. 1); and
a gate structure (a high-K dielectric layer (HK) and metal gate electrode (MG) stack 264, Illustrative Fig. 1, [0048]) over the adjacent fins (fins, Illustrative Fig. 1) of the first plurality of fins (Illustrative Fig. 1) and the STI layer (STI features 220, Illustrative Fig. 1); and
a source/ drain region (S/D features, Illustrative Fig. 1, [0048]) in each of the adjacent fins (fins, Illustrative Fig. 1) of the first plurality of fins (fins, Illustrative Fig. 1), each source/drain region (S/D features, Illustrative Fig. 1) being adjacent to the gate structure (see Fig. 13A of Illustrative Fig. 1: adjacent in Y direction).
Jhan, however, does not teach that
an atomic percentage concentration of carbon of the STI layer is in a range from 0.5 percent to 4 percent.
Peng, on the other hand teaches a finFET device (semiconductor device, Figs. 8A-B, [0015]) comprising a first plurality of fins (fins 22, Fig. 8A, [0016]) extending from a substrate (semiconductor substrate 20, Fig. 8A, [0016]), and a shallow trench isolation (STI) layer (converted dielectric material 26 and fill dielectric material 28, Fig. 8B, [0041]) between adjacent fins (fins 22, Figs. 6 and 8B) of the first plurality of fins (fins 22, Figs. 6 and 8B), wherein
an atomic percentage concentration of carbon of the STI layer (fill dielectric material 28, Fig. 8B) is in a range from 0 percent to 20 percent ([0042]: fill dielectric material is silicon oxycarbide nitride (SiOxCyNz) and “carbon at a concentration in a range about 0 at. % to 20 at. %”).
Peng further discloses that varying the concentration of carbon in silicon oxycarbide nitride (SiOxCyNz) can vary the k-value, such as increasing the concentration of carbon can result in a lower k-value, and decreasing the concentration of carbon can result in a higher k-value ([0037]), and also control the wet etch rate (carbon concentration affects the wet etch rate, [0037] and [0042]). It is known in the field of semiconductor devices that isolation regions with lower k-value materials provide the benefit of reduced parasitic capacitance in semiconductor devices as evidenced by Gabriel (US 6,475,929 B1, col. 3, lines 8-30). Peng further discloses that including two layers in the STI layer facilitates reliable filing larger gaps between fins ([0038]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention, who is aiming to reduce the parasitic capacitance between fins in a semiconductor device or setting the etch rate of the STI layer to help manufacturing the device, would realize that the material of the STI layer (STI features 220, Illustrative Fig. 1) of Jhan is silicon oxynitride ([0028]) and the STI layer of Peng is also silicon oxynitride with added carbon, and therefore, would be motivated to modify the semiconductor device of Jhan such that the STI layer is composed of two layers of silicon oxycarbide nitride, as taught by Peng, which will provide the benefit reducing the k-value and etch rate of the STI layer, and facilitating filling the gaps between fins reliably. Regarding the concentration of carbon in the STI layer, the range of concentration values provided Peng covers the range of concentration values disclosed in the claimed invention (0.5-4%), and therefore, a prima facie case of obviousness exists (see MPEP 2144.05(I)), as the concentration of the carbon in the STI layer can be optimized by routine experimentation to achieve desired k-value and etch rate for the STI layer, as disclosed by Peng ([0042]). Thus, the range of values provided does not hold an inventive subject matter, and the combination of Jhan and Peng meets all the limitations of claim 16.
Regarding claim 17, Jhan in view of Peng teaches the semiconductor device of claim 16, wherein
the combination of Jhan and Peng (the semiconductor device where the STI layer 280 (Illustrative Fig. 1) of Khan is replaced by the STI layer of Peng (Fig. 8B), i.e. by replacing STI features 220 of Jhan (Illustrative Fig. 1) with converted dielectric material 26 and fill dielectric material 28 of Peng (Fig. 8B)) further teaches that STI layer further (converted dielectric material 26 and fill dielectric material 28, Fig. 8B of Peng) comprises:jjj
a first dielectric liner (converted dielectric material 26, Fig. 8B of Peng); and
a first dielectric layer (fill dielectric material 28, Fig. 8B of Peng) over the first dielectric liner (converted dielectric material 26, Fig. 8B of Peng), wherein the first dielectric liner (converted dielectric material 26, Illustrative Fig. 2) is disposed between the first plurality of fins (fins, Illustrative Fig. 1) and the first dielectric layer (fill dielectric material 28, Fig. 8B of Peng), and between a top surface of the substrate (top surface of substrate 202 between fins, Illustrative Fig. 1) and the first dielectric layer (converted dielectric material 26, Fig. 8B of Peng), wherein the first dielectric liner (converted dielectric material 26, Fig. 8B of Peng) comprises SiOCN (Peng, [0037]: “… the converted dielectric material 26 is silicon oxycarbide nitride (SiOxCyNz) …”).
Regarding claim 19, Jhan in view of Peng teaches the semiconductor device of claim 16 wherein
the combination of Jhan and Peng (the semiconductor device where the STI layer of Jhan is replaced by the STI layer of Peng, see claim 17 rejection above) further teaches that
an atomic percentage concentration of carbon at a first point in the STI layer (in the converted dielectric material 26, Peng’s Fig. 8B, [0037]: “… carbon at a concentration in a range from about 5 at % to about 16 at % …“) is larger than an atomic percentage concentration of carbon at a second point in the STI layer (fill dielectric material 28, Peng’s Fig. 8B, ([0037]: “… carbon at a concentration in a range from about 0 at % to about 20 at % …“): while Peng does not explicitly disclose that the carbon concentration in the converted dielectric material 26 is larger than fill dielectric material 28, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that at a 1% carbon concentration in the fill dielectric material, the converted dielectric material would have a higher carbon concentration), wherein the first point (any point within the converted dielectric material 26 at the bottom of the trench between fins, Peng’s Fig. 8B) is vertically below and overlapped by the second point (any point within the fill dielectric material 28 at the bottom of the trench, Peng’s Fig. 8B).
Regarding claim 20, while Jhan in view of Peng teaches the semiconductor device of claim 16, wherein
Jhan does not explicitly teaches that a ratio between a height of each fin of the first plurality of fins and a thickness of the STI layer is in a range from 15 to 1.2.
Peng, on the other hand teaches a finFET device (semiconductor device, Figs. 8A-B, [0015]) comprising a first plurality of fins (fins 22, Fig. 8A, [0016]) extending from a substrate (semiconductor substrate 20, Fig. 8A, [0016]), and a shallow trench isolation (STI) layer (converted dielectric material 26 and fill dielectric material 28, Fig. 8B, [0041]) between adjacent fins (fins 22, Figs. 6 and 8B) of the first plurality of fins (fins 22, Figs. 6 and 8B), wherein a ratio between a height of each fin (fins 22, Fig. 5A, [0043]) of the first plurality of fins (fins 22, Fig. 5A) and a thickness of the STI layer (converted dielectric material 26 and fill dielectric material 28, Fig. 8B, [0041]) is in a range from 15 to 1.2 (see Fig. 5A indicating that a ratio of about 2.).
FinFET devices wherein the ratio between the height of each fin of the first plurality of fins and the thickness of the STI layer is in a range from 15 to 1.2 are known and common in the field of semiconductor devices, as also evidenced by Lin (US 2019/0103304 A1, Fig. 32: see fins 52 and STI region 204), and there is no criticality of the value of the ratio between the height of each fin of the first plurality of fins and the thickness of the STI layer in the semiconductor device of Jhan in view of Peng. Therefore, a prima facie case of obviousness exists (see MPEP 2143 (I)(E)), because having a ratio between the height of each fin of the first plurality of fins and the thickness of the STI layer is in a range from 15 to 1.2 is another and a known way of implementing the semiconductor device of Jhan in view of Peng without compromising its functionality. Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention would have configured the semiconductor device of Jhan in view of Peng to have the ratio between the height of each fin of the first plurality of fins and the thickness of the STI layer is in a known range from 15 to 1.2 to obtain a finFET device with a reasonable expectation of success (see MPEP 2143 (I)(E)). Thus, the limitation that a ratio between a height of each fin of the first plurality of fins and a thickness of the STI layer is in a range from 15 to 1.2 does not carry an inventive weight.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Jhan (US 2021/0257480 A1) in view of Peng (US 2021/0225692 A1) as applied to claims 16-17 and 19-20 above, and further in view of Lee (US 2019/0287971 A1).
Regarding claim 18, while Jhan in view of Peng teaches the semiconductor device of claim 17,
Neither Jhan nor Peng teaches that the STI layer further comprises:
a second dielectric liner disposed between the first dielectric liner and the first dielectric layer, wherein the second dielectric liner comprises SiOCN, and wherein a carbon concentration of the first dielectric liner and a carbon concentration of the second dielectric liner are different.
Lee, on the other hand, teaches a method (for manufacturing a FinFET device with oxidation-resistant STI liner structure, Fig. 15, [0074]) comprising:
a second dielectric liner (nitrided surface region 332, Fig. 15, [0074]) disposed between the first dielectric liner (liner layer 330, Fig. 15, [0033]) and the first dielectric layer (insulating layer 142, Fig. 6, [0040]), wherein the second dielectric liner (nitrided surface region 332, Fig. 15) comprises SiOCN (nitrided SiOCN when the liner layer is SiOCN, see [0075]), and wherein a carbon concentration of the first dielectric liner (liner layer 330, Fig. 15) and a carbon concentration of the second dielectric liner (nitrided surface region 332: nitride region has a lower carbon concentration due to extra N atoms).
Lee further discloses that a liner layer 330 with a nitrided surface serves as an oxidation-resist layer to prevent fin structures from damage by oxidation during manufacturing ([0077]). Therefore, a person of ordinary skill in the art before the effective filling date of the claimed invention would be motivated to modify the semiconductor device of Jhan in view Peng according to the teachings of Lee to use a first dielectric liner with a nitride surface region as the second dielectric liner to obtain the benefit of protecting the fin structures from oxidation during manufacturing.
Allowable Subject Matter
Claims 1-15 and 21-23 are allowed, where claims 1 and 8 are the independent claims.
Regarding claim 1 and its dependent claims 2-7, the amended independent claim 1, disclosing the limitations that " after performing the anneal process the first dielectric layer has a second thickness that is smaller than the first thickness” is allowed as also stated in the final office action mailed on 4/1/2026. The closest prior art identified for the invention of claim 1 is Lee (US 2019/0287971 A1, Embodiment 1 as shown in Figs. 2-7, [0006]). Accordingly, Lee Embodiment 1 teaches a method (for manufacturing a FinFET device, Figs. 4-7, [0006]) comprising:
etching a first trench (trench 111a, Fig. 4, [0029]) in a semiconductor substrate (semiconductor substrate 100, Fig. 4, [0029]) to form a first fin (the left fin of the first fin structures 110a, Fig. 4, [0029]) and a second fin (the right fin of first fin structures 110a, Fig. 4, [0029]); and
forming a shallow trench isolation (STI) region (region formed by first liner layer 130, second liner layer 132, and isolation features 142a, Fig. 8, [0018]-[0019]) in the first trench (trench 111a, Figs. 4 and 8), wherein forming the STI region (region formed by first liner layer 130, second liner layer 132, and isolation features 142a, Fig. 8) comprises:
depositing a first dielectric layer (first liner layer 130, Fig. 5, [0033]) over top surfaces of the first fin (the left fin of first fin structures 110a, Fig. 5) and the second fin (the right fin of the first fin structures 110a, Fig. 5), and on sidewalls and a bottom surface of the first trench (trench 111a, Fig. 5: first liner layer 130 cover the fin structures 110a and 110b conformally), the first dielectric layer (first liner layer 130, Fig. 5) comprising carbon ([0034]: “silicon carbide (SiC) film, or a carbon-doped silicon oxide (SiOC) films“);
depositing a second dielectric layer (insulating layer 142, Fig. 6, [0040]) over the first dielectric layer (first liner layer 130, Fig. 6), and in the first trench (trench 111a, Fig. 6), wherein the second dielectric layer (insulating layer142, Fig. 6) fills the first trench (trench 111a, Fig. 6); and
performing an anneal process (anneal process 144, Fig. 6, [0041]), wherein the anneal process releases carbon from the first dielectric layer (first liner layer 130) into the second dielectric layer (insulating layer 142, Fig. 6: while Lee Embodiment 1 does not disclose that the anneal process releases carbon from the first dielectric layer into second dielectric layer, Lee Embodiment 1 discloses that the anneal process is performed at a temperature in a range from 150° C to about 950° C, for more than 0.5 hour ([0041]). This anneal process will drive out the carbon from the dielectric layer by diffusion as evidenced by Kao-771 (US 2021/0082771 A1), where annealing dielectric layers 112 ([0027]: SiOCN layer) and 116 ([0048]: SiOCN layer) at about 500° C to about 700°C for more than 0.5 hour ([0053]) would drive the carbon out by diffusion ([0055]). As further evidenced by Gabriel (US 6,475,929 B1), the diffused carbon will be absorbed by the neighboring low-k dielectric layer (col. 7, lines 34-43). Therefore, the release of carbon from the first dielectric layer into the second dielectric layer (a low-k dielectric layer according to Lee Embodiment 1, [0040]) is an intrinsic property of annealing the layers at the temperatures disclosed by Lee Embodiment 1.), wherein during the anneal process the second dielectric layer is oxidized ([0041]: annealing process 144 including oxidant gas which reacts with the second insulating layer 142).
Lee Embodiment 1, however, does not teach that after performing the anneal process the first dielectric layer has a second thickness that is smaller than the first thickness.
Other relevant prior art is Peng (US 2021/0225692 A1, Fig. 8, [0040]) and Kao-264 (US 2022/0336264 A1, Fig. 4, [0042]), each teaching annealing the second dielectric layer, but do not disclose or indicate that the thickness of the first dielectric layer decreases. As an alternative process, Peng (another embodiment, [0041]) and Kao-454 (US 2020/0365454 A1, Figs. 1B and 1C) teach annealing the second dielectric layer, where first dielectric layer (Kao-454: first dielectric layer 112, Figs. 1B-C) disappears after annealing. No prior art has been identified that teaches the limitation that “after performing the anneal process the first dielectric layer has a second thickness that is smaller than the first thickness”, when this limitation is combined with the limitations of claim 1.
There has been no other prior art identified that can, by itself, or in combination others, render claim 1 anticipated or obvious. Therefore, claim 1 is allowed, as the references of the prior art of record considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding the limitation that “after performing the anneal process the first dielectric layer has a second thickness that is smaller than the first thickness”, when this limitation is accompanied by the remaining structural and methodological limitations of claim 1.
Consequently, claims 2-8 are also allowed, because these claims inherit the allowable subject matter of claim 1.
Regarding claim 8 and its dependent claims 12-15 and 21-23, the independent claim 8 disclosing the limitation “after oxidizing the second dielectric layer, the first dielectric layer is partially consumed” is allowed as also stated in the final office action mailed on 4/1/2026. The closest prior art identified for the invention claimed in claim 8 is again Lee Embodiment 1 (US 2019/0287971 A1, Figs. 2-7, [0006]). Accordingly, Lee Embodiment 1 teaches a method (for manufacturing a FinFET device, Figs. 4-10, [0006]) comprising:
etching a semiconductor substrate (semiconductor substrate 100, Fig. 4, [0029]) to form a plurality of first fins (first fin structures 110a, Fig. 4, [0029]) that protrude from the semiconductor substrate (semiconductor substrate 100, Fig. 4), a first trench (trench 111a, Fig. 4, [0029]) being interposed between adjacent first fins (first fin structures 110a, Fig. 4) of the plurality of first fins (first fin structures 110a, Fig. 4);
forming a shallow trench isolation (STI) region (region formed by first liner layer 130, second liner layer 132, and isolation features 142a, Fig. 8, [0018]-[0019]) in the first trench (trench 111a, Figs. 4 and 8), wherein forming the STI region (region formed by first liner layer 130, second liner layer 132, and isolation features 142a, Fig. 8) comprises:
conformally depositing a first dielectric layer (liner structure 140 comprising first liner layer 130 and second liner 132, Fig. 5, [0033]: “… a liner structure 140 is conformally formed over the structure shown in FIG. 4 …“) over the plurality of first fins (first fin structures 110a, Fig. 5) and on sidewalls and a bottom surface of the first trench (trench 111a, Fig. 5), wherein the first dielectric layer (liner structure 140) comprises carbon ([0020]);
forming a second dielectric layer (insulating layer 142, Fig. 6, [0040]) over the first dielectric layer (liner structure 140, Fig. 6) and in the first trench (trench 111a, Fig. 6), wherein the second dielectric layer (insulating layer 142, Fig. 6) fills the first trench (trench 111a, Fig. 6); and
oxidizing ([0041]: annealing process 144 including oxidant gas) the second dielectric layer (insulating layer 142, Fig. 6), wherein during oxidizing the second dielectric layer (insulating layer 142, Fig. 6), carbon from the first dielectric layer (liner structure 140, Fig. 6) diffuses into the second dielectric layer (insulating layer 142, Fig. 6: while Lee Embodiment 1 does not disclose that the anneal process releases carbon from the first dielectric layer into second dielectric layer, Lee Embodiment 1 discloses that the anneal process is performed at a temperature in a range from 150° C to about 950° C, for more than 0.5 hour ([0041]). This anneal process will drive out the carbon from the first dielectric layer by diffusion as evidenced by Kao-771 (US 2021/0082771 A1), where annealing dielectric layers 112 ([0027]: SiOCN layer) and 116 ([0048]: SiOCN layer) at about 500° C to about 700°C for more than 0.5 hour ([0053]) would drive the carbon out by diffusion ([0055]). As further evidenced by Gabriel (US6475929), the diffused carbon will be absorbed by the neighboring low-k dielectric layer (col. 7, lines 34-43). Therefore, the release of carbon from the first dielectric layer into the second dielectric layer (a low-k dielectric layer according to Lee Embodiment 1, [0040]) is an intrinsic property of annealing the layers at the temperatures disclosed by Lee Embodiment 1.), wherein oxidizing the second dielectric layer (insulating layer 142, Fig. 6) comprises performing an anneal process (annealing process 144, Fig. 6, [0041]) while exposing the second dielectric layer (insulating layer 142, Fig. 6) to an oxygen-containing ambient ([0041]-[0042]: “… the wet steam anneal process…”).
Lee Embodiment 1, however, does not teach that after oxidizing the second dielectric layer, the first dielectric layer is partially consumed.
Other relevant prior art is Peng (US 2021/0225692 A1, Fig. 8, [0040]) and Kao (US 2022/0336264 A1, Fig. 4, [0042]), each teaching annealing the second dielectric layer, but do not disclose or indicate that the first dielectric layer is consumed. As an alternative process, Peng (another embodiment, [0041]) and Kao-454 (US 2020/0365454 A1, Figs. 1B and 1C where first dielectric layer 112 is fully consumed after annealing) teach annealing the second dielectric layer, where the first dielectric fully consumed. No prior art has been identified that teaches the limitation that “after oxidizing the second dielectric layer, the first dielectric layer is partially consumed”, when this limitation is combined with the limitations of claim 8.
There has been no other prior art identified that can, by itself, or in combination others, render claim 8 anticipated or obvious. Therefore, claim 8 is allowed, as the references of the prior art of record considered pertinent to the applicant’s disclosure and examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding the limitation that “after oxidizing the second dielectric layer, the first dielectric layer is partially consumed”, when this limitation is accompanied by the remaining structural and methodological limitations of claim 8.
Consequently, claims 12-15 and 21-23 are also allowed, because these claims inherit the allowable subject matter of claim 8.
Response to Arguments
It has been acknowledged that the applicant amended claim 16 per response dated on 5/28/2026 by including the limitation "wherein topmost surfaces of the first plurality of fins are disposed above a topmost surface of the STI layer, and wherein the topmost surfaces of the first plurality of fins are disposed above a bottommost surface of the insulating fin”. Applicant's arguments with respect to claims have been fully considered. The Examiner respectfully disagrees with the Applicant on that the amended claims 16 overcomes the rejection based on Keng (US 2021/0408012 A1) in view of Peng (US 2021/0225692 A1), because according to Keng the fins also include the channel layers 208 and sacrificial layers 206 (see Fig. 3, [0016]: “Each of the fin-shaped structures 212 includes a base portion 12B formed from the substrate 202 and a stack portion 12S”). Accordingly, Keng’s fins are fin structures 212 comprising the channel stacks. Based on this, Keng also meets the new limitation “wherein topmost surfaces of the first plurality of fins are disposed above a topmost surface of the STI layer, and wherein the topmost surfaces of the first plurality of fins are disposed above a bottommost surface of the insulating fin”, and Keng in view of Peng still teaches all the limitations of amended claim 16. Therefore, unless fins of claim 16 are not limited to be a direct extension of the substrate made of the same material as the substrate, claim 16 cannot overcome Keng in view of Peng.
However, for demonstrating that even limiting the fins to be a direct extension of the substrate is not enough to render claim 16 to be allowable, claim 16 is now rejected based on a new prior art, Jhan (US 2021/0257480 A1), in combination with Peng as detailed in the current office action above. Claims 17-20 are also rejected based on Jhan and Peng or their combination with prior art of the final office action.
For the purpose of compact prosecution, the Examiner notes that incorporating more limitations regarding the structures and their material compositions in the semiconductor device might make claim 16 overcome the prior art of the current office action.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin (US 2021/0126109 A1) teaches a semiconductor device, which is relevant to all claims 16-20.
Lin (US 2021/0328043 A1) teaches a semiconductor device, which is relevant to all claims 16-20.
Chiang (US 2021/0375858 A1) teaches a semiconductor device, which is relevant to all claims 16-20.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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