DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, corresponding to claims 1-15 and new claims 21-25, in the reply filed on December 12, 2025 is acknowledged. No claims have been amended. Claims 21-25 have been added. Claims 16-20 were canceled. As a result, claims 1-15 and 21-25 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claim 1-15 and 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over (US 20220093472 A1) “Hsu et al.” in view of Huang, Mao-Lin (US 20210336033 A1) “Huang et al.”.
Regarding Independent Claim 1, Hsu et al. Figs. 1-18 discloses, a method, comprising:
forming a channel (“The stack of semiconductor layers 215 serve as the transistor channels for the respective transistor.” ¶ [0022]) structure on a substrate (“a stack of semiconductor layers 215 suspended over the substrate 202” ¶ [0022]);
forming an interfacial layer on the channel structure (“forms an interfacial dielectric layer 280 wrapping around the channel layers 215,” ¶ [0034]);
forming a first high-k dielectric layer on the interfacial layer (“forms a high-k dielectric layer 282 over the interfacial layer 280” ¶ [0035]);
forming dipoles in the first high-k dielectric layer with a dopant (“dipole elements 216′ and 220” ¶ [0042]), wherein the dopant comprises a first metal element (“the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La.sub.2O.sub.3), yttrium oxide (Y.sub.2O.sub.3), titanium oxide (TiO.sub.2), or other suitable n-dipole materials” ¶ [0071]); and
forming a second high-k dielectric layer (“forms another patterned hard mask 290”; “the patterned hard mask 290 may include … alumina, or other suitable materials.” ¶ [0037]; alumina is a high-k dielectric material) on the first high-k dielectric layer, wherein the second high-k dielectric layer (“forms another patterned hard mask 290”; “the patterned hard mask 290 may include … alumina, or other suitable materials.” ¶ [0037]; alumina is a high-k dielectric material) comprises a second metal element (“the patterned hard mask 290 may include … alumina, or other suitable materials.” ¶ [0037]) different from the first metal element (“the patterned hard mask 290 includes a material that is different than a material of the high-k dielectric layer 282” ¶ [0037]).
However, Hsu et al. does not explicitly disclose, forming a second high-k dielectric layer on the first high-k dielectric layer.
In the similar field of endeavor of nanostructure transistors, Huang et al. Figs. 10A-11D and 16A-18C discloses forming a second high-k dielectric layer (“forms a passivation layer 342”; “the passivation layer 342 includes a semiconductor material, a dielectric material, a bi-layer of a semiconductor material and a dielectric material, or other suitable material” ¶ [0039]; “the passivation layer 342 may include … a layer of alumina, or other suitable materials.” ¶ [0039]; Alumina is a high-k dielectric) on the first high-k dielectric layer (“high-k dielectric layer 282” ¶ [0052]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Hsu et al. with the structure including the passivation layer of Huang et al. in order to improve V.sub.t uniformity in the n-type GAA transistors (Huang et al. ¶ [0017]).
Regarding Claim 2, Hsu et al. as modified by Huang et al. discloses the limitations of claim 1. Hsu et al. further discloses comprising annealing (“a thermal drive-in process 222” ¶ [0040]) the first and second high-k dielectric layers at a temperature from about 500 °C to about 700 °C (“In an embodiment, the thermal drive-in process 222 is a spike anneal process or a soak anneal process at a temperature in a range from about 600° C. to about 1,000° C.”; “In another embodiment, the thermal drive-in process 222 is a furnace anneal process at a temperature in a range from about 300° C. to about 600° C.” ¶ [0040]) to diffuse the second metal element into the first high-k dielectric layer (“to migrate (or diffuse) from the dipole layer 220 into the high-k dielectric layer 282 thereunder” ¶ [0040]).
Regarding Claim 3, Hsu et al. as modified by Huang et al. discloses the limitations of claim 1. Hsu et al. further discloses further comprising forming a gate structure on the second high-k dielectric layer (“In some implementations, a blocking layer (not shown) is optionally formed (e.g., by ALD) over the work function metal layer 288 before forming the bulk metal layer 350, such that the bulk metal layer 350 is disposed on the blocking layer. After the bulk metal layer 350 is deposited, a planarization process may then be performed to remove excess gate materials from the device 200” ¶ [0044]).
Regarding Claim 4, Hsu et al. as modified by Huang et al. discloses the limitations of claim 1. Hsu et al. further discloses wherein forming the channel structure comprises forming a set of nanostructures on the substrate (“The embodiments illustrated in FIGS. 2B, 2C, and 2D are nanosheet FETs, where their channel layers 215 are in the shape of sheets” ¶ [0019]).
Regarding Claim 5, Hsu et al. as modified by Huang et al. discloses the limitations of claim 1. Hsu et al. further discloses wherein forming the second high-k dielectric layer comprises depositing a high-k dielectric material on the first high-k dielectric layer, wherein the high-k dielectric material comprises lutetium oxide, yttrium oxide (“The high-k dielectric layer 282 includes a high-k dielectric material, such as … Y.sub.2O.sub.3, other suitable high-k dielectric material, or combinations thereof” ¶ [0035]), thulium oxide, erbium oxide, or gadolinium oxide.
Regarding Claim 6, Hsu et al. as modified by Huang et al. discloses the limitations of claim 1. Hsu et al. further discloses wherein the dopant comprises lutetium oxide, scandium oxide, yttrium oxide, thulium oxide, erbium oxide, gadolinium oxide, lanthanum oxide zinc oxide, germanium oxide, aluminum oxide, titanium oxide, or vanadium oxide (“n-dipole material such as lanthanum oxide (La.sub.2O.sub.3), yttrium oxide (Y.sub.2O.sub.3), titanium oxide (TiO.sub.2), or other suitable n-dipole materials.” ¶ [0036]).
Regarding Claim 7, Hsu et al. as modified by Huang et al. discloses the limitations of claim 1. However, Hsu et al. does not disclose further comprising forming a third high-k dielectric layer on the second high-k dielectric layer, wherein the first and third high-k dielectric layers comprise a same high-k dielectric material.
In the similar field of endeavor of nanostructure transistors, Huang et al. Figs. 10A-11D and 16A-18C discloses further comprising forming a third high-k dielectric layer (“In some implementations, a passivation layer (or a blocking layer) 352 (e.g., shown in FIG. 18B)” ¶ [0051]) on the second high-k dielectric layer 342,
wherein the first 282 (“layer 282 includes a high-k dielectric material, such as … Al.sub.2O.sub.3,” ¶ [0029]) and third high-k dielectric layers 352 comprise a same high-k dielectric material (“the passivation layer 342 may include … a layer of alumina, or other suitable materials.” ¶ [0039]; “The passivation layer 352 may include the same or similar material as the passivation layer 342” ¶ [0053]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Hsu et al. with the structure including the passivation layer of Huang et al. in order to improve V.sub.t uniformity in the n-type GAA transistors (Huang et al. ¶ [0017]).
Regarding Claim 8, Hsu et al. as modified by Huang et al. discloses the limitations of claim 1. Hsu et al. further discloses wherein forming the dipoles in the first high-k dielectric layer comprises:
depositing a dipole source layer on the first high-k dielectric layer (“forms another dipole layer 220 over the high-k dielectric layer 282” ¶ [0036]), wherein the dipole source layer comprises the dopant (“the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La.sub.2O.sub.3), yttrium oxide (Y.sub.2O.sub.3), titanium oxide (TiO.sub.2), or other suitable n-dipole materials” ¶ [0071]);
annealing (“The dipole elements can be driven into the high-k dielectric layer 282, for example, by an annealing process.” ¶ [0036]) the dipole source layer to diffuse the dopant into the first high-k dielectric layer (“to migrate (or diffuse) from the dipole layer 220 into the high-k dielectric layer 282 thereunder” ¶ [0040]); and
removing the dipole source layer (“removes the dipole layer 220” ¶ [0038]).
Regarding Independent Claim 9, Hsu et al. Figs. 1-18 discloses, a method, comprising:
forming (“The stack of semiconductor layers 215 serve as the transistor channels for the respective transistor.” ¶ [0022]) first and second channel structures (“transistors 200A and 200B further includes a stack of semiconductor layers 215” ¶ [0022]) on a substrate (“a stack of semiconductor layers 215 suspended over the substrate 202” ¶ [0022]);
forming an interfacial layer on the first and second channel structures (“forms an interfacial dielectric layer 280 wrapping around the channel layers 215,” ¶ [0034]);
forming a first dielectric layer on the interfacial layer over the first and second channel structures (“forms a high-k dielectric layer 282 over the interfacial layer 280” ¶ [0035]);
forming dipoles (“dipole elements 216′ and 220” ¶ [0042]), in the first dielectric layer over the first channel structure with a first dopant, wherein the first dopant comprises a first metal element (“the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La.sub.2O.sub.3), yttrium oxide (Y.sub.2O.sub.3), titanium oxide (TiO.sub.2), or other suitable n-dipole materials” ¶ [0071]);
forming dipoles (“dipole elements 216′ and 220” ¶ [0042]) in the first dielectric layer over the second channel structure with a second dopant, wherein the second dopant comprises a second metal element different (“some embodiments of the present disclosure may incorporate an n-type dipole material into a gate dielectric layer of an NMOSFET to further reduce its threshold voltage and incorporate a p-type dipole material into a gate dielectric layer of a PMOSFET to further reduce its threshold voltage.” ¶ [0016]; “the transistors 200A and 200B may.… be one n-type transistor and one p-type transistor.” ¶ [0019]) from the first metal element (“the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La.sub.2O.sub.3), yttrium oxide (Y.sub.2O.sub.3), titanium oxide (TiO.sub.2), or other suitable n-dipole materials” ¶ [0071]); and
forming a second dielectric layer on the first dielectric layer (“forms another patterned hard mask 290”; “the patterned hard mask 290 may include … alumina, or other suitable materials.” ¶ [0037]; alumina is a high-k dielectric material), wherein the second dielectric layer comprises a third metal element different from the first and second metal elements (“the patterned hard mask 290 includes a material that is different than a material of the high-k dielectric layer 282” ¶ [0037]).
However, Hsu et al. does not explicitly disclose, forming a second dielectric layer on the first dielectric layer.
In the similar field of endeavor of nanostructure transistors, Huang et al. Figs. 10A-11D and 16A-18C discloses forming a second dielectric layer (“forms a passivation layer 342”; “the passivation layer 342 includes a semiconductor material, a dielectric material, a bi-layer of a semiconductor material and a dielectric material, or other suitable material” ¶ [0039]; “the passivation layer 342 may include … a layer of alumina, or other suitable materials.” ¶ [0039]; Alumina is a high-k dielectric) on the first dielectric layer (“high-k dielectric layer 282” ¶ [0052]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Hsu et al. with the structure including the passivation layer of Huang et al. in order to improve V.sub.t uniformity in the n-type GAA transistors (Huang et al. ¶ [0017]).
Regarding Claim 10, Hsu et al. as modified by Huang et al. discloses the limitations of claim 9. Hsu et al. further discloses further comprising annealing (“The dipole elements can be driven into the high-k dielectric layer 282, for example, by an annealing process.” ¶ [0036]) the first and second dielectric layers at a temperature from about 500 °C to about 700 °C (“In an embodiment, the thermal drive-in process 222 is a spike anneal process or a soak anneal process at a temperature in a range from about 600° C. to about 1,000° C.”; “In another embodiment, the thermal drive-in process 222 is a furnace anneal process at a temperature in a range from about 300° C. to about 600° C.” ¶ [0040]) to diffuse the third metal element into the first and second dielectric layers (“to migrate (or diffuse) from the dipole layer 220 into the high-k dielectric layer 282 thereunder” ¶ [0040]).
Regarding Claim 11, Hsu et al. as modified by Huang et al. discloses the limitations of claim 9. Hsu et al. further discloses further comprising forming a first gate structure on the second dielectric layer over the first channel structure (“In some implementations, a blocking layer (not shown) is optionally formed (e.g., by ALD) over the work function metal layer 288 before forming the bulk metal layer 350, such that the bulk metal layer 350 is disposed on the blocking layer. After the bulk metal layer 350 is deposited, a planarization process may then be performed to remove excess gate materials from the device 200” ¶ [0044]) and a second gate structure different from the first gate structure on the second dielectric layer over the second channel structure (“In some implementations, a blocking layer (not shown) is optionally formed (e.g., by ALD) over the work function metal layer 288 before forming the bulk metal layer 350, such that the bulk metal layer 350 is disposed on the blocking layer. After the bulk metal layer 350 is deposited, a planarization process may then be performed to remove excess gate materials from the device 200” ¶ [0044]).
Regarding Claim 12, Hsu et al. as modified by Huang et al. discloses the limitations of claim 9. Hsu et al. further discloses wherein forming the first and second channel structures comprises forming first and second sets of nanostructures on the substrate (“The embodiments illustrated in FIGS. 2B, 2C, and 2D are nanosheet FETs, where their channel layers 215 are in the shape of sheets” ¶ [0019]).
Regarding Claim 13, Hsu et al. as modified by Huang et al. discloses the limitations of claim 9. Hsu et al. further discloses wherein forming the second dielectric layer comprises depositing a high-k dielectric material on the first dielectric layer, wherein the high-k dielectric material comprises lutetium oxide, yttrium oxide (“The high-k dielectric layer 282 includes a high-k dielectric material, such as … Y.sub.2O.sub.3, other suitable high-k dielectric material, or combinations thereof” ¶ [0035]), thulium oxide, erbium oxide, or gadolinium oxide.
Regarding Claim 14, Hsu et al. as modified by Huang et al. discloses the limitations of claim 9. However, Hsu et al. does not disclose further comprising forming a third dielectric layer on the second dielectric layer, wherein the first and third dielectric layers comprise a same high-k dielectric material.
In the similar field of endeavor of nanostructure transistors, Huang et al. Figs. 10A-11D and 16A-18C discloses further comprising forming a third dielectric layer (“In some implementations, a passivation layer (or a blocking layer) 352 (e.g., shown in FIG. 18B)” ¶ [0051]) on the second dielectric layer 342,
wherein the first 282 (“layer 282 includes a high-k dielectric material, such as … Al.sub.2O.sub.3,” ¶ [0029]) and third high-k dielectric layers 352 comprise a same high-k dielectric material (“the passivation layer 342 may include … a layer of alumina, or other suitable materials.” ¶ [0039]; “The passivation layer 352 may include the same or similar material as the passivation layer 342” ¶ [0053]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Hsu et al. with the structure including the passivation layer of Huang et al. in order to improve V.sub.t uniformity in the n-type GAA transistors (Huang et al. ¶ [0017]).
Regarding Claim 15, Hsu et al. as modified by Huang et al. discloses the limitations of claim 9. Hsu et al. further discloses wherein forming the dipoles in the first dielectric layer over the first and second channel structures comprises:
depositing a first dipole source layer (“forms another dipole layer 220 over the high-k dielectric layer 282” ¶ [0036]), comprising the first dopant on the first dielectric layer over the first channel structure, wherein the first dopant comprises lutetium oxide, scandium oxide, yttrium oxide, thulium oxide, erbium oxide, gadolinium oxide, or lanthanum oxide (“the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La.sub.2O.sub.3), yttrium oxide (Y.sub.2O.sub.3), titanium oxide (TiO.sub.2), or other suitable n-dipole materials” ¶ [0071]);
annealing (“The dipole elements can be driven into the high-k dielectric layer 282, for example, by an annealing process.” ¶ [0036]) the first dipole source layer to diffuse the first dopant into the first dielectric layer over the first channel structure (“to migrate (or diffuse) from the dipole layer 220 into the high-k dielectric layer 282 thereunder” ¶ [0040]);
removing the first dipole source layer (“removes the dipole layer 220” ¶ [0038]);
depositing a second dipole source layer (“forms another dipole layer 220 over the high-k dielectric layer 282” ¶ [0036]), comprising the second dopant on the first dielectric layer over the second channel structure, wherein the second dopant comprises zinc oxide, germanium oxide, aluminum oxide, titanium oxide, or vanadium oxide (“he p-dipole material may include germanium oxide, aluminum oxide, gallium oxide, or zinc oxide.” ¶ [0030]);
annealing (“The dipole elements can be driven into the high-k dielectric layer 282, for example, by an annealing process.” ¶ [0036]) the second dipole source layer to diffuse the second dopant into the first dielectric layer over the second channel structure (“to migrate (or diffuse) from the dipole layer 220 into the high-k dielectric layer 282 thereunder” ¶ [0040]); and
removing the second dipole source layer (“removes the dipole layer 220” ¶ [0038]).
Regarding Independent Claim 21, Hsu et al. Figs. 1-18 discloses, a method, comprising:
forming a channel (“The stack of semiconductor layers 215 serve as the transistor channels for the respective transistor.” ¶ [0022]) structure on a substrate (“a stack of semiconductor layers 215 suspended over the substrate 202” ¶ [0022]);
forming an interfacial layer on the channel structure (“forms an interfacial dielectric layer 280 wrapping around the channel layers 215,” ¶ [0034]);
forming a first high-k dielectric layer on the interfacial layer (“forms a high-k dielectric layer 282 over the interfacial layer 280” ¶ [0035]);
forming a second high-k dielectric layer (“forms another patterned hard mask 290”; “the patterned hard mask 290 may include … alumina, or other suitable materials.” ¶ [0037]; alumina is a high-k dielectric material) on the first high-k dielectric layer 282, wherein the first and second high-k dielectric layers comprise different high-k dielectric materials (“The high-k dielectric layer 282 includes a high-k dielectric material, such as … Y.sub.2O.sub.3, other suitable high-k dielectric material, or combinations thereof” ¶ [0035]; “the patterned hard mask 290 may include … alumina, or other suitable materials.” ¶ [0037]; “the patterned hard mask 290 includes a material that is different than a material of the high-k dielectric layer 282” ¶ [0037]); and
doping the second high-k dielectric layer with a dopant (“dipole elements 216′ and 220” ¶ [0042]), wherein the dopant forms dipoles in the second high-k dielectric layer (“to migrate (or diffuse) from the dipole layer 220 into the high-k dielectric layer 282 thereunder” ¶ [0040]).
However, Hsu et al. does not explicitly disclose, forming a second high-k dielectric layer on the first high-k dielectric layer.
In the similar field of endeavor of nanostructure transistors, Huang et al. Figs. 10A-11D and 16A-18C discloses forming a second high-k dielectric layer (“forms a passivation layer 342”; “the passivation layer 342 includes a semiconductor material, a dielectric material, a bi-layer of a semiconductor material and a dielectric material, or other suitable material” ¶ [0039]; “the passivation layer 342 may include … a layer of alumina, or other suitable materials.” ¶ [0039]; Alumina is a high-k dielectric) on the first high-k dielectric layer (“high-k dielectric layer 282” ¶ [0052]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Hsu et al. with the structure including the passivation layer of Huang et al. in order to improve V.sub.t uniformity in the n-type GAA transistors (Huang et al. ¶ [0017]).
Regarding Claim 22, Hsu et al. as modified by Huang et al. discloses the limitations of claim 21. Hsu et al. further discloses further comprising annealing (“The dipole elements can be driven into the high-k dielectric layer 282, for example, by an annealing process.” ¶ [0036]) the first and second dielectric layers at a temperature from about 500 °C to about 700 °C (“In an embodiment, the thermal drive-in process 222 is a spike anneal process or a soak anneal process at a temperature in a range from about 600° C. to about 1,000° C.”; “In another embodiment, the thermal drive-in process 222 is a furnace anneal process at a temperature in a range from about 300° C. to about 600° C.” ¶ [0040]) to diffuse the third metal element into the first and second dielectric layers (“to migrate (or diffuse) from the dipole layer 220 into the high-k dielectric layer 282 thereunder” ¶ [0040]).
Regarding Claim 23, Hsu et al. as modified by Huang et al. discloses the limitations of claim 21. Hsu et al. further discloses wherein forming the second high-k dielectric layer comprises depositing a high-k dielectric material on the first high-k dielectric layer, wherein the high-k dielectric material comprises lutetium oxide, yttrium oxide (“The high-k dielectric layer 282 includes a high-k dielectric material, such as … Y.sub.2O.sub.3, other suitable high-k dielectric material, or combinations thereof” ¶ [0035]), thulium oxide, erbium oxide, or gadolinium oxide.
Regarding Claim 24, Hsu et al. as modified by Huang et al. discloses the limitations of claim 21. However, Hsu et al. does not disclose further comprising forming a third high-k dielectric layer on the second high-k dielectric layer, wherein the second and third high-k dielectric layers comprise a same high-k dielectric material.
In the similar field of endeavor of nanostructure transistors, Huang et al. Figs. 10A-11D and 16A-18C discloses further comprising forming a third high-k dielectric layer (“In some implementations, a passivation layer (or a blocking layer) 352 (e.g., shown in FIG. 18B)” ¶ [0051]) on the second high-k dielectric layer 342,
wherein the second 342 and third high-k dielectric layers 352 comprise a same high-k dielectric material (“the passivation layer 342 may include … a layer of alumina, or other suitable materials.” ¶ [0039]; “The passivation layer 352 may include the same or similar material as the passivation layer 342” ¶ [0053]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the structure of Hsu et al. with the structure including the passivation layer of Huang et al. in order to improve V.sub.t uniformity in the n-type GAA transistors (Huang et al. ¶ [0017]).
Regarding Claim 25, Hsu et al. as modified by Huang et al. discloses the limitations of claim 21. Hsu et al. further discloses wherein forming the dipoles in the first high-k dielectric layer comprises:
depositing a dipole source layer on the first high-k dielectric layer (“forms another dipole layer 220 over the high-k dielectric layer 282” ¶ [0036]), wherein the dipole source layer comprises the dopant (“the dipole layer 220 includes an n-dipole material such as lanthanum oxide (La.sub.2O.sub.3), yttrium oxide (Y.sub.2O.sub.3), titanium oxide (TiO.sub.2), or other suitable n-dipole materials” ¶ [0071]);
annealing (“The dipole elements can be driven into the high-k dielectric layer 282, for example, by an annealing process.” ¶ [0036]) the dipole source layer to diffuse the dopant into the first high-k dielectric layer (“to migrate (or diffuse) from the dipole layer 220 into the high-k dielectric layer 282 thereunder” ¶ [0040]); and
removing the dipole source layer (“removes the dipole layer 220” ¶ [0038]).
Conclusion
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893