Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/12/2026 has been entered.
Response to Amendment
The amendment filed 5/12/2026 has been entered. Claims 1, 4-5, 8-9, 12-13, and 16 are pending.
Response to Arguments
Applicant's arguments filed 5/12/2026 have been fully considered but they are not persuasive.
Regarding amended claims 1 and 9, Applicant contends that a person of ordinary skill in the art would “have no motivation to encapsulate the board-to-board (B2B) pad, and would appreciate to prevent the B2B pad from being damaged by mold pressure, because the B2B pad is configured for connecting the package to another package.” However, it is not the pad that is being encapsulated. Rather, it is a (potential) second chip or package that is being encapsulated, and this is what renders the claim obvious, in the view of the Examiner.
Had Applicant explicitly precluded the presence of a second chip or package on the second contact pad (which seems supported by at least Fig. 2A in the specification) as a limitation of Claim 1, Examiner would have found Applicant’s arguments more persuasive. As it stands, the claim does not prevent a second chip or package from being added and encapsulated, all in the same process.
In other words, Examiner is contending that a person of ordinary skill in the art would find it obvious to add a second chip or package and encapsulate both the first and second chips through the first and second cavities in the same method steps. If Applicant makes it explicit that this is not the case, by amending Claim 1 in the manner suggested above, then this would strengthen the claim, in the view of the Examiner.
Because Claim 1 (and Claim 9) have been amended largely with subject matter that has already been rejected, Examiner is largely repeating the rejections from the previous Office Action. Applicant is advised to carefully consider the response above, and, if Applicant agrees, to amend Claim 1 (and 9) in the manner suggested.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over US20080150119A1 (Jang) in view of US20110057330A1 (Ushiyama).
Regarding Claim 1, Jang discloses a method for forming a semiconductor device (Fig. 8, el. 800, Para. [0065]), comprising: providing a package (Fig. 8, el. 802, Para. [0065]) comprising: a substrate (Fig. 1, el. 104, Para. [0021]); a solder resist layer (Fig. 1, el. 112, Para. [0024]) disposed on a top surface of the substrate (Fig. 1, Para. [0024]); an electronic component (Fig. 1, el. 108, Para. [0022]) mounted on the top surface of substrate (Para. [0023]); a first contact pad (Fig. 1, el. 114, Para. 0024]) disposed on the top surface of the substrate (Fig. 1) and exposed from the solder resist layer (Fig. 1); and
a second contact pad (Fig. 1, where there are multiple contact pads 114), wherein the first contact pad is between the electronic component and the second contact pad (Jang, Fig. 1, el. 114 that is to the right of the first contact pad closest to the chip 108), and the second contact pad is a board-to-board pad configured for connecting the package to another package (Para. [0024]); providing a mold (Fig. 8, el. 804, Para. [0065]; Fig. 1, el. 102, Para. [0021])) comprising: a first cavity (Fig. 1, el. 122, Para. [0026]) exposed from a bottom surface of the mold (Fig. 1); and a recess (Fig. 1, el. 126, Para. [0028]) formed adjacent to the first cavity (Fig. 1); engaging the mold and the package with the first cavity over the electronic component and the recess between the electronic component and the first contact pad (Fig. 8, el. 806, Para. [0065]); and injecting encapsulation material into the first cavity to form an encapsulant over the electronic component (Fig. 8, el. 808, Para. [0065]).
Jang does not disclose that the solder resist layer is a stress absorbing layer that comprises solder resist, where the stress absorbing layer ranges from 20 to 100 um, does not disclose that the second contact pad is a board-to-does not disclose that the mold further comprises a second cavity, and when the mold and the package are engaged, the second cavity is over the second contact pad
Ushiyama discloses a package (Fig. 1, el. 1, Para. [0030]) with a substrate (Fig. 1, el. 10, Para. [0030) with a solder resist layer (Fig. 3, el. 13, Para. [0033]) on the top layer of the substrate (Fig. 3, Para. [0033]) where the solder resist layer has elastomer and is a stress absorbing layer (Para. [0038]), where and has a thickness from 20 to 100 um (Para. [0037]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use the stress absorbing layer (solder resist and elastomer) disclosed by Ushiyama as a substitute for the solder resist layer of Jang. As disclosed by Ushiyama, doing so enables the solder resist layer to bear the strain caused by thermal deformation of the substrate and semiconductor element in the resin sealing step (Para. [0038]). Also, it would have been obvious to make the thickness between 20 to 100 um. As disclosed by Ushiyama, a thickness in this range would cover the wiring, while also not causing cracks (Para. [0037]). Further, it would have been obvious to add a second cavity to the mold discloses by Jang for the purpose of providing the ability to add another board or chip the substrate, and to encapsulate that board or chip through a second cavity in the same process of encapsulating the first chip. Adding more chips or another board to the substrate would allow for the creation of a multi-chip module or stacked substrate, which can create more complex devices.
Regarding Claim 4, Jang in view of Ushiyama discloses the method of claim 1, wherein the bottom surface of the mold compresses the stress absorbing layer when the mold and the package are engaged (Jang, Para. [0031]).
Regarding Claim 5, Jang in view of Ushiyama discloses the method of claim 1, wherein the recess is formed around a perimeter of the first cavity (Jang, Para. [0034]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Ushiyama.
Regarding Claim 8, Jang in view of Ushiyama discloses the method of claim 1,
Jang in view of Ushiyama does not disclose that the first contact pad is a ground pad.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to make the first contact pad in Ushiyama a ground pad. A ground pad is needed in nearly all chip packages, and provides a way to ground all the chips on the substrate through a wiring layer.
Claims 9, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Ushiyama.
Regarding Claim 9, Jang discloses a molding apparatus for forming an encapsulant on a package (Fig. 1, el. 102, Para. [0021]), comprising: a mold (Fig. 1, el. 102, Para. [0021]), wherein the mold comprising: a first cavity (Fig. 1, el. 122, Para. [0026]) exposed from a bottom surface of the mold (Fig. 1); and a recess (Fig. 1, el. 126, Para. [0028]) formed adjacent to the first cavity (Fig. 1); wherein the package comprises: a substrate (Fig. 1, el. 104, Para. [0021]); a solder resist layer (Fig. 1, el. 112, Para. [0024]) disposed on a top surface of the substrate (Fig. 1, Para. [0024]); an electronic component (Fig. 1, el. 108, Para. [0022]) mounted on the top surface of substrate (Para. [0023]); and a first contact pad (Fig. 1, el. 114, Para. 0024]) disposed on the top surface of the substrate (Fig. 1) and exposed from the solder resist layer (Fig. 1); and a second contact pad (Jang, Fig. 1, where there are multiple contact pads 114), and the first contact pad is between the electronic component and the second contact pad (Jang, Fig. 1, el. 114 that is to the right of the first contact pad closest to the chip 108), and the second contact pad is a board-to-board pad configured for connecting the package to another package (Para. [0024]); and wherein the mold is configured for engaging the package with the first cavity over the electronic component and the recess between the electronic component and the first contact pad (Fig. 8, el. 806, Para. [0065]); and encapsulation material can be injected into the first cavity to form an encapsulant over the electronic component (Fig. 8, el. 808, Para. [0065]).
Jang does not disclose that the solder resist layer is a stress absorbing layer that comprises solder resist, where the stress absorbing layer ranges from 20 to 100 um, does not disclose that the second contact pad is a board-to-does not disclose that the mold further comprises a second cavity, and when the mold and the package are engaged, the second cavity is over the second contact pad
Ushiyama discloses a package (Fig. 1, el. 1, Para. [0030]) with a substrate (Fig. 1, el. 10, Para. [0030) with a solder resist layer (Fig. 3, el. 13, Para. [0033]) on the top layer of the substrate (Fig. 3, Para. [0033]) where the solder resist layer has elastomer and is a stress absorbing layer (Para. [0038]), where and has a thickness from 20 to 100 um (Para. [0037]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use the stress absorbing layer (solder resist and elastomer) disclosed by Ushiyama as a substitute for the solder resist layer of Jang. As disclosed by Ushiyama, doing so enables the solder resist layer to bear the strain caused by thermal deformation of the substrate and semiconductor element in the resin sealing step (Para. [0038]). Also, it would have been obvious to make the thickness between 20 to 100 um. As disclosed by Ushiyama, a thickness in this range would cover the wiring, while also not causing cracks (Para. [0037]). Further, it would have been obvious to add a second cavity to the mold discloses by Jang for the purpose of providing the ability to add another board or chip the substrate, and to encapsulate that board or chip through a second cavity in the same process of encapsulating the first chip. Adding more chips or another board to the substrate would allow for the creation of a multi-chip module or stacked substrate, which can create more complex devices.
Regarding Claim 12, Jang in view of Ushiyama discloses the molding apparatus of claim 9, wherein the bottom surface of the mold compresses the stress absorbing layer when the mold and the package are engaged (Jang, Para. [0031]).
Regarding Claim 13, Jang in view of Ushiyama discloses the molding apparatus of claim 9, wherein the recess is formed around a perimeter of the first cavity (Jang, Para. [0034]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Ushiyama.
Regarding Claim 16, Jang in view of Ushiyama discloses the molding apparatus of claim 9.
Jang in view of Ushiyama does not disclose that the first contact pad is a ground pad.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to make the first contact pad in Ushiyama a ground pad. A ground pad is needed in nearly all chip packages, and provides a way to ground all the chips on the substrate through a wiring layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
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/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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