Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 12/31/2025 has been entered. Claims 1-5, 8-13, and 16 remain
pending in the application. Claims 6-7 and 14-15 are cancelled.
Response to Arguments
(add motivation to add second cavity from Jang – prevent encapsulant from spilling) Applicant's arguments filed 12/31/2025 have been fully considered but they are not persuasive.
Applicant’s main argument is that Examiner’s rationale for rejection Claim 7 as obvious was conclusory. Applicant contends that “examiner’s rationale to modify the prior art is based upon the statement that the claimed invention is within the ordinary skill of the art”.
Applicant secondarily argues that Jang discloses that “the first mold bottom surface 106 is placed flush against the solder mask 112”, which Applicant presumably interprets as prohibiting a second cavity.
Examiner disagrees with Applicant’s main argument for the following reasons:
First, Examiner did provide a rationale for modifying Jang. The rejection of Claim 7 states “it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to add a second cavity to the mold discloses by Jang for the purpose of providing the ability to add another board or chip the substrate, and to encapsulate that board or chip through a second cavity. Adding more chips or another board to the substrate would allow for the creation of a multi-chip module or stacked substrate, which can create more complex devices.” (Bold indicates the rationale). Hence, the rejection is not conclusory, but provides a justification for modifying Jang.
According to MPEP 2144 (I), “The rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law. In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988)” (Bold added for emphasis). In the present case, Examiner is relying on a rationale that would be generally available to one of ordinary skill in the art – namely, the motivation to add extra chips to the structure at hand.
Second, MPEP 2144.04 (VI)(B) supports a prima facie rejection of obviousness on the grounds that adding a second cavity is a duplication of parts. The prior art (Jang) has already presented a motivation for adding a first cavity – to prevent bleeding of the encapsulant from spilling over (Jang, Para. [0029]). As Examiner stated in the Non-Final Office Action, adding a second cavity would allow for another chip to placed on the board, and the cavity would prevent the encapsulation of that chip from spilling over, just like the first cavity did. Thus, the second cavity does not perform a new function (“…the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.” In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Examiner disagrees with Applicant’s second argument for the following reason:
As mentioned above, Applicant seems to be interpreting Jang as precluding the addition of a second cavity, since the first bottom surface 106 is placed flush against solder mask 112 (Para. [0029]). However, Examiner does not read Jang so narrowly. It is true, in Examiner’s view, that if one chip is to be encapsulated, that the first bottom surface is to be placed flush against the solder mask. However, in Examiner’s view, this is because Jang only discloses one chip being placed on the board. Examiner does not read Jang to mean that a second chip cannot be placed further away. If this is done, the first bottom surface can still be flush against the solder mask up to the second cavity. Examiner does not see any inconsistency here.
In conclusion, for the above reasons, Examiner is maintaining the rejections (modified based on the Applicant’s amendments).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over US20080150119A1 (Jang) in view of US20110057330A1 (Ushiyama).
Regarding Claim 1, Jang discloses a method for forming a semiconductor device (Fig. 8, el. 800, Para. [0065]), comprising: providing a package (Fig. 8, el. 802, Para. [0065]) comprising: a substrate (Fig. 1, el. 104, Para. [0021]); a solder resist layer (Fig. 1, el. 112, Para. [0024]) disposed on a top surface of the substrate (Fig. 1, Para. [0024]); an electronic component (Fig. 1, el. 108, Para. [0022]) mounted on the top surface of substrate (Para. [0023]); a first contact pad (Fig. 1, el. 114, Para. 0024]) disposed on the top surface of the substrate (Fig. 1) and exposed from the solder resist layer (Fig. 1); and
a second contact pad (Fig. 1, where there are multiple contact pads 114), and the first contact pad is between the electronic component and the second contact pad (Jang, Fig. 1, el. 114 that is to the right of the first contact pad closest to the chip 108); providing a mold (Fig. 8, el. 804, Para. [0065]; Fig. 1, el. 102, Para. [0021])) comprising: a first cavity (Fig. 1, el. 122, Para. [0026]) exposed from a bottom surface of the mold (Fig. 1); and a recess (Fig. 1, el. 126, Para. [0028]) formed adjacent to the first cavity (Fig. 1); engaging the mold and the package with the first cavity over the electronic component and the recess between the electronic component and the first contact pad (Fig. 8, el. 806, Para. [0065]); and injecting encapsulation material into the first cavity to form an encapsulant over the electronic component (Fig. 8, el. 808, Para. [0065]).
Jang does not disclose that the solder resist layer is a stress absorbing layer, and does not disclose that the mold further comprises a second cavity, and when the mold and the package are engaged, the second cavity is over the second contact pad.
Ushiyama discloses a package (Fig. 1, el. 1, Para. [0030]) with a substrate (Fig. 1, el. 10, Para. [0030) with a solder resist layer (Fig. 3, el. 13, Para. [0033]) on the top layer of the substrate (Fig. 3, Para. [0033]) where the solder resist layer has elastomer and is a stress absorbing layer (Para. [0038]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use the stress absorbing layer (solder resist and elastomer) disclosed by Ushiyama as a substitute for the solder resist layer of Jang. As disclosed by Ushiyama, doing so enables the solder resist layer to bear the strain caused by thermal deformation of the substrate and semiconductor element in the resin sealing step (Para. [0038]). Further, it would have been obvious to add a second cavity to the mold discloses by Jang for the purpose of providing the ability to add another board or chip the substrate, and to encapsulate that board or chip through a second cavity. Adding more chips or another board to the substrate would allow for the creation of a multi-chip module or stacked substrate, which can create more complex devices.
Regarding Claim 2, Jang in view of Ushiyama discloses the method of Claim 1, wherein the stress absorbing layer comprises solder resist (Ushiyama, Para. [0038]).
Regarding Claim 3, Jang in view of Ushiyama discloses method of Claim 1, wherein a thickness of the stress absorbing layer ranges from 20 um to 100 um (Ushiyama, Para. 0037]).
Regarding Claim 4, Jang in view of Ushiyama discloses the method of claim 1, wherein the bottom surface of the mold compresses the stress absorbing layer when the mold and the package are engaged (Jang, Para. [0031]).
Regarding Claim 5, Jang in view of Ushiyama discloses the method of claim 1, wherein the recess is formed around a perimeter of the first cavity (Jang, Para. [0034]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Ushiyama.
Regarding Claim 8, Jang in view of Ushiyama discloses the method of claim 7, wherein the second contact pad is a board-to-board pad (Para. [0024]).
Jang in view of Ushiyama does not disclose that the first contact pad is a ground pad.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to make the first contact pad in Ushiyama a ground pad. A ground pad is needed in nearly all chip packages, and provides a way to ground all the chips on the substrate through a wiring layer.
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Ushiyama.
Regarding Claim 9, Jang discloses a molding apparatus for forming an encapsulant on a package (Fig. 1, el. 102, Para. [0021]), comprising: a mold (Fig. 1, el. 102, Para. [0021]), wherein the mold comprising: a first cavity (Fig. 1, el. 122, Para. [0026]) exposed from a bottom surface of the mold (Fig. 1); and a recess (Fig. 1, el. 126, Para. [0028]) formed adjacent to the first cavity (Fig. 1); wherein the package comprises: a substrate (Fig. 1, el. 104, Para. [0021]); a solder resist layer (Fig. 1, el. 112, Para. [0024]) disposed on a top surface of the substrate (Fig. 1, Para. [0024]); an electronic component (Fig. 1, el. 108, Para. [0022]) mounted on the top surface of substrate (Para. [0023]); and a first contact pad (Fig. 1, el. 114, Para. 0024]) disposed on the top surface of the substrate (Fig. 1) and exposed from the solder resist layer (Fig. 1); and a second contact pad (Jang, Fig. 1, where there are multiple contact pads 114), and the first contact pad is between the electronic component and the second contact pad (Jang, Fig. 1, el. 114 that is to the right of the first contact pad closest to the chip 108); and wherein the mold is configured for engaging the package with the first cavity over the electronic component and the recess between the electronic component and the first contact pad (Fig. 8, el. 806, Para. [0065]); and encapsulation material can be injected into the first cavity to form an encapsulant over the electronic component (Fig. 8, el. 808, Para. [0065]).
Jang does not disclose that the solder resist layer is a stress absorbing layer, and does not disclose that the mold further comprises a second cavity, and when the mold and the package are engaged, the second cavity is over the second contact pad.
Ushiyama discloses a package (Fig. 1, el. 1, Para. [0030]) with a substrate (Fig. 1, el. 10, Para. [0030) with a solder resist layer (Fig. 3, el. 13, Para. [0033]) on the top layer of the substrate (Fig. 3, Para. [0033]) where the solder resist layer has elastomer and is a stress absorbing layer (Para. [0038]).
It would have been obvious to one skilled in the art before the effective filing date of the
claimed invention to use the stress absorbing layer (solder resist and elastomer) disclosed by Ushiyama as a substitute for the solder resist layer of Jang. As disclosed by Ushiyama, doing so enables the solder resist layer to bear the strain caused by thermal deformation of the substrate and semiconductor element in the resin sealing step (Para. [0038]). Further, it would have been obvious to add a second cavity to the mold discloses by Jang for the purpose of providing the ability to add another board or chip the substrate, and to encapsulate that board or chip through a second cavity. Adding more chips or another board to the substrate would allow for the creation of a multi-chip module or stacked substrate, which can create more complex devices.
Regarding Claim 10, Jang in view of Ushiyama discloses the molding apparatus of Claim 9, wherein the stress absorbing layer comprises solder resist (Ushiyama, Para. [0038]).
Regarding Claim 11, Jang in view of Ushiyama discloses the molding apparatus of Claim 9, wherein a thickness of the stress absorbing layer ranges from 20 um to 100 um (Ushiyama, Para. 0037]).
Regarding Claim 12, Jang in view of Ushiyama discloses the molding apparatus of claim 9, wherein the bottom surface of the mold compresses the stress absorbing layer when the mold and the package are engaged (Jang, Para. [0031]).
Regarding Claim 13, Jang in view of Ushiyama discloses the molding apparatus of claim 9, wherein the recess is formed around a perimeter of the first cavity (Jang, Para. [0034]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Ushiyama.
Regarding Claim 16, Jang in view of Ushiyama discloses the molding apparatus of claim 15, wherein the second contact pad is a board-to-board pad (Para. [0024]).
Jang in view of Ushiyama does not disclose that the first contact pad is a ground pad.
However, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to make the first contact pad in Ushiyama a ground pad. A ground pad is needed in nearly all chip packages, and provides a way to ground all the chips on the substrate through a wiring layer.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROHIT PARTHASARATHY whose telephone number is (571)272-2572. The examiner can normally be reached Monday-Friday 8:30a-5p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 5712707877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ROHIT PARTHASARATHY/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights