DETAILED ACTION
This Office action responds to the application filed on 06/05/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election with traverse of Species 4, reading on figures 1-8, 16-18, & 13a-c, in the reply filed on 12/22/2025 is acknowledged. The traversal is on the ground(s) that claims 10, 18, & 23 are generic to all species. This is not found persuasive because claims 10, 18, & 23 are method claims, and Species 5, reading on figures 19, 20, 21, & 23, shows configurations of integrated circuit packages and does not show any steps of forming such as depositing, planarizing, reflowing, bonding, etc. The requirement is still deemed proper and is therefore made final.
Applicant cancels claims 1-9, adds new claims 21-29, and elects claims 10-29. The applicant indicates that claims 10-29 read on the elected species. The examiner disagrees.
The limitations “a package substrate with conductive connectors” recited in Claim 23 reads on package substrate 200, in figure 20 of non-elected Species 5.
Although applicant elected claims 24-29, said claims depend on now-withdrawn claim 23, and as such is de facto withdrawn from examination by virtue of dependency to a withdrawn claim.
Accordingly, claims 1-9, and 23-29 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim.
Claims 10-22 will be examined in this Office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, 11, 12, 15 & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20190035767) in view of Zhou (US 20230282605).
Regarding Claim 10, Yu (see, e.g., fig. 3, fig. 4c) shows a method comprising:
forming microbumps 324, 332, & 334 on a first side of an integrated circuit die 200 (see, e.g., para.0020),
each of the microbumps including a conductive post 324 (see, e.g., para.0046) with a solder region 334 (see, e.g., para.0041) on the conductive post;
forming a first dielectric layer 342 (see, e.g., para.0044) on the first side of the integrated circuit die and at least laterally surrounding the microbumps;
forming a second dielectric layer 340 (see, e.g., para.0044) over the first dielectric layer and the solder bumps of the microbumps;
and bonding the first side of the integrated circuit die to conductive pads 312 (see, e.g., para.0046) of a wafer 302 (see, e.g., para.0015, para.0028) with the microbumps,
the solder bumps of the microbumps physically contacting the conductive pads of the wafer.
Yu, however, fails to show
planarizing the microbumps and the first dielectric layer;
reflowing the solder regions of the planarized microbumps,
the reflowing forming solder bumps on the conductive posts;
Zhou (see, e.g., figs. 2a-2d, para.0021-0022), in a similar method to Yu, teaches steps of planarizing the solder regions 204 and dielectric layer 206, then reflowing 204 to form solder bumps as spheres, would facilitate bonding connection and improve bond reliability.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the steps of Zhou in the method of Yu to facilitate bonding connection and improve bond reliability.
Regarding Claim 11, Yu (see, e.g., fig. 4c, para.0046), in view of Zhou, shows the method of claim 10,
wherein after bonding the first side of the integrated circuit die to conductive pads of the wafer with the microbumps,
the second dielectric layer 340 laterally surrounding each of the conductive pads 312 of the wafer (see, e.g., fig. 4c, para.0046).
Regarding 12, Yu (see, e.g., fig. 4c), in view of Zhou, shows the method of claim 11,
wherein after bonding the first side of the integrated circuit die to conductive pads of the wafer with the microbumps,
the second dielectric layer 340 laterally surrounding each of the solder bumps 334 of the microbumps (similar lateral surrounding as in claim 11, see, e.g., fig. 4c).
Regarding Claim 15, Yu (see, e.g., fig. 3, para.0029), in view of Zhou, shows the method of claim 10,
wherein bonding the first side of the integrated circuit die to conductive pads of a wafer with the microbumps comprises performing a thermocompression bonding process (thermal compression bond, see, e.g., para.0029).
Regarding Claim 16, Yu (see, e.g., fig. 4c), in view of Zhou, shows the method of claim 10,
wherein the second dielectric layer 340 is an adhesive, a flux, a non-conductive film, or a combination thereof (see, e.g., para.0044).
Claims 13 & 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20190035767) in view of Zhou (US 20230282605) and further in view of Williamson (20200251436).
Regarding Claim 13, Yu (see, e.g., fig. 4c), in view of Zhou, shows the method of claim 10,
Yu, in view of Zhou, however, fails to show
wherein after bonding the first side of the integrated circuit die to conductive pads of the wafer with the microbumps,
the solder bumps of the microbumps covers portions of sidewalls of the conductive pads of the wafer.
Williamson (see, e.g., fig. 5c, para.0040), in a similar method to Yu, in view of Zhou, teaches a configuration, wherein the solder bumps 511 of the microbumps covers portions of sidewalls of the conductive pads 504 of the wafer 502, would form reliable solder joints that prevent solder wicking and bridging.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Williamson in the method of Yu, in view of Zhou, to form reliable solder joints that prevent solder wicking and bridging.
Regarding Claim 14, Yu, in view of Zhou, shows method of claim 10,
Yu, in view of Zhou, however, fails to show
wherein after bonding the first side of the integrated circuit die to conductive pads of the wafer with the microbumps,
the solder bumps of the microbumps extend laterally into the second dielectric layer.
Williamson (see, e.g., fig. 5e, annotated figure 5e, para.0040), in a similar method to Yu, in view of Zhou, teaches a configuration, wherein the solder bumps 511 of the microbumps flow into the second dielectric layer 518 and fill the space between the pads 504 and the second dielectric layer, would form reliable solder joints that prevent solder wicking and bridging.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Williamson in the method of Yu, in view of Zhou, to form reliable solder joints that prevent solder wicking and bridging.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20190035767) in view of Zhou (US 20230282605) and further in view of Shah (US 20230201952).
Regarding Claim 17, Yu (see, e.g., fig. 4c), in view of Zhou, shows the method of claim 10,
Yu, in view of Zhou, however, fails to show
wherein the conductive pads of the wafer extend into the first dielectric layer.
Shah (see, e.g., fig. 14, para.0063-0065), in a similar method to Yu, in view of Zhou, teaches wherein the conductive pads of the wafer 1238 extend into the first dielectric layer 1212 above the bond interface would reduce the amount of thermal expansion required and allow for a lower bonding temperature.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the limitation of Shah in the method of Yu, in view of Zhou, to reduce the amount of thermal expansion required and allow for a lower bonding temperature.
Claims 18, 19, 20, 21, & 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20190035767) in view of Zhou (US 20230282605) and further in view of Kim (US 20230029098).
Regarding Claim 18, Yu (see, e.g., fig. 3, fig. 4c) shows method comprising:
forming microbumps 324, 332, & 334 on a first side of an integrated circuit die 200 (see, e.g., para.0020),
each of the microbumps including a conductive post 324 (see, e.g., para.0046) with a solder region 334 (see, e.g., para.0041) on the conductive post;
depositing a first dielectric layer 340 (see, e.g., para.0044) on the first side of the integrated circuit die,
and performing a thermocompression bonding process (see, e.g., para.0029, para.0041) to bond the microbumps of the integrated circuit die to conductive pads 312 (see, e.g., para.0046) of a wafer 302 (see, e.g., para.0015, para.0028),
the solder bumps of the microbumps physically contacting the conductive pads of the wafer,
Yu, however, fails to show
the first dielectric layer burying the solder regions of the microbumps;
grinding the first dielectric layer to expose the solder regions of the microbumps;
reflowing the solder regions of the microbumps,
the reflowing forming solder bumps on the conductive posts;
Zhou (see, e.g., figs. 2a-2d, para.0021-0022), in a similar method to Yu, teaches steps of burying solder regions 204 in dielectric layer 206, grinding the dielectric layer to expose the solder regions, then reflowing 204 to form solder bumps as spheres, would facilitate bonding connection and improve bond reliability.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the steps of Zhou in the method of Yu to facilitate bonding connection and improve bond reliability.
Yu, in view of Zhou, however, fails to show
forming a second dielectric layer over the first dielectric layer and the solder bumps of the microbumps;
the second dielectric layer covering the solder bumps at a start of the thermocompression bonding process.
Kim (see, e.g., figs. 7d-e, para.0043), in a similar method to Yu, in view of Zhou, teaches an additional dielectric layer NCF covering the solder bumps BS at the start of the thermocompression bonding process would improve uniform bonding adhesion and provide structural and electrical reliability.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the layer of Kim in the method of Yu, in view of Zhou, to improve uniform bonding adhesion and provide structural and electrical reliability.
Regarding Claim 19, Yu, in view of Zhou, and further in view of Kim (see, e.g., para.0035), shows the method of claim 18,
wherein the second dielectric layer is an adhesive, a flux, a non-conductive film, or a combination thereof.
Regarding Claim 20, Yu (see, e.g., fig. 4c, para.0045-0046), in view of Zhou, and further in view of Kim, shows the method of claim 18,
wherein the conductive pads 312 of the wafer extend into the first dielectric layer (see, e.g., para.0045).
Regarding Claim 21, Yu (see, e.g., fig. 4c, annotated figure 4c, para.0045-0046), in view of Zhou, and further in view of Kim, method of claim 18,
wherein after performing the thermocompression bonding process,
the second dielectric layer NCF laterally surrounds each of the conductive pads 312 of the wafer.
Kim (see, e.g., fig. 7f, para.0037) states the second dielectric layer NCF would fill the space between the solder and conductive pads.
Yu (see, e.g., fig. 4c, para.0042) states there to be a gap 336 in the area of bonding between the solder 334 and the conductive pads 312.
Thus, Yu, in view of Zhou, and further in view of Kim, would teach the second dielectric layer NCF laterally surrounding conductive pads 312 by filling in the gap space.
Regarding Claim 22, Yu (see, e.g., fig. 4c, annotated figure 4c), in view of Zhou, and further in view of Kim, shows the method of claim 18,
wherein after performing the thermocompression bonding process,
a top surface of the second dielectric layer NCF is below a top surface of one of the conductive pads 312 of the wafer (see, e.g., annotated figure 4c).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814