DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 05/13/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 05/13/2026 in reply to the non-final rejection mailed on 02/13/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. The restriction filed on 10/23/2025 has been withdrawn. Claims 23-29 have been rejoined.
Accordingly, pending in this Office action are claims 10-29.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-14 & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Williamson (US 20200251436) in view of Zhou (US 20230282605) & Kuo (US 20150348872) and further in view of Kim (US 20230029098).
Regarding Claim 10, Williamson (see, e.g., figs. 5a-d) shows a method comprising:
forming microbumps 508, 510, & 511 (see, e.g., para.0039) on a first side (bottommost surface) of an integrated circuit die 506 (see, e.g., para.0038),
each of the microbumps including a conductive post 508 with a solder region 510 & 511 on the conductive post (510 becomes 511 after solder reflow, see, e.g., para.0039-0040);
bonding the first side of the integrated circuit die to conductive pads 504 (see, e.g., para.0039) of a wafer 502 (package substrate 502 is interpreted as a wafer, see, e.g., para.0039) with the microbumps (see, e.g., fig. 5b),
the solder bumps 511 of the microbumps physically contacting the conductive pads of the wafer.
Williamson, however, fails to show,
forming a first dielectric layer on the first side of the integrated circuit die and at least laterally surrounding the microbumps;
planarizing the microbumps and the first dielectric layer;
reflowing the solder regions of the planarized microbumps, the reflowing forming solder bumps on the conductive posts;
forming a second dielectric layer over the first dielectric layer and the solder bumps of the microbumps;
and after forming the second dielectric layer over the first dielectric layer,
bonding the first side of the integrated circuit die to conductive pads of the wafer with the microbumps, the solder bumps of the microbumps physically contacting the conductive pads of the wafer (shown in Williamson but repeated to emphasize they do not occur after a step of forming the second dielectric layer over the first dielectric layer).
Zhou (see, e.g., figs. 2a-d, fig. 3, para.0023, para.0037) states semiconductor device 200 shown in fig. 3 is formed according to the embodiment of the method in figs. 2a-d. Therefore the combination of figs. 2a-2d & 3 is used.
Zhou (see, e.g., figs. 2a-d, fig. 3, para.0037), in a similar method to Williamson, shows
forming a first dielectric layer 206 (see, e.g., fig. 2b) on the first side of the integrated circuit die 200 (Zhou states semiconductor device 200 can be a die, see, e.g., para.0039) and at least laterally surrounding the microbumps 204 (Zhou states the solder bump 204 has the configuration of a nickel pillar capped with a solder alloy that is interpreted as a conductive post and solder region, see, e.g., para.0020);
planarizing the microbumps and the first dielectric layer (see, e.g., fig. 2c);
reflowing the solder regions of the microbumps, the reflowing forming solder bumps on the conductive posts (“reflow process can be conducted on solder bump 204 to form a solder ball…”, see, e.g., fig. 2d, para.0022);
Zhou (see, e.g., para.0022) states the step of forming a first dielectric layer 206 surrounding the microbumps 204 would provide better reliability as the first dielectric layer supports the reflowed solder bumps and the step of reflowing the solder regions of the microbumps 204 would facilitate bonding the microbumps to other conductive features (such as TSV 104 of semiconductor device 100, see, e.g., fig. 3).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the steps of Zhou in the method of Williamson to provide better reliability to the reflowed solder bump and to facilitate bonding the microbumps to other conductive features (see annotated figure 1).
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Williamson, in view of Zhou, however, fails to show
planarizing the microbumps
solder regions of the planarized microbumps
Kuo (see, e.g., fig. 4, para.00023-0025), in a similar method to Williamson, in view of Zhou, teaches
planarizing the microbumps 190 (see, e.g., para.0025)
The microbumps 204 of the die 200 of Williamson, in view of Zhou, are formed to connect TSVs 104 of the semiconductor device 100.
Kuo (para.0032) states the metal features 150, 170, & 190, interpreted as microbumps, of the semiconductor apparatus 100 are formed to connect to other interconnect structure and solder bumps. The microbumps of both devices serve the purpose of bonding connections to other devices.
The step of planarizing the microbumps of Kuo is incorporated into the method of Williamson, in view of Zhou after the step of planarizing the first dielectric layer 206 (see, e.g., fig. 2c) and prior to the step of reflowing the solder regions of the microbumps 204 (see, e.g., fig. 2d).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the step of Kuo in the method of Williamson, in view of Zhou, because the combination would prevent issues with bump height variation and overburden thickness that may increase manufacturing costs (see, e.g., Kuo, para.0025-0029); and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of one method of forming microbumps in a similar device for another for the purpose of forming bonding connections to other devices.
The combination of the step of planarizing the microbumps of Kuo, in the method of Williamson, in view of Zhou, would now teach the limitation “solder regions of the planarized microbumps,” since the microbumps are now planarized.
Williamson, in view of Zhou & Kuo, however, fails to show
forming a second dielectric layer over the first dielectric layer and the solder bumps of the microbumps;
and after forming the second dielectric layer over the first dielectric layer,
bonding the first side of the integrated circuit die to conductive pads of the wafer with the microbumps, the solder bumps of the microbumps physically contacting the conductive pads of the wafer.
Kim (see, e.g., figs. 7d-f, para.0035, para.0043), in a similar method to Williamson, in view of Zhou & Kuo, teaches a step of forming a dielectric layer NCF covering the solder bumps BS of die 200 prior to bonding the solder bumps to the conductive pads 160 of wafer 100 would ensure uniform bonding adhesion and provide structural and electrical reliability. After the dielectric layer NCF is formed, the solder bumps BS of the die 200 are bonded to the conductive pads of the wafer (see, e.g., fig. 7f).
Williamson (see, e.g., fig. 5c, para.0041) shows a similar underfill 512 that serves to provide mechanical support for bonding structures 511 to conductive pads 504 of the wafer.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the dielectric layer NCF of Kim in the method of Williamson, in view of Zhou & Kuo, because the combination ensures uniform bonding adhesion and provides structural and electrical reliability (see annotated figure 2); and because the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of one method of forming a dielectric layer in a similar device for another for the purpose of providing structural support for bonding connectors of semiconductor devices.
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Regarding Claim 11, Williamson, in view of Zhou & Kuo and further in view of Kim, shows the method of claim 10,
wherein after bonding the first side of the integrated circuit die to conductive pads 504 of the wafer 502 with the microbumps,
the second dielectric layer NCF laterally surrounding each of the conductive pads 504 of the wafer (see, e.g., annotated figure 2).
Regarding Claim 12, Williamson, in view of Zhou & Kuo and further in view of Kim, shows the method of claim 11,
wherein after bonding the first side of the integrated circuit die to conductive pads of the wafer with the microbumps,
the second dielectric layer NCF laterally surrounding each of the solder bumps 511 of the microbumps (see, e.g., annotated figure 2).
Regarding Claim 13, Williamson (see, e.g., fig. 5c), in view of Zhou & Kuo and further in view of Kim, shows the method of claim 10,
wherein after bonding the first side of the integrated circuit die to conductive pads of the wafer with the microbumps,
the solder bumps 511 of the microbumps covers portions of sidewalls of the conductive pads 504 of the wafer (see, e.g., fig. 5c).
Regarding Claim 14, Williamson (see, e.g., fig. 5c), in view of Zhou & Kuo and further in view of Kim, shows the method of claim 10,
wherein after bonding the first side of the integrated circuit die to conductive pads of the wafer with the microbumps,
the solder bumps 511 of the microbumps extend laterally into the second dielectric layer NCF (solder bumps 511 extending laterally after reflowing, see, e.g., fig. 5c, annotated figure 2).
Regarding Claim 16, Williamson, in view of Zhou & Kuo and further in view of Kim (see, e.g., para.0035), shows the method of claim 10,
wherein the second dielectric layer NCF is an adhesive, a flux, a non-conductive film, or a combination thereof (see, e.g., para.0035).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Williamson (US 20200251436) in view of Zhou (US 20230282605), Kuo (US 20150348872), & Kim (US 20230029098) and further in view of Yu (US 20190035767).
The references Zhou (US 20230282605), Kuo (US 20150348872), & Kim (US 20230029098) are hereinafter referred to as “Reference Group #1”.
Regarding Claim 15, Williamson, in view of Reference Group #1, shows the method of claim 10,
Williamson, in view of Reference Group #1, however, fails to show
wherein bonding the first side of the integrated circuit die to conductive pads of a wafer with the microbumps comprises performing a thermocompression bonding process.
Yu (see, e.g., fig. 3, para.0029), in a similar method to Williamson, in view of Reference Group #1, teaches that performing a thermocompression bonding process to bond pads and solder of dies would reduce bonding time and thermos-mechanical stress of the bonding joints at the bonding interface.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the thermocompression bonding process of Yu in the method of Williamson, in view of Reference Group #1, to reduce bonding time and thermos-mechanical stress of the bonding joints at the bonding interface.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Williamson (US 20200251436) in view of Reference Group #1 and further in view of Pogge (US 20060121690).
Regarding Claim 17, Williamson, in view of Reference Group #1, shows the method of claim 10,
Williamson, in view of Reference Group #1, however, fails to show
wherein the conductive pads of the wafer extend into the first dielectric layer.
Pogge (see, e.g., fig. 1e, para.0022, para.0029), in a similar method to Williamson, in view of Reference Group #1, teaches
wherein the conductive pads 27 of the wafer 2 extend above the surrounding dielectric layer 26
Pogge (see, e.g., para.0023) states the height of the conductive pads 27 extending above the surrounding dielectric layer 26 would accommodate for imprecision of alignment between wafers 1 & 2 and would ensure a reliable mechanical bond and a vertical electrical connection.
The height of the conductive pads 27 is incorporated into the method of Williamson, in view of Reference Group #1. The surrounding dielectric layer 26 corresponds to the position of the second dielectric layer NCF. Therefore, the combination would teach the conductive pads 504 of the wafer 502 extending into the first dielectric layer 206 above the second dielectric layer NCF, see annotated figure 3.
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It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the height of the conductive pads of Pogge, in the method of Williamson, in view of Reference Group #1, ensure a reliable mechanical bond and a vertical electrical connection.
Claims 18, 19, & 21 are rejected under 35 U.S.C. 103 as being unpatentable over Williamson (US 20200251436) in view of Zhou (US 20230282605) & Kim (US 20230029098) and further in view of Yu (US 20190035767).
Regarding Claim 18, Williamson (see, e.g., figs. 5a-d) shows a method comprising:
forming microbumps 508, 510, & 511 (see, e.g., para.0039) on a first side (bottommost surface) of an integrated circuit die 506 (see, e.g., para.0038),
each of the microbumps including a conductive post 508 with a solder region 510 & 511 on the conductive post (510 becomes 511 after solder reflow, see, e.g., para.0039-0040);
and performing a bonding process to bond the microbumps of the integrated circuit die to conductive pads of a wafer 502 (package substrate 502 is interpreted as a wafer, see, e.g., para.0039),
the solder bumps 511 of the microbumps physically contacting the conductive pads of the wafer 502 (see, e.g., fig. 5b),
Williamson, however, fails to show,
depositing a first dielectric layer on the first side of the integrated circuit die, the first dielectric layer burying the solder regions of the microbumps;
grinding the first dielectric layer to expose the solder regions of the microbumps;
reflowing the solder regions of the microbumps, the reflowing forming solder bumps on the conductive posts;
forming a second dielectric layer over the first dielectric layer and the solder bumps of the microbumps;
and performing a thermocompression bonding process to bond the microbumps of the integrated circuit die to the conductive pads of the wafer
the second dielectric layer covering the solder bumps at a start of the thermocompression bonding process.
Zhou (see, e.g., figs. 2a-d, fig. 3, para.0023, para.0037) states semiconductor device 200 shown in fig. 3 is formed according to the embodiment of the method in figs. 2a-d. Therefore the combination of figs. 2a-2d & 3 is used.
Zhou (see, e.g., figs. 2a-d, fig. 3, para.0037), in a similar method to Williamson, shows
depositing a first dielectric layer 206 (see, e.g., fig. 2b) on the first side of the integrated circuit die 200 (Zhou states semiconductor device 200 can be a die, see, e.g., para.0039), the first dielectric layer burying the solder regions of the microbumps 204 (Zhou states the solder bump 204 has the configuration of a nickel pillar capped with a solder alloy that is interpreted as a conductive posts and solder regions, see, e.g., para.0020, para.0023);
grinding the first dielectric layer first dielectric layer to expose the solder regions of the microbumps (see, e.g., fig. 2c, para.0021);
reflowing the solder regions of the microbumps, the reflowing forming solder bumps on the conductive posts (“reflow process can be conducted on solder bump 204 to form a solder ball…”, see, e.g., fig. 2d, para.0022);
Zhou (see, e.g., para.0022) states the step of forming a first dielectric layer 206 surrounding the microbumps 204 would provide better reliability as the first dielectric layer supports the reflowed solder bumps and the step of reflowing the solder regions of the microbumps 204 would facilitate bonding the microbumps to other conductive features (such as TSV 104 of semiconductor device 100, see, e.g., fig. 3).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the steps of Zhou in the method of Williamson to provide better reliability to the reflowed solder bump and to facilitate bonding the microbumps to other conductive features (see annotated figure 1).
Williamson, in view of Zhou, however, fails to show
forming a second dielectric layer over the first dielectric layer and the solder bumps of the microbumps;
Kim (see, e.g., figs. 7d-f, para.0035, para.0043), in a similar method to Williamson, in view of Zhou & Kuo, teaches a step of forming a dielectric layer NCF covering the solder bumps BS of die 200 prior to bonding the solder bumps to the conductive pads 160 of wafer 100 would ensure uniform bonding adhesion and provide structural and electrical reliability. After the dielectric layer NCF is formed, the solder bumps BS of the die 200 are bonded to the conductive pads of the wafer (see, e.g., fig. 7f).
Williamson (see, e.g., fig. 5c, para.0041) shows a similar underfill 512 that serves to provide mechanical support for bonding structures 511 to conductive pads 504 of the wafer.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the dielectric layer NCF of Kim in the method of Williamson, in view of Zhou, because the combination ensures uniform bonding adhesion and provides structural and electrical reliability (see annotated figure 2); and because the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of one method of forming a dielectric layer in a similar device for another for the purpose of providing structural support for bonding connectors of semiconductor devices.
Williamson, in view of Zhou & Kim, however, fails to show
and performing a thermocompression bonding process to bond the microbumps of the integrated circuit die to the conductive pads of the wafer
the second dielectric layer covering the solder bumps at a start of the thermocompression bonding process.
Yu (see, e.g., fig. 3, para.0029), in a similar method to Williamson, in view of Zhou & Kim, teaches that performing a thermocompression bonding process to bond pads and solder of dies would reduce bonding time and thermos-mechanical stress of the bonding joints at the bonding interface.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the thermocompression bonding process of Yu in the method of Williamson, in view of Zhou & Kim, to reduce bonding time and thermos-mechanical stress of the bonding joints at the bonding interface.
Annotated figure 2 of Williamson, in view of Zhou & Kim and further in view of Yu, shows the presence of the second dielectric layer NCF in fig. 5a prior to the start of the thermocompression bonding process.
Regarding Claim 19, Williamson, in view of Zhou & Kim (see, e.g., para.0035) and further in view of Yu, shows the method of claim 18,
wherein the second dielectric layer NCF an adhesive, a flux, a non-conductive film, or a combination thereof (see, e.g., para.0035).
Regarding Claim 21, Williamson, in view of Zhou & Kim and further in view of Yu, shows the method of claim 18,
wherein after performing the thermocompression bonding process,
the second dielectric layer NCF laterally surrounds each of the conductive pads 504 of the wafer 502 (see, e.g., annotated figure 2).
Claims 20 & 22 are rejected under 35 U.S.C. 103 as being unpatentable over Williamson (US 20200251436) in view of Zhou (US 20230282605), Kim (US 20230029098), & Yu (US 20190035767) and further in view of Pogge (US 20060121690).
The references Zhou (US 20230282605), Kim (US 20230029098) & Yu (US 20190035767) are hereinafter referred to as “Reference Group #2”.
Regarding Claim 20, Williamson, in view of Reference Group #2, shows the method of claim 18,
Williamson, in view of Reference Group #2, however, fails to show
wherein the conductive pads of the wafer extend into the first dielectric layer.
Pogge (see, e.g., fig. 1e, para.0022, para.0029), in a similar method to Williamson, in view of Reference Group #1, teaches
wherein the conductive pads 27 of the wafer 2 extend above the surrounding dielectric layer 26
Pogge (see, e.g., para.0023) states the height of the conductive pads 27 extending above the surrounding dielectric layer 26 would accommodate for imprecision of alignment between wafers 1 & 2 and would ensure a reliable mechanical bond and a vertical electrical connection.
The height of the conductive pads 27 is incorporated into the method of Williamson, in view of Reference Group #2. The surrounding dielectric layer 26 corresponds to the position of the second dielectric layer NCF. Therefore, the combination would teach the conductive pads 504 of the wafer 502 extending into the first dielectric layer 206 above the second dielectric layer NCF, see annotated figure 3.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the height of the conductive pads of Pogge, in the method of Williamson, in view of Reference Group #2, ensure a reliable mechanical bond and a vertical electrical connection.
Regarding Claim 22, Williamson, in view of in view of Reference Group #2, shows the method of claim 18,
Williamson, in view of Reference Group #2, however, fails to show
wherein after performing the thermocompression bonding process,
a top surface of the second dielectric layer is below a top surface of one of the conductive pads of the wafer.
Pogge (see, e.g., fig. 1e, para.0022, para.0029), in a similar method to Williamson, in view of Reference Group #1, teaches
wherein a top surface of the surrounding dielectric layer 26 is below a top surface of one of the conductive pads 27 of the wafer 2.
Pogge (see, e.g., para.0023) states the height of the conductive pads 27 extending above the surrounding dielectric layer 26 would accommodate for imprecision of alignment between wafers 1 & 2 and would ensure a reliable mechanical bond and a vertical electrical connection.
The height of the conductive pads 27 is incorporated into the method of Williamson, in view of Reference Group #2. The surrounding dielectric layer 26 corresponds to the position of the second dielectric layer NCF. Therefore, the combination would teach a top surface of the second dielectric layer NCF is below a top surface of one of the conductive pads 27 of the wafer 2, see annotated figure 4.
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It would have been obvious at the time of filing the invention to one of ordinary skill in the art to incorporate the height of the conductive pads of Pogge, in the method of Williamson, in view of Reference Group #2, ensure a reliable mechanical bond and a vertical electrical connection.
Claims 23, 24, 25, 27, 28, & 29 are rejected under 35 U.S.C. 103 as being unpatentable over Yu C (US 20240077669) in view of Zhou (US 20230282605), Kim (US 20230029098), & Yu (US 20190035767) and further in view of Pogge (US 20060121690).
Regarding Claim 23, Yu C (see, e.g., para.0038, para.0056) discloses fig. 1, fig. 5, & figs. 8-9 can be used together in combination as a single embodiment.
Yu C (see, e.g., fig. 1, fig. 5, figs. 8-9) shows a method comprising:
forming microbumps 56a & 56b on a first side 50F of an integrated circuit die 50 (see, e.g., fig. 1, para.0022),
each of the microbumps including a conductive post 56a (see, e.g., para.0023) with a solder region 56b (see, e.g., para.0024) on the conductive post;
reflowing the solder regions 56b of the microbumps (see, e.g., fig. 5),
the reflowing forming solder bumps 124 (see, e.g., para.0038) on the conductive posts;
performing a bonding process (see, e.g., fig. 5, para.0038) to bond the microbumps of the integrated circuit die to conductive pads 120a (see, e.g., para.0035) of a wafer 200 (see, e.g., fig. 5, para.0034),
the solder bumps 124 of the microbumps physically contacting the conductive pads 120a of the wafer,
and bonding the wafer to a package substrate 500 (see, e.g., para.0046) with conductive connectors 134 (see, e.g., figs. 8-9, para.0054).
Yu C, however, fails to show
depositing a first dielectric layer on the first side of the integrated circuit die,
the first dielectric layer burying the solder regions of the microbumps;
grinding the first dielectric layer to expose the solder regions of the microbumps;
forming a second dielectric layer over the first dielectric layer and the solder bumps of the microbumps;
performing a thermocompression bonding process to bond the microbumps of the integrated circuit die to conductive pads of a wafer,
the second dielectric layer covering the solder bumps at a start of the thermocompression bonding process,
wherein after the thermocompression bonding process,
a top surface of the second dielectric layer is below a top surface of at least one of the conductive pads of the wafer;
Zhou (see, e.g., figs. 2a-d, fig. 3, para.0023, para.0037) states semiconductor device 200 shown in fig. 3 is formed according to the embodiment of the method in figs. 2a-d. Therefore the combination of figs. 2a-2d & 3 is used.
Zhou (see, e.g., figs. 2a-d, fig. 3, para.0037), in a similar method to Yu C, shows
depositing a first dielectric layer 206 (see, e.g., fig. 2b) on the first side of the integrated circuit die 200 (Zhou states semiconductor device 200 can be a die, see, e.g., para.0039),
the first dielectric layer burying the solder regions of the microbumps 204 (Zhou states the solder bump 204 has the configuration of a nickel pillar capped with a solder alloy that is interpreted as a conductive post and solder region, see, e.g., para.0020);
grinding the first dielectric layer to expose the solder regions of the microbumps (see, e.g., fig. 2c, para.0021);
Zhou (see, e.g., para.0022) states the step of forming a first dielectric layer 206 surrounding the microbumps 204 would provide better reliability as the first dielectric layer supports the reflowed solder bumps to facilitate bonding the microbumps to other conductive features (such as TSV 104 of semiconductor device 100, see, e.g., fig. 3).
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the steps of Zhou in the method of Yu C to provide better reliability to the reflowed solder bump and to facilitate bonding the microbumps to other conductive features (see annotated figure 5).
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Yu C, in view of Zhou, however, fails to show
forming a second dielectric layer over the first dielectric layer and the solder bumps of the microbumps;
performing a thermocompression bonding process to bond the microbumps of the integrated circuit die to conductive pads of a wafer,
the second dielectric layer covering the solder bumps at a start of the thermocompression bonding process,
wherein after the thermocompression bonding process,
a top surface of the second dielectric layer is below a top surface of at least one of the conductive pads of the wafer;
Kim (see, e.g., figs. 7d-f, para.0035, para.0043), in a similar method to Yu C, in view of Zhou, teaches a step of forming a dielectric layer NCF covering the solder bumps BS of die 200 prior to bonding the solder bumps to the conductive pads 160 of wafer 100 would ensure uniform bonding adhesion and provide structural and electrical reliability. The dielectric layer NCF is formed and present at a start of the bonding between the solder bumps BS of the die 200 and the conductive pads 160 of the wafer (see, e.g., fig. 7f).
Yu C (see, e.g., fig. 5, para.0039) shows a similar underfill 126 that serves to provide mechanical support for bonding structures 56a & 124 to conductive pads 120a of the wafer 200.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the dielectric layer NCF of Kim in the method of Yu C, in view of Zhou, because the combination ensures uniform bonding adhesion and provides structural and electrical reliability (see annotated figure 6); and because the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of one method of forming a dielectric layer in a similar device for another for the purpose of providing structural support for bonding connectors of semiconductor devices.
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Yu C, in view of Zhou & Kim, however, fails to show
performing a thermocompression bonding process to bond the microbumps of the integrated circuit die to conductive pads of a wafer,
the second dielectric layer covering the solder bumps at a start of the thermocompression bonding process,
wherein after the thermocompression bonding process,
a top surface of the second dielectric layer is below a top surface of at least one of the conductive pads of the wafer;
Yu (see, e.g., fig. 3, para.0029), in a similar method to Yu C, in view of Zhou & Kim, teaches that performing a thermocompression bonding process to bond pads and solder of dies would reduce bonding time and thermos-mechanical stress of the bonding joints at the bonding interface.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the thermocompression bonding process of Yu in the method of Yu C, in view of Zhou & Kim, to reduce bonding time and thermos-mechanical stress of the bonding joints at the bonding interface.
Yu C, in view of Zhou, Kim, & Yu, however, fails to show
wherein after the thermocompression bonding process,
a top surface of the second dielectric layer is below a top surface of at least one of the conductive pads of the wafer;
Pogge (see, e.g., fig. 1e, para.0022, para.0029), in a similar method to Yu C, in view of Zhou, Kim, & Yu, teaches
wherein the conductive pads 27 of the wafer 2 extend above the surrounding dielectric layer 26
Pogge (see, e.g., para.0023) states the height of the conductive pads 27 extending above the surrounding dielectric layer 26 would accommodate for imprecision of alignment between wafers 1 & 2 and would ensure a reliable mechanical bond and a vertical electrical connection.
The height of the conductive pads 27 is incorporated into the method of Yu C, in view of Zhou, Kim, & Yu. The surrounding dielectric layer 26 corresponds to the position of the second dielectric layer NCF. Therefore, the combination would teach the conductive pads 120a of the wafer 200 extending into the first dielectric layer 206 above the second dielectric layer NCF, see annotated figure 7.
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Regarding Claim 24, Yu C, in view of Zhou, Kim (see, e.g., para.0035), & Yu and further in view of Pogge, shows the method of claim 23,
wherein the second dielectric layer is an adhesive, a flux, a non-conductive film, or a combination thereof (see, e.g., para.0035).
Regarding Claim 25, Yu C, in view of Zhou, Kim (see, e.g., fig. 7f), & Yu and further in view of Pogge, shows the method of claim 23,
wherein after the thermocompression bonding process,
the solder bumps 120a of the microbumps have protruding portions extending into the second dielectric layer NCF (as shown in Kim the solder bumps BS extending laterally after bonding , see, e.g., fig. 7f).
Regarding Claim 27, Yu C, in view of Zhou, Kim, & Yu and further in view of Pogge, shows the method of claim 23,
wherein after the thermocompression bonding process,
the conductive pads 120a of the wafer extend into the first dielectric layer 206 (see, e.g., annotated figure 7).
Regarding Claim 28, Yu C (see, e.g., fig. 9, para.0056), in view of Zhou, Kim, & Yu and further in view of Pogge, shows the method of claim 23, further comprising
forming an underfill 526 (see, e.g., fig. 9, para.0056) between the package substrate 500 and the wafer 200 (of package component 400),
the underfill surrounding the conductive connectors (see, e.g., fig. 9).
Regarding Claim 29, Yu C (see, e.g., fig. 7, para.0037), in view of Zhou, Kim, & Yu and further in view of Pogge, shows the method of claim 23,
wherein the integrated circuit die 50 is one of a plurality of integrated circuit dies 50, 60, & 70 (see, e.g., para.0037) bonded to the wafer,
the plurality of integrated circuit dies being laterally adjacent to one another (see, e.g., fig. 7).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Yu C (US 20240077669) in view of Zhou (US 20230282605), Kim (US 20230029098), Yu (US 20190035767), & Pogge (US 20060121690) and further in view of Williamson (US 20200251436).
Regarding Claim 26, Yu C, in view of Zhou, Kim, Yu, & Pogge, shows the method of claim 25,
Yu C, in view of Zhou, Kim, Yu, & Pogge, however, fails to show
wherein the protruding portions of the solder bumps 511 cover portions of sidewalls of the conductive pads 504 of the wafer (see, e.g., fig. 5c).
Williamson (see, e.g., fig. 5b, para.0040), in a similar method to Yu C, in view of Zhou, Kim, Yu, & Pogge, teaches
wherein the protruding portions of the solder bumps 511 cover portions of sidewalls of the conductive pads 504 of the wafer 502 (see, e.g., fig. 5b).
Williamson (see, e.g., para.0040) states the solder bumps 511b surrounding and covering the sidewalls of the conductive pads would cover a larger area of the conductive pad, form a reliable solder connection, and prevent solder wicking.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Williamson in the method of Yu C, in view of Zhou, Kim, Yu, & Pogge, to cover a larger area of the conductive pad, form a reliable solder connection, and prevent solder wicking.
Response to Arguments
Applicant’s arguments, see pages 6-8, filed 05/13/2026, with respect to the restriction filed on 10/23/2025 have been fully considered and are persuasive. The restriction has been withdrawn. Applicant’s arguments with respect to claim(s) 10-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record in the same manner for any teaching or matter specifically challenged in the argument.
Conclusion
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/F.R.D./ Examiner, Art Unit 2818
Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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