DETAILED ACTION
This action is responsive to the amendment received June 30, 2026. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “the storage container” in the last line of the claim, lacking antecedence.
Claims 6 and 7 each recite “a storage container”. A [storage] container is introduced in claim 1, making the number of required storage containers unclear. Claims 6 and 7 should recite “the storage container” after amending claim 1 to recite “a storage container”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Mori et al. (US 2021/0090954, of record) in view of Martens et al. (US 2013/0084659, of record), Arai et al. (US 2001/0004002, newly cited), and Chen et al. (US 2010/0166535, newly cited).
(Re Claim 1) Mori teaches a verification method for device chips, comprising:
a providing step of providing a wafer having a front surface with a plurality of devices formed thereon and demarcated by a plurality of intersecting streets (Figs. 3-5, 13-15: wafer 13, devices 23, streets 17) the devices including non-defective devices and defective devices that are distinguished from each other based on an electrical characteristic (Figs. 12-13 and ¶¶102-104); a dividing step of, after the providing step, dividing the wafer into individual device chips along the streets (Figs. 12, 15, dividing step S3); a defective device chip extracting step of extracting defective device chips from the individual device chips, the defective device chips corresponding to the defective devices and being defective in the electrical characteristic (¶108, step S4, Figs. 7A-7C, 12); and a verification step of verifying a physical characteristic of each of the extracted defective device chips (Fig. 11A-12, step S6 in S5, ¶¶109-110).
Mori is silent regarding a marking step of marking front surfaces of the defective devices and a storing step of storing the defective devices marked in the marking step in a container. A PHOSITA desiring to use and improve upon Mori’s process would be motivated to look to related art to teach possible modifications and improvements. Related art from Martens teaches marking the top surfaces of defective dies (¶35) so they can be easily identified for subsequent removal. In view of Martens, a PHOSITA would find it obvious to mark the top surfaces of the defective dies to make them easy to identify. Related art from Arai teaches storing bad dies in a storage container (tray) for subsequent processes (¶¶9,11,15). Related art from Chen also similarly teaches (¶¶5,11,21,30) storing bad dies in a storage container (bin 116) prior to subsequent processes. In view of the prior art, a PHOSITA would find it obvious to mark the bad dies to make them easier to identify, thereby enabling sorting based on visual/image data after testing, and to pick-and-place the bad dies into a storage container. Storing the bad dies in a container prevents them from moving down the manufacturing line, allows them to be collected and stored together. Storing small parts in a container is advantageous as this keeps the parts organized, the parts can be moved or transported in the container rather than individually, while preventing loss.
(Re Claim 3) wherein the wafer is positioned in an opening of an annular frame and is integrated with the annular frame via a dicing tape (Fig. 3: frame 21, tape 19).
(Re Claim 4) wherein the dividing step is performed by one of a cutting blade, a laser beam, plasma, dicing before grinding, or stealth dicing before grinding (¶¶105-106).
(Re Claim 7) further comprising a picking up step of picking up the defective devices from the wafer and storing the defective devices in a storage container (the combination of Mori, Arai, and Chen, as discussed above provide for picking the defective devices and storing them in a storage container).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Mori et al., Martens et al., Arai et al., and Chen et al., as applied above, and further in view of Aoki (US 2002/0092622), newly cited, and Davis et al. (US 5,976,306), newly cited.
(Re Claim 5) further comprising an imaging step of imaging the devices on the wafer and identifying and storing position information of the defective devices on the wafer; and (Re Claim 6) further comprising a picking up step of picking up the defective devices from the wafer based on the position information and storing the defective devices in a storage container.
Mori, Martens, Arai, and Chen are silent regarding an imaging step of imaging the devices on the wafer and identifying and storing position information of the defective devices on the wafer; and further comprising a picking up step of picking up the defective devices from the wafer based on the position information and storing the defective devices in a storage container. As discussed above, applying a mark to a defective device would be obvious as this makes the defective devices easy to visually identify in an image, the image is a wafer map showing the locations of the good and bad dies. Related art from Aoki teaches bad dies can be marked, imaged, and a map can be made of the locations of the good and bad dies for subsequent use in a pick and place operation (¶¶19-20, 27, 32, 36, 39). Related art from Davis similarly discloses bad dies can be marked, imaged, and a map can be made of the locations of the good and bad dies for subsequent use in a pick and place operation (col 5 lines 9-29 and col 6 lines 28-35). In view of the teachings of Davis and Aoki, once the dies are tested and marked, it would be obvious to a PHOSITA to perform imaging for the purpose of mapping the locations of the marked bad dies to facilitate subsequent picking operations. This step obviously requires storing the information for later use, e.g. at least in computer memory. Once the information is obtained, a PHOSITA would find itr obvious to use this in Mori’s subsequent picking/extracting step to quickly and easily locate the marked bad dies.
Allowable Subject Matter
Claim 2 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 2 recites the allowable subject matter “…further comprising: a determination step of determining based on results of the verification step whether or not to transfer non-defective device chips out of the individual device chips to a subsequent step, the non-defective device chips corresponding to the non-defective devices and being non-defective in the electrical characteristic”, as set forth in the claimed combination. This method step is not anticipated or rendered obvious by the prior art known to the Examiner.
Claims 8-13 are allowed.
Claim 8 recites the limitations of original claim 1 along with the allowable subject matter recited in original claim 2. See Non-Final Rejection mailed March 5, 2026, p. 3.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is cited on the PTO-892 attachment. The additional cited art teaches related die testing, marking, imaging, and picking processes.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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