DETAILED ACTION
This action is responsive to the application No. 18/328,988 filed on June 5, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mori et al. (US 2021/0090954), of record.
(Re Claim 1) Mori teaches a verification method for device chips, comprising:
a providing step of providing a wafer having a front surface with a plurality of devices formed thereon and demarcated by a plurality of intersecting streets (Figs. 3-5, 13-15: wafer 13, devices 23, streets 17) the devices including non-defective devices and defective devices that are distinguished from each other based on an electrical characteristic (Figs. 12-13 and ¶¶102-104); a dividing step of, after the providing step, dividing the wafer into individual device chips along the streets (Figs. 12, 15, dividing step S3); a defective device chip extracting step of extracting defective device chips from the individual device chips, the defective device chips corresponding to the defective devices and being defective in the electrical characteristic (¶108, step S4, Figs. 7A-7C, 12); and a verification step of verifying a physical characteristic of each of the extracted defective device chips (Fig. 11A-12, step S6 in S5, ¶¶109-110).
(Re Claim 3) wherein the wafer is positioned in an opening of an annular frame and is integrated with the annular frame via a dicing tape (Fig. 3: frame 21, tape 19).
(Re Claim 4) wherein the dividing step is performed by one of a cutting blade, a laser beam, plasma, dicing before grinding, or stealth dicing before grinding (¶¶105-106).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 recites the allowable subject matter “…further comprising: a determination step of determining based on results of the verification step whether or not to transfer non-defective device chips out of the individual device chips to a subsequent step, the non-defective device chips corresponding to the non-defective devices and being non-defective in the electrical characteristic”, as set forth in the claimed combination. This method step is not anticipated or rendered obvious by the prior art known to the Examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches related testing and pick and place processes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
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