DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsiung et al [US 2023/0047598]]
► With respect to claim 11, Hsiung et al (figs 1-10, text [0001]-[0078]) discloses the claimed method of forming semiconductor device comprising:
receiving a workpiece having a first metal gate stack (401/501, fig 6, text [0045]) ) over a first channel region, a second metal gate stack (401/501, fig 6, text [0045]) over a second channel region, a source/drain (S/D) feature (111, text [0019]) between the first and second channel regions, and an S/D contact (603, text [0052]) over the S/D feature;
forming first and second dielectric caps (503, SiON, fig 6, text [0050]-[0051]) covering and in direct contact with the first and second metal gate stacks, respectively;
forming a contact etch stop layer (CESL) (703, SiN, fig 7, text [0060]) over the S/D contact and over the first and second dielectric caps, wherein the CESL and the first and second dielectric caps are made of different materials;
forming an interlayer dielectric (ILD) (705, PSG, fig 7, text [0060]) layer over the CESL;
forming a gate via trench (707, fig 8) through the ILD layer, through the CESL, and through the first dielectric cap, the gate via trench exposes a top surface of the first metal gate stack;
forming a gate via (901, fig 9) in the gate via trench;
forming an S/D via trench ( opening fig 10, text [0070]) through the ILD layer and through the CESL, the S/D via trench exposes a top surface of the S/D contact and a side and a top surface of the gate via; and
forming an S/D via (1003, fig 10, text [0070]) in the S/D via trench, wherein the S/D via lands on the top surface of the S/D contact and the side and top surfaces of the gate via.
► With respect to claim 14, Hsiung et al (fig 6) discloses wherein the workpiece further includes a third metal gate stack (401/501) over a third channel region, a second S/D feature (111) adjacent the third channel region, and a second S/D contact (603) over the second S/D feature, the method further comprises: forming a third dielectric cap (503, fig 6) covering and in direct contact with the third metal gate stack; forming a second gate via trench (707, fig 8 ) through the ILD layer, through the CESL, and through the third dielectric cap, the second gate via trench exposes a top surface of the third metal gate stack; forming a second gate via (901, fig 9) in the second gate via trench; forming a second S/D via trench through the ILD layer and through the CESL (opening in fig 10 to form the second S/D via 1001, text [0070]), the second S/D via trench exposes a top surface of the second S/D contact; and forming a second S/D via (1001, fig 10) in the second via trench.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al [US 2020/0411378] in view of Hsiung et al [US 2022/0406653]
► With respect to claim 1, Huang et al (figs 1A-2Q, text [0001]-[0062]) discloses the claimed method of forming a semiconductor device, comprising:
receiving a workpiece having a first metal gate stack (119a, fig 2H, text [0022]) over a first channel region, a second metal gate stack (119b) over a second channel region, a source/drain (S/D) feature (112, text [0019]) between the first and second channel regions, and an S/D contact (142a, text [0033])over the S/D feature;
forming first and second dielectric caps (132a & 132b, fig 2H, text [0028]) over the first and second metal gate stacks, respectively;
forming a contact etch stop layer (CESL) (150, fig 2J, text [0035]) over the S/D contact and over the first and second dielectric caps, wherein the CESL is different from the first and second dielectric caps in composition;
forming an interlayer dielectric (ILD) layer (152, fig 2J, text [0036]) over the CESL;
performing a patterning process to form an S/D via trench (153, fig 2N, text [0046]-[0049]) through the ILD layer and through the CESL, wherein the patterning process includes a selective etching process using an etchant to selectively etch the CESL without substantially etching the first and second dielectric caps (text [0049]), and the S/D via trench fully exposes a top surface of the S/D contact and partially expose top surfaces of the first and second dielectric caps;
forming an S/D via in the S/D via trench, wherein the S/D via makes partially surface contact with the S/D contact and partial surface contact with the first and second dielectric caps.
Huang et al does not expressly teach the S/D makes fully surface contact with the S/D contact.
However, Hsiung et al (fig 6B, text [0001]-[0130]) teaches using the S/D via (134) make fully contact with the S/D contact (122).
Therefore, it would have been obvious for those skilled in the art to modify process of Huang et al by forming the S/D via making fully surface contact with the S/D contact as being claimed, per taught by Hsiung et al, to provide a better contact area between via and contact structures for better electrical connection in semiconductor device.
► With respect to claim 5, Huang et al (figs 2J-2N) discloses the patterning process further includes an ILD etching process (fig 2K), wherein the ILD etching process is performed before the selective etching process, and the ILD etching process uses an etchant that etches the ILD layer to exposes a top surface of the CESL.
► With respect to claim 6, Huang et al discloses the CESL (150, SiCN, text [0035]) includes carbon and the first and second dielectric caps(132a & 132b, ZrO2, text [0027}) are free of carbon.
► With respect to claim 7, Huang et al discloses the CESL is made of silicon carbonate (SiCO) or silicon carbonitride (SiCN). SiN is a well known material for dielectric caps. Selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301. See also In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960) (selection of a known plastic to make a container of a type made of plastics prior to the invention was held to be obvious). See Hsiung et al (text [0055]) as an evidence that shows SiN as a known material for dielectric cap 120.
► With respect to claim 8, the claimed parameter of etch selectivity is considered to involve routine optimization while has been held to be within the level of ordinary skill in the art. As noted in In re Aller 105 USPQ233, 255 (CCPA 1955)., the selection of reaction parameters such as temperature and concentration would have been obvious.
"Normally, it is to be expected that a change in temperature, or in concentration, or in both, would be an unpatentable modification. Under some circumstances, however, changes such as these may be impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed "critical ranges and the applicant has the burden of proving such criticality... More particularly, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."
See also In re Waite 77 USPQ 586 (CCPA 1948); In re Scherl 70 USPQ 204 (CCPA 1946); In re Irmscher 66 USPQ 314 (CCPA 1945); In re Norman 66 USPQ 308 (CCPA 1945); In re Swenson 56 USPQ 372 (CCPA 1942); In re Sola 25 USPQ 433 (CCPA 1935); In re Dreyfus 24 USPQ 52 (CCPA 1934).
► With respect to claim 9, Huang et al discloses forming gate spacers (113) along sidewalls of the first and second metal gate stacks, wherein the first and second dielectric caps are directly over the first and second metal gate stacks and the gate spacers, wherein the CESL (SiCO) and the gate spacers are made of different materials (text [0017])and the selective etching process selectively etches the CESL without substantially etching the gate spacers
► With respect to claim 10, Huang et al discloses forming dielectric layers (120, FSG, text [0019]) adjacent the gate spacers, wherein the dielectric layers surround the S/D contact, wherein the CESL (SiCO) and the dielectric layers (FSG) are made of different materials and the selective etching process selectively etches the CESL without substantially etching the dielectric layers.
Allowable Subject Matter
Claims 17-20 are allowed.
Claims 2-3, 12-13 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANHHA S PHAM whose telephone number is (571)272-1696. The examiner can normally be reached Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THANHHA S PHAM/Primary Examiner, Art Unit 2812