DETAILED ACTION
This Office action is in response to the Amendment filed on 02 December 2025. Claims 1-20 are pending in the application.
This application is a continuation of application Serial No. 16/926,528; filed on 10 July 2020, now US Patent 11,670,551; which claims priority to provisional application 62/906,291, filed on 26 September 2019.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Lee et al., US 2016/0056277, newly cited.
With respect to claim 1, Lee et al. disclose a semiconductor structure, shown in Fig. 7, comprising:
a first pair of fins 320 and a second pair of fins 320 disposed on a substrate 210/222/224, as shown in annotated Fig. 7 below;
an isolation feature 410 disposed around and between the first pair of fins 320 and second pair of fins 320, as shown in Fig. 4;
a silicon nitride liner 405 (see paragraph [0018]) disposed between the isolation feature 410 and surfaces of the first pair of fins 320 as well as between and the isolation feature 410 and surfaces of the second pair of fins 320, as shown in Fig. 4;
a first source/drain feature 310/515 disposed continuously extending over source/drain regions of the first pair of fins 320, as shown in Figs. 6 and 7; and
a second source/drain feature 310 disposed continuously extending over source/drain regions of the second pair of fins 320, as shown in Figs. 6 and 7,
wherein a bottommost surface of the first source/drain feature 310/515 is lower than a topmost surface of the isolation feature 410, as shown in Figs. 6 and 7.
With respect to claim 2, in the semiconductor device of Lee et al., the isolation feature 410 comprises silicon oxide or silicon oxynitride, see paragraph [0019].
With respect to claim 3, in the semiconductor device of Lee et al., the substrate comprises an n-type well and a p-type well (see paragraph [0011]), wherein a composition of lower portions 226 of the first pair of fins 320 is the same as a composition of the n-type well (Lee et al. teach that both the substrate 210 and the lower portions 226 can be silicon germanium, for example, see paragraphs [0009] and [0012].), and wherein a composition of lower portions 226 of the second pair of fins 320 is the same as a composition of the p-type well (Lee et al. teach that both the substrate 210 and the lower portions 226 can be silicon germanium, for example, see paragraphs [0009] and [0012].).
With respect to claim 4, in the semiconductor device of Lee et al., top portions 515 of the first pair of fins 320 comprise silicon germanium (see paragraph [0022]), wherein top portions 310 of the second pair of fins 320 comprise silicon (see paragraph [0015]).
With respect to claim 5, in the semiconductor device of Lee et al., a germanium content of the top portions 515 of the first pair of fins is between about 20% and about 80% (see paragraph [0022]).
With respect to claim 6, in the semiconductor device of Lee et al., the top portions 515 of the first pair of fins 320 are spaced apart from the lower portions 226 of the first pair of fins 320 by a semiconductor layer 310, wherein the semiconductor layer 310 comprises silicon (see paragraph [0015] and Fig. 7).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-16 are rejected under 35 U.S.C. 103 as being unpatentable over More et al., US 9,847,334, in view of Liu et al., US 2016/0190303, both cited by Applicant on the Information Disclosure Statement submitted on 05 June 2023, both of record, further in view of More et al., US 2019/0148551, hereinafter referred to as More et al. ‘551, newly cited.
With respect to claim 10, More et al. disclose a semiconductor structure, shown in Fig. 1G, comprising:
a substrate 102P/102N;
a first fin 126P (see Figs. 1D-1F) disposed on the substrate and comprising:
a first lower portion 100/104 comprising silicon and an n-type dopant (see column 3, lines 5-7, and 28-30),
a middle portion 114 over the first lower portion and comprising silicon (see column 4, lines 16-19), and
a first upper portion 102A/102B over the middle portion and comprising silicon germanium (see column 6, lines 19-24);
a second fin 126N (see Figs. 1D-1F) disposed on the substrate and comprising:
a second lower portion 100/106 comprising silicon and a p-type dopant (see column 3, lines 5-7, and 28-30), and
a second upper portion 108 over the second lower portion and comprising silicon (see column 4, lines 16-19);
a liner (STI liner, see column 11, line 66, bridging column 12 to line 4) along and in contact with sidewalls of the first lower portion of the first fin 126P and the second lower portion of the second fin 126N; and
a silicon cap layer 124 extending continuously along and in contact with a top surface of the first upper portion of the first fin 126P and a top surface of the second upper portion 108 of the second fin 126N, as shown in Fig. 1G..
Independent claim 10 has been amended to require a silicon cap layer extending continuously along and in contact with a top surface of the first upper portion of the first fin, sidewalls of the first upper portion of the first fin, sidewalls of the middle portion of the first fin, a top surface of the second upper portion of the second fin, and sidewalls of the second upper portion of the second fin. However, More et al. lack anticipation of the silicon cap layer 124 extending continuously along and in contact with sidewalls of the first upper portion 102A/102B of the first fin 126P and sidewalls of the second upper portion 108 of the second fin 126N. In the same field of endeavor, More et al. ‘551 disclose a silicon cap layer 400, shown in Fig. 4, that extends continuously and in contact with a top surface of the first upper portion of a first fin 210, sidewalls of the first upper portion of the first fin 210, sidewalls of the middle portion of the first fin 210, a top surface of the second upper portion of the second fin 210, and sidewalls of the second upper portion of the second fin 210. As shown in Fig. 4, the silicon cap layer 400 continuously extends and is in contact with the top surfaces and sidewall surfaces of all fins 210, so that an oxide layer can be grown thereon to form a silicon oxide gate dielectric, see paragraphs [0034]-[0035]. Since More et al. also disclose a silicon oxide gate dielectric, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the silicon cap layer 124 extending continuously along and in contact with a top surface of the first upper portion of the first fin 126P, sidewalls of the first upper portion 102A/102B of the first fin 126P, a top surface of the second upper portion 108 of the second fin 126N, and sidewalls of the second upper portion 108 of the second fin 126N in order to thermally grow a silicon oxide gate dielectric in the known semiconductor structure of More et al.
With respect to claims 10 and 11, although More et al. disclose a STI liner, More et al. do not disclose that the liner is a dielectric comprising silicon nitride. However, in a finFET, shown in Fig. 4, Liu et al. disclose disposing a dielectric liner 118 comprising silicon nitride between an isolation feature 120 and surfaces of a pair of fins in order to structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration. Liu et al. also teach that a silicon nitride liner is an effective barrier to oxygen, see paragraph [0010]. Since the fins in the known semiconductor structure of More et al contain a high germanium content, it would have been obvious to the skilled artisan to dispose a dielectric liner comprising silicon nitride along and in contact with sidewalls of the first lower portion of the first fin 126P and the second lower portion of the second fin 126N in the known semiconductor structure of More et al.
With respect to claim 12, the semiconductor structure of More et al. in view of Liu et al. further comprises: an isolation feature 131 surrounding the first lower portion of the first fin 126P and the second lower portion of the second fin 126N, as shown in Fig. 1G of More et al., wherein the isolation feature 131 would be spaced apart from the first lower portion and the second lower portion by the dielectric liner (silicon nitride liner), such as 118, shown in Fig. 4 of Liu et al., since the dielectric liner could be disposed prior to disposition of the isolation feature 131.
With respect to claim 13, it would have been obvious to the skilled artisan that the liner disclosed by More et al. would have spaced the isolation feature 131 apart from the substrate 102P/102N by the dielectric liner in light Fig. 4 of Liu et al., which clearly shows the silicon nitride dielectric liner 118 between the isolation feature 120 and the substrate 102.
With respect to claim 14, in the semiconductor structure of More et al., a germanium content of the top portions 120A/120B of the first pair of fins is between about 20% and about 80%, see column 7, lines 12-25.
With respect to claim 15, the semiconductor structure of More et al. further comprises: an interfacial layer 134P/134N disposed over the silicon cap layer 24 such that the interfacial layer 134P/134N is spaced apart from the first upper portion of the first fin 126P and the second upper portion of the second fin 126N by the silicon cap layer 24, as shown in Figs. 2 and 3. More et al. ‘551 disclose that the silicon cap layer 400 consists essentially of silicon, see paragraphs [0034]-[0035].
With respect to claim 16, in the semiconductor structure of More et al., the first upper portion 102A and 102B of the first fin 126P (see column 7, lines 40-59). More et al. do not expressly disclose that the second upper portion 108 of the second fin 126N are strained, however, since the second fin 126N is structurally identical to Applicant’s claimed second fin, it would have been obvious to the skilled artisan that the second fin in the known semiconductor structure of More et al. would be strained.
Claims 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over of Lee et al., US 2016/0056277, newly cited, in view of More et al., US 9,847,334, cited by Applicant on the Information Disclosure Statement submitted on 05 June 2023, of record.
With respect to claim 17, Lee et al. disclose a semiconductor structure, shown in Fig. 7, comprising:
a first pair of fins 320 and a second pair of fins 320 disposed on a substrate 210/222/224, as shown in annotated Fig. 7 below;
an isolation feature 410 disposed around and between the first pair of fins 320 and second pair of fins 320, as shown in Fig. 4;
a silicon nitride liner 405 (see paragraph [0018]) disposed between the isolation feature 410 and surfaces of the first pair of fins 320 as well as between and the isolation feature 410 and surfaces of the second pair of fins 320, as shown in Fig. 4;
a first source/drain feature 310/515 continuously extending over source/drain regions of the first pair of fins 320, as shown in Figs. 6 and 7; and
a second source/drain feature 310 continuously extending over source/drain regions of the second pair of fins 320, as shown in Figs. 6 and 7,
wherein the first pair of fins 320 comprise silicon (see paragraphs [0015] and [0022]),
wherein the second pair of fins 320 comprise silicon (see paragraph [0015]).
wherein a bottommost surface of the first source/drain feature 310/515 is lower than a topmost surface of the isolation feature 410, as shown in Figs. 6 and 7.
Lee et al. lack anticipation only of the first pair of fins 320 comprising an n-type dopant and the second pair of fins 320 comprising a p-type dopant. However, Lee et al. disclose that the disclosed device can be a FinFET device, and the FinFET device may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device, see paragraph [0007]. In the same field of endeavor, More et al. discloses a semiconductor device, shown in Fig. 1G, comprising a first pair of fins 126P and a second pair of fins 126N disposed on a substrate 102P/102N; wherein the first pair of fins 126P comprise silicon and an n-type dopant (see Figs. 1D-1F and column 3, lines 5-7 and 28-30) for forming a PMOS FinFET, and wherein the second pair of fins 128N comprises silicon and a p-type dopant (see Figs. 1D-1F and column 3, lines 5-7 and 28-30) for forming an NMOS FinFET. In light of the disclosure of More et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first pair of fins 320 could comprise an n-type dopant and the second pair of fins 320 could comprise a p-type dopant in the known semiconductor structure of Lee et al. in order to fabricate a CMOS FinFET.
With respect to claim 19, in the semiconductor structure of Lee et al., the first source/drain feature 310/515 comprises silicon germanium 515 (see paragraph [0022], and the second source/drain feature 310 comprises silicon (see paragraph [0015], however, Lee et al. fail to teach or suggest that the first source/drain feature 310/515 includes a p-type dopant and the second source/drain feature includes an n-type dopant. However, Lee et al. disclose that the disclosed device can be a FinFET device, and the FinFET device may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device, see paragraph [0007]. In the same field of endeavor, More et al. discloses a semiconductor device, shown in Fig. 1G, comprising a first pair of fins 126P and a second pair of fins 126N disposed on a substrate 102P/102N. In the semiconductor structure of More et al., the first source/drain feature comprises silicon germanium 102A and 102B and a p-type dopant, wherein the second source/drain feature comprises silicon 108 and an n-type dopant, see Figs. 2 and 3 and column 13, lines 48-60. In light of the disclosure of More et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first source/drain feature 310/515 could include a p-type dopant and the second source/drain feature 310 could include an n-type dopant in the known semiconductor structure of Lee et al. in order to fabricate a CMOS FinFET.
With respect to claim 20, in the semiconductor structure of Lee et al., the first source/drain feature 310/515 is in contact with top surfaces of the first pair of fins 320, wherein the second source/drain feature 310 is in contact with top surfaces of the second pair of fins 320, as shown in Fig. 7.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over of Lee et al., US 2016/0056277, newly cited, as applied to claim 1 above, further in view of More et al., US 2019/0148551, hereinafter referred to as More et al. ‘551, newly cited.
Dependent claim 7 requires a first silicon cap layer disposed directly on sidewalls and top surfaces of the top portions of the first pair of fins in channel regions of the first pair of fins; and a second silicon cap layer disposed directly on sidewalls and top surfaces of the top portions of the second paid of fins in channel regions of the second pair of fins. However, Lee et al. fails to disclose the claimed silicon cap layer. In the same field of endeavor, More et al. ‘551 disclose a silicon cap layer 400, shown in Fig. 4, that is disposed directly on sidewalls and top surfaces of the top portions of the first pair of fins 210 in channel regions of the first pair of fins; and a second silicon cap layer 400 disposed directly on sidewalls and top surfaces of the top portions of the second paid of fins 210 in channel regions of the second pair of fins. As shown in Fig. 4 of More et al. ‘551, the silicon cap layer 400 is disposed directly on sidewalls and top surfaces of each fin 210, see paragraphs [0034]-[0035]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first silicon cap layer disposed directly on sidewalls and top surfaces of the top portions of the first pair of fins in channel regions of the first pair of fins; and a second silicon cap layer disposed directly on sidewalls and top surfaces of the top portions of the second paid of fins in channel regions of the second pair of fins in the known structure of Lee et al. in order to thermally grow a silicon oxide gate dielectric over the fins.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over of Lee et al., US 2016/0056277, newly cited, as applied to claim 1 above, further in view of More et al., US 9,847,334, cited by Applicant on the Information Disclosure Statement submitted on 05 June 2023, of record.
In the semiconductor structure of Lee et al., the first source/drain feature 310/515 comprises silicon germanium 515 (see paragraph [0022], and the second source/drain feature 310 comprises silicon (see paragraph [0015], however, Lee et al. fail to teach or suggest that the first source/drain feature 310/515 includes a p-type dopant and the second source/drain feature includes an n-type dopant. However, Lee et al. disclose that the disclosed device can be a FinFET device, and the FinFET device may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device, see paragraph [0007]. In the same field of endeavor, More et al. discloses a semiconductor device, shown in Fig. 1G, comprising a first pair of fins 126P and a second pair of fins 126N disposed on a substrate 102P/102N. In the semiconductor structure of More et al., the first source/drain feature comprises silicon germanium 102A and 102B and a p-type dopant, wherein the second source/drain feature comprises silicon 108 and an n-type dopant, see Figs. 2 and 3 and column 13, lines 48-60. In light of the disclosure of More et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first source/drain feature 310/515 could include a p-type dopant and the second source/drain feature 310 could include an n-type dopant in the known semiconductor structure of Lee et al. in order to fabricate a CMOS FinFET.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over of Lee et al., US 2016/0056277, newly cited, as applied to claim 1 above, further in view of Liu et al., US 2016/0190303, cited by Applicant on the Information Disclosure Statement submitted on 05 June 2023, of record.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over of Lee et al., US 2016/0056277, newly cited, in view of More et al., US 9,847,334, cited by Applicant on the Information Disclosure Statement submitted on 05 June 2023, of record, as applied to claim 17 above, further in view of Liu et al., US 2016/0190303, cited by Applicant on the Information Disclosure Statement submitted on 05 June 2023, of record.
Lee et al. is applied as above. However, Lee et al. lack anticipation of the silicon nitride liner 405 having a thickness between about 0.5 nm to about 3 nm, as required in dependent claims 9 and 18. In the FinFET shown in Fig. 4, Liu et al. disclose disposing a dielectric liner 118 comprising silicon nitride between an isolation feature 120 and surfaces of a pair of fins in order to provide structural stability for fins. Liu et al. further disclose that if the silicon nitride liner 118 has a thickness of less than 5 nm, the silicon nitride liner is effective as an oxygen barrier, see paragraph [0010]. In light of this teaching of Liu et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention. that the silicon nitride liner 405 in the known semiconductor structure of Lee et al. could have a thickness in the range of about 0.5 nm to about 3 nm to provide structural stability and be an effective barrier to oxygen.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot in light of the new grounds of rejection. The newly-cited reference to Lee et al., US 2016/0056277 clearly discloses a bottommost surface of the first source/drain feature is lower than a topmost surface of the isolation feature, as required in independent claims 1 and 17. The newly-cited reference to More et al., US 2019/0148551, teaches that a silicon cap layer can be formed continuously along the sidewall and top surfaces of fins, as required in amended independent claim 10.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898