DETAILED ACTION
This Office action is in response to the Request for Continued Examination (RCE) filed on 18 May 2026. Claims 1-19 and 21 are pending in the application. Claim 20 has been cancelled. Claim 21 is newly submitted.
This application is a continuation of application Serial No. 16/926,528; filed on 10 July 2020, now US Patent 11,670,551; which claims priority to provisional application 62/906,291, filed on 26 September 2019.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11 May 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Lee et al., US 2016/0056277, of record.
With respect to claim 1, Lee et al. disclose a semiconductor structure, shown in Fig. 7, comprising:
a first pair of fins 520 and a second pair of fins 320 disposed on a substrate 210/222/224, as shown in annotated Fig. 7 below;
an isolation feature 410 disposed around and between the first pair of fins 320 and second pair of fins 320, as shown in Fig. 4;
a silicon nitride liner 405 (see paragraph [0018]) disposed between the isolation feature 410 and surfaces of the first pair of fins 320 as well as between and the isolation feature 410 and surfaces of the second pair of fins 320, as shown in Fig. 4;
a first source/drain feature 226/310/515 disposed continuously extending over source/drain regions of the first pair of fins 320, as shown in Figs. 6 and 7; and
a second source/drain feature 226/310 disposed continuously extending over source/drain regions of the second pair of fins 320, as shown in Figs. 6 and 7,
wherein a bottommost surface of the first source/drain feature (bottommost surface of 226) is lower than a topmost surface of the isolation feature 410, as shown in Figs. 6 and 7;
wherein the first pair of fins 520 (see annotated Fig. 7 below) each comprise a first bottom portion 226, a middle portion 310 on the first bottom portion 226, and a first top portion 515 on the middle portion 310, wherein the first top portion 515, the middle portion 310, and the first bottom portion 226 have different compositions (See paragraphs [0022], [0015], and [0012]: the first top portion 515 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, the middle portion 310 may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, and the first bottom portion 226 may include SiGe, InAlAs, InP, AlGaAs, GaAs, GaAsP; therefore, the first top portion 515 could be Si, the middle portion 310 could be AlGaAs, and the first bottom portion 226 could be SiGe, for example.).
With respect to claim 2, in the semiconductor device of Lee et al., the isolation feature 410 comprises silicon oxide or silicon oxynitride, see paragraph [0019].
With respect to claim 3, in the semiconductor device of Lee et al., the substrate comprises an n-type well and a p-type well (see paragraph [0011]), wherein a composition of the first bottom portions 226 of the first pair of fins 520 is the same as a composition of the n-type well (Lee et al. teach that both the substrate 210 and the lower portions 226 can be silicon germanium, for example, see paragraphs [0009] and [0012].), and wherein a composition of second bottom portions 226 of the second pair of fins 320 is the same as a composition of the p-type well (Lee et al. teach that both the substrate 210 and the lower portions 226 can be silicon germanium, for example, see paragraphs [0009] and [0012].).
With respect to claim 4, in the semiconductor device of Lee et al., the first top portions 515 of the first pair of fins 520 can comprise silicon germanium (see paragraph [0022]), wherein second top portions 310 of the second pair of fins 320 comprise silicon (see paragraph [0015]).
With respect to claim 5, in the semiconductor device of Lee et al., a germanium content of the first top portions 515 of the first pair of fins 520 is between about 20% and about 80% (see paragraph [0022]).
With respect to claim 6, in the semiconductor device of Lee et al., the middle portion 310 of the first pair of fins 520 comprise silicon (see paragraph [0015] and Fig. 7).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-16 are rejected under 35 U.S.C. 103 as being unpatentable over More et al., US 9,847,334, cited by Applicant on the Information Disclosure Statement (IDS) submitted on 05 June 2023, of record, further in view of Ching et al., US 2018/0366465, newly cited.
With respect to claim 10, More et al. disclose a semiconductor structure, shown in Fig. 1G, comprising:
a substrate 102P/102N;
a first fin 126P (see Figs. 1D-1F) disposed on the substrate and comprising:
a first lower portion 100/104 comprising silicon and an n-type dopant (see column 3, lines 5-7, and 28-30),
a middle portion 114/116 over the first lower portion and comprising silicon (see Fig. 1D; column 4, lines 16-19; and column 5, lines 4-14), and
a first upper portion 102A/102B over the middle portion 114/116 and comprising silicon germanium (see column 6, lines 19-24), wherein the middle portion 114/116 (comprising silicon/silicon carbide) and the first upper portion 102A/102B (comprising silicon germanium) have different compositions;
a second fin 126N (see Figs. 1D-1F) disposed on the substrate and comprising:
a second lower portion 100/106 comprising silicon and a p-type dopant (see column 3, lines 5-7, and 28-30), and
a second upper portion 108 over the second lower portion and comprising silicon (see column 4, lines 16-19), as shown in Fig. 1F.
Independent claim 10 requires a dielectric liner along and in contact with sidewalls of the first lower portion of the first fin and the second lower portion of the second fin; and a silicon cap layer extending continuously along and in contact with a top surface of the first upper portion of the first fin, sidewalls of the first upper portion of the first fin, sidewalls of the middle portion of the first fin, a top surface of the second upper portion of the second fin, and sidewalls of the second upper portion of the second fins wherein the dielectric liner contacts the silicon cap layer. Admittedly, More et al. disclose a liner (STI liner, see column 11, line 66, bridging column 12 to line 4) along and in contact with sidewalls of the first lower portion of the first fin 126P and the second lower portion of the second fin 126N. In the same field of endeavor, Ching et al. disclose a dielectric liner 122/124 (layer 124 is a nitride layer, see paragraph [0023]) along and in contact with sidewalls of a first lower portion 104 of a first fin and a second lower portion 102 of a second fin, see Fig. 1B of Ching et al.; and a silicon cap layer 142 (see paragraph [0022]) extending continuously along and in contact with a top surface of a first upper portion 108 of the first fin, sidewalls of the first upper portion 108 of the first fin, sidewalls of the middle portion 108a of the first fin, a top surface of the second upper portion 106 of the second fin, and sidewalls of the second upper portion 106 of the second fins, as shown in Fig. 1B, wherein the dielectric liner 142 contacts the silicon cap layer 142, as shown in Fig. 1B of Ching et al. Ching et al. disclose this configuration prevents leakage problems from occurring in the FinFET and providing good FinFET performance, see paragraph [0022]. In light of the advantages associated with the liner 122/124 and silicon cap layer 142 of Ching et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a dielectric liner along and in contact with sidewalls of the first lower portion of the first fin 126P and the second lower portion of the second fin 126N; and to provide a silicon cap layer extending continuously along and in contact with a top surface of the first upper portion 100/104 of the first fin 126P, sidewalls of the first upper portion 102A/102B of the first fin 126P, sidewalls of the middle portion 114/116 of the first fin, a top surface of the second upper portion 108 of the second fin 126N, and sidewalls of the second upper portion 108 of the second fin 126N, wherein the dielectric liner contacts the silicon cap layer in the known device of More et al. in order to prevent leakage from occurring in the device of More et al.
With respect to claim 11, Ching et al. disclose the dielectric liner comprises silicon nitride, see paragraph [0023].
With respect to claim 12, More et al. disclose an isolation feature 131 and an STI liner, however, the STI liner is not shown in the figures of More et al. However, the combination of More et al. and Ching et al. disclose an isolation feature 126 surrounding the first lower portion of the first fin and the second lower portion of the second fin, wherein the isolation feature 126 is spaced apart from the first lower portion and the second lower portion by the dielectric liner 122/124, as shown in Fig. 1B of Ching et al., see paragraph [0021].
With respect to claim 13, the combination of More et al. and Ching et al. disclose the isolation feature 126 is spaced apart from the substrate 100 by the dielectric liner 122/124, as shown in Fig. 1B of Ching et al..
With respect to claim 14, in the semiconductor structure of More et al., a germanium content of the top portions 120A/120B of the first pair of fins 520 is between about 20% and about 80%, see column 7, lines 12-25.
With respect to claim 15, the semiconductor structure of More et al. further comprises: an interfacial layer 134P/134N disposed over the silicon cap layer 24 such that the interfacial layer 134P/134N is spaced apart from the first upper portion of the first fin 126P and the second upper portion of the second fin 126N by the silicon cap layer 24, as shown in Figs. 2 and 3. More et al. ‘551 disclose that the silicon cap layer 400 consists essentially of silicon, see paragraphs [0034]-[0035].
With respect to claim 16, in the semiconductor structure of More et al., the first upper portion 102A and 102B of the first fin 126P (see column 7, lines 40-59). More et al. do not expressly disclose that the second upper portion 108 of the second fin 126N are strained, however, since the second fin 126N is structurally identical to Applicant’s claimed second fin, it would have been obvious to the skilled artisan that the second fin in the known semiconductor structure of More et al. would be strained.
Claims 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over of Lee et al., US 2016/0056277, in view of More et al., US 9,847,334, cited by Applicant on the Information Disclosure Statement submitted on 05 June 2023, of record.
With respect to claim 17, Lee et al. disclose a semiconductor structure, shown in Fig. 7, comprising:
a first pair of fins 520 and a second pair of fins 320 disposed on a substrate 210/222/224, as shown in annotated Fig. 7 below;
an isolation feature 410 disposed around and between the first pair of fins 520 and second pair of fins 320, as shown in Fig. 4;
a silicon nitride liner 405 (see paragraph [0018]) disposed between the isolation feature 410 and surfaces of the first pair of fins 520 as well as between and the isolation feature 410 and surfaces of the second pair of fins 320, as shown in Fig. 4;
a first source/drain feature 310/515 continuously extending over source/drain regions of the first pair of fins 520, as shown in Figs. 6 and 7; and
a second source/drain feature 310 continuously extending over source/drain regions of the second pair of fins 320, as shown in Figs. 6 and 7,
wherein the first pair of fins 520 comprise a bottom layer 226 comprising silicon (see paragraph [0012]), a middle layer 310 on the bottom layer 225, and a top layer 515on the middle layer 310, as shown in Fig. 7,
wherein the top layer 515 and the middle layer 310 are different in composition from the bottom layer 226, see paragraphs [0015] and [0022]: middle layer 310 can be GaAs and top layer 515 can be Ge, for example),
wherein the first source/drain feature 310/515 is on the bottom layers 226 of the first pair of fins 520;
wherein the second pair of fins 320 comprise silicon (see paragraph [0015]).
wherein a bottommost surface of the first source/drain feature 310/515 is lower than a topmost surface of the isolation feature 410, as shown in Figs. 6 and 7.
Lee et al. lack anticipation only of the first pair of fins 520 comprising an n-type dopant and the second pair of fins 320 comprising a p-type dopant. However, Lee et al. disclose that the disclosed device can be a FinFET device, and the FinFET device may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device, see paragraph [0007]. In the same field of endeavor, More et al. discloses a semiconductor device, shown in Fig. 1G, comprising a first pair of fins 126P and a second pair of fins 126N disposed on a substrate 102P/102N; wherein the first pair of fins 126P comprise silicon and an n-type dopant (see Figs. 1D-1F and column 3, lines 5-7 and 28-30) for forming a PMOS FinFET, and wherein the second pair of fins 128N comprises silicon and a p-type dopant (see Figs. 1D-1F and column 3, lines 5-7 and 28-30) for forming an NMOS FinFET. In light of the disclosure of More et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first pair of fins 320 could comprise an n-type dopant and the second pair of fins 320 could comprise a p-type dopant in the known semiconductor structure of Lee et al. in order to fabricate a CMOS FinFET.
With respect to claim 19, in the semiconductor structure of Lee et al., the first source/drain feature 310/515 comprises silicon germanium 515 (see paragraph [0022], and the second source/drain feature 310 comprises silicon (see paragraph [0015], however, Lee et al. fail to teach or suggest that the first source/drain feature 310/515 includes a p-type dopant and the second source/drain feature includes an n-type dopant. However, Lee et al. disclose that the disclosed device can be a FinFET device, and the FinFET device may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device, see paragraph [0007]. In the same field of endeavor, More et al. discloses a semiconductor device, shown in Fig. 1G, comprising a first pair of fins 126P and a second pair of fins 126N disposed on a substrate 102P/102N. In the semiconductor structure of More et al., the first source/drain feature comprises silicon germanium 102A and 102B and a p-type dopant, wherein the second source/drain feature comprises silicon 108 and an n-type dopant, see Figs. 2 and 3 and column 13, lines 48-60. In light of the disclosure of More et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first source/drain feature 310/515 could include a p-type dopant and the second source/drain feature 310 could include an n-type dopant in the known semiconductor structure of Lee et al. in order to fabricate a CMOS FinFET.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over of Lee et al., US 2016/0056277, as applied to claim 1 above, further in view of Ching et al., US 2018/0366465. newly cited.
Lee et al. is applied as above. Dependent claim 7 requires a first silicon cap layer disposed directly on sidewalls and top surfaces of the top portions of the first pair of fins in channel regions of the first pair of fins; and a second silicon cap layer disposed directly on sidewalls and top surfaces of the top portions of the second paid of fins in channel regions of the second pair of fins. However, Lee et al. fail to disclose the claimed silicon cap layer. In the same field of endeavor, Ching et al. disclose a first silicon cap layer 242 (see paragraph [0030]) disposed directly on sidewalls and top surfaces of the top portions of the first pair of fins in channel regions of the first pair of fins 204; and a second silicon cap layer 242 (see paragraph [0030]) disposed directly on sidewalls and top surfaces of the top portions of the second paid of fins in channel regions of the second pair of fins 202, as shown in Fig. 2L of Ching et al. Ching et al. disclose this configuration prevents leakage problems from occurring in the FinFET and provides good FinFET performance, see paragraph [0022]. In light of the advantages associated with the silicon cap layer 242 of Ching et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first silicon cap layer 242 disposed directly on sidewalls and top surfaces of the top portions of the first pair of fins 520 in channel regions of the first pair of fins; and a second silicon cap layer 242 disposed directly on sidewalls and top surfaces of the top portions of the second paid of fins 320 in channel regions of the second pair of fins in the known device of Lee et al. in order to prevent leakage from occurring in the device of Lee et al.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over of Lee et al., US 2016/0056277, as applied to claim 1 above, further in view of More et al., US 9,847,334, cited by Applicant on the Information Disclosure Statement submitted on 05 June 2023, of record.
In the semiconductor structure of Lee et al., the first source/drain feature 310/515 comprises silicon germanium 515 (see paragraph [0022], and the second source/drain feature 310 comprises silicon (see paragraph [0015], however, Lee et al. fail to teach or suggest that the first source/drain feature 310/515 includes a p-type dopant and the second source/drain feature includes an n-type dopant. However, Lee et al. disclose that the disclosed device can be a FinFET device, and the FinFET device may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device, see paragraph [0007]. In the same field of endeavor, More et al. discloses a semiconductor device, shown in Fig. 1G, comprising a first pair of fins 126P and a second pair of fins 126N disposed on a substrate 102P/102N. In the semiconductor structure of More et al., the first source/drain feature comprises silicon germanium 102A and 102B and a p-type dopant, wherein the second source/drain feature comprises silicon 108 and an n-type dopant, see Figs. 2 and 3 and column 13, lines 48-60. In light of the disclosure of More et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first source/drain feature 310/515 could include a p-type dopant and the second source/drain feature 310 could include an n-type dopant in the known semiconductor structure of Lee et al. in order to fabricate a CMOS FinFET.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over of Lee et al., US 2016/0056277, newly cited, as applied to claim 1 above, further in view of Liu et al., US 2016/0190303, cited by Applicant on the Information Disclosure Statement submitted on 05 June 2023, of record.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over of Lee et al., US 2016/0056277, newly cited, in view of More et al., US 9,847,334, cited by Applicant on the Information Disclosure Statement submitted on 05 June 2023, of record, as applied to claim 17 above, further in view of Liu et al., US 2016/0190303, cited by Applicant on the Information Disclosure Statement submitted on 05 June 2023, of record.
Lee et al. is applied as above. However, Lee et al. lack anticipation of the silicon nitride liner 405 having a thickness between about 0.5 nm to about 3 nm, as required in dependent claims 9 and 18. In the FinFET shown in Fig. 4, Liu et al. disclose disposing a dielectric liner 118 comprising silicon nitride between an isolation feature 120 and surfaces of a pair of fins in order to provide structural stability for fins. Liu et al. further disclose that if the silicon nitride liner 118 has a thickness of less than 5 nm, the silicon nitride liner is effective as an oxygen barrier, see paragraph [0010]. In light of this teaching of Liu et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention. that the silicon nitride liner 405 in the known semiconductor structure of Lee et al. could have a thickness in the range of about 0.5 nm to about 3 nm to provide structural stability and be an effective barrier to oxygen.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2016/0056277, in view of More et al., US 9,847,334, as applied to claim 17 above, further in view of Ching et al., US 2018/0366465. newly cited.
Lee et al. is applied as above. Dependent claim 21 requires a silicon liner disposed on sidewalls of the top layers and the middle layer of the first pair of fins, wherein the silicon nitride liner is disposed on sidewalls of the bottom layers of the first pair of fins. Lee et al. clearly teach the silicon nitride liner 405 is disposed on sidewalls of the bottom layers 226 of the first pair of fins 520, as shown in Fig. 7 of Lee et al. However, Lee et al. fail to disclose a silicon liner disposed on sidewalls of the top layers and the middle layer of the first pair of fins. In the same field of endeavor, Ching et al. disclose a silicon liner 242 (see paragraph [0030]) disposed on sidewalls of the top layers 208a and the middle layer 208b of the first pair of fins 204, as shown in Fig. 2L of Ching et al. Ching et al. disclose this configuration prevents leakage problems from occurring in the FinFET and provides good FinFET performance, see paragraph [0022]. In light of the advantages associated with the silicon cap layer 242 of Ching et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a silicon liner 242 disposed on sidewalls of the top layers 515 and the middle layer 310 of the first pair of fins 520 in the known device of Lee et al. in order to prevent leakage from occurring in the device of Lee et al.
Response to Arguments
Applicant's arguments filed 11 May 2026 have been fully considered but they are not persuasive. Independent claim 1 has been amended to require the first pair of fins each comprise a first bottom portion, a middle portion on the first bottom portion, and a first top portion on the middle portion, wherein the first top portion, the middle portion, and the first bottom portion have different compositions. As noted in the rejection above, Lee et al. disclose the first pair of fins 520 each comprise a first bottom portion 226, a middle portion 310 on the first bottom portion 226, and a first top portion 515 on the middle portion 310, wherein the first top portion 515, the middle portion 310, and the first bottom portion 226 have different compositions, as disclosed in paragraphs [0022], [0015], and [0012]. Therefore, amended claim 1 does not recite a semiconductor structure which is patentably distinct from the known semiconductor structure of Lee et al.
Claim 10 has been amended to require the middle portion and the first upper portion of the first fin have different compositions. More et al. clearly teach a first upper portion 102A/102B over the middle portion 114/116 and comprising silicon germanium (see column 6, lines 19-24), wherein the middle portion 114/116 (comprising silicon/silicon carbide) and the first upper portion 102A/102B (comprising silicon germanium) have different compositions. Therefore, this limitation does not patentably distinguish Applicant’s claimed semiconductor structure from the known structure of More et al. Independent claim 10 has also been amended to require a dielectric liner and that the dielectric liner contacts the silicon cap layer. This is clearly taught by the newly-applied Ching et al. reference, see the above rejection of claims 10-16.
Claim 17 has been amended to require the first pair of fins 520 each comprise a bottom layer comprising silicon and an n- type dopant, a middle layer on the bottom layer, and a top layer on the middle layer, wherein the top layer and the middle layer are different in composition from the bottom layer. Lee et al. clearly teach that the first pair of fins 520 comprise a bottom layer 226 comprising silicon (see paragraph [0012]), a middle layer 310 on the bottom layer 225, and a top layer 515 on the middle layer 310, as shown in Fig. 7, wherein the top layer 515 and the middle layer 310 are different in composition from the bottom layer 226, see paragraphs [0015] and [0022]: middle layer 310 can be GaAs and top layer 515 can be Ge, for example). Therefore, requiring the top layer and the middle layer to have different compositions does not patentably distinguish Applicant’s claimed semiconductor structure from the known semiconductor structure of Lee et al. Independent claim 17 has also been amended to require the first source/drain feature 515/310 is on the bottom layers 226 of the first pair of fins 520. This is clearly shown in Fig. 7 of Lee et al. Consequently, amended claim 17 does not recite a semiconductor structure which is patentably distinct from the known semiconductor structure of Lee et al.
Conclusion
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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