DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/07/2025 has been entered.
Response to Amendment
Applicant’s amendment filed on 10/07/2025 is acknowledged. Claims 1, 11, and 16 have been amended. Claims 21-22 are added.
Response to Arguments
Applicant’s arguments with respect to claims 1-12, 15-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “gate spacers spacing apart the gate structure from the source/drain contacts”. It is unclear whether these gate spacers are the same or different than the one defined in claim 1. For the purpose of examination, it is interpreted to be the same.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US 2017/0053804 A1) in view of Lee et al. (US 2019/0333915 A1).
Regarding claim 1, Lu teaches a device (100 in Fig. 2L of Lu), comprising:
source/drain epitaxial structures (104, as described in [0013] of Lu) over a substrate (102);
source/drain contacts (118-134a/b) over the source/drain epitaxial structures, respectively;
a gate structure (the second gate stack 108 from the right) laterally between the source/drain contacts;
a gate dielectric cap (110 and 120) over the gate structure and having a bottom surface below top surfaces of the source/drain contacts (as shown in Fig. 2L of Lu);
a nitride-based etch stop layer (124);
an interlayer dielectric (ILD) layer (126) over the nitride-based etch stop layer;
a gate contact (136a) extending through the ILD layer, the nitride-based etch stop layer, and the gate dielectric cap to electrically connect with the gate structure; and
a gate spacer (112) spacing apart the gate structure from one of the source/drain contacts.
But Lu does not teach that the device comprising: an oxide-based etch-resistant layer over the gate dielectric cap, wherein the oxide-based etch-resistant layer has a bottom surface forming an interface with a top surface of one of the source/drain contacts; the nitride-based etch stop layer is over the oxide-based etch-resistant layer; the gate contact extending through the oxide-based etch-resistant layer, wherein the bottom surface of the oxide-based etch-resistant layer is separated from the gate spacer by a first distance, and separated from a bottommost point of the gate dielectric cap by a second distance greater than the first distance.
Lee teach a device (Fig. 4 of Lee) comprising: a gate electrode (460); a gate spacer (360); and a gate capping layer (480) covering a top surface of the gate electrode and top surface of the gate spacer (as shown in Fig. 4 and [0023] of Lee); an oxide-base etch-resistant layer (silicon oxide layer 490, as described in [0035] of Lee) and a nitride-base etch stop layer (silicon nitride 500, as described in [0035] of Lee), and an ILD (510) above the oxide-base etch-resistant layer and the nitride-base etch stop layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have replaced the etch-resistant layer of Lu with the oxide-base etch-resistant layer and the nitride-base etch stop layer of Lee in order to have better etch preventing properties.
As incorporated, the layer 124 in Fig. 2L of Lu would be replaced by the SiO layer 490 and SiN 500 in Fig. 4 of Lee. As such, the bottom of this SiO layer 490 would be spaced from the gate spacer 112 by the thickness of layer 120 while the bottom of 490 is spaced away from the bottom of the gate dielectric cap 110 by a distance greater than the thickness of layer 120, as shown in Fig. 2L of Lu.
Regarding claim 4, Lu in view of Lee teaches all limitations of the device of claim 1, and also teaches wherein the oxide-based etch-resistant layer is further over the source/drain contacts (as shown in Fig. 2L of Lu).
Regarding claim 6, Lu in view of Lee teaches all limitations of the device of claim 1, and also teaches wherein the oxide-based etch-resistant layer is spaced apart from the gate structure by the gate dielectric cap (as combined in claim 1 above).
Regarding claim 9, Lu in view of Lee teaches all limitations of the device of claim 1, and further comprising: gate spacers (112, see interpretation in 112b rejection above) spacing apart the gate structure from the source/drain contacts.
Regarding claim 10, Lu in view of Lee teaches all limitations of the device of claim 9, and wherein the gate spacers are spaced apart from the oxide-based etch-resistant layer by the gate dielectric cap (as shown in Fig. 2L of Lu).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yen in view of Lee, as applied to claim 1 above, and further in view of Iwata et al. (US 2019/0296012 A1).
Regarding claim 2, Lu in view of Lee teaches all limitations of the device of claim 1, but does not teach wherein the oxide-based etch-resistant layer is thinner than the nitride-based etch stop layer.
Iwata teaches a device (702 in Fig. 12 of Iwata), comprising: source/drain contacts (782N) over source/drain epitaxial structures; a gate structure (752N-754) laterally between the source/drain contacts; a gate dielectric cap (758); an oxide-based etch-resistant layer (silicon oxide liner 761) over the gate dielectric cap; a nitride-based etch stop layer (silicon nitride liner 762) over the oxide-based etch-resistant layer; an ILD (770) over the nitride-based etch stop layer; the oxide-based etch-resistant layer is in the range of 1nm to 10nm and the nitride-based etch stop layer is in the range of 2nm to 20nm.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the oxide-based etch-resistant layer and nitride-based etch stop layer with thicknesses as disclosed by Iwata since these are known working ranges of these layers.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yen in view of Lee, as applied to claim 1 above, and further in view of Iwata and Frank et al. (US 8778759 B1).
Regarding claim 3, Lu in view of Lee teaches all limitations of the device of claim 1, but does not teach wherein the oxide-based etch-resistant layer is thinner than the gate dielectric cap.
Iwata teaches a device (702 in Fig. 12 of Iwata), comprising: source/drain contacts (782N) over source/drain epitaxial structures; a gate structure (752N-754) laterally between the source/drain contacts; a gate dielectric cap (758); an oxide-based etch-resistant layer (silicon oxide liner 761) over the gate dielectric cap; a nitride-based etch stop layer (silicon nitride liner 762) over the oxide-based etch-resistant layer; an ILD (770) over the nitride-based etch stop layer; the oxide-based etch-resistant layer is in the range of 1nm to 10nm and the nitride-based etch stop layer is in the range of 2nm to 20nm.
Frank teaches a device (see Fig. 4 of Frank) comprising a gate dielectric cap (70L) is disposed a gate structure; the gate dielectric cap has thickness in the range from 3nm to 60 nm (column 11 lines 10-15 of Frank).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made thickness of the oxide-based etch-resistant layer in the range of 1nm to 10nm, the thickness of the nitride-based etch stop layer in the range of 2nm to 20nm, as disclosed by Iwata, and to have made the gate dielectric cap to have thickness in the range from 3nm to 60nm, as disclosed by Frank, since these are known working ranges of these layers.
As incorporated, the gate dielectric cap layer 36 of Yen would be thicker than the oxide-based etch-resistant layer 490 of Lee, as incorporated above.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Lee, as applied in claim 1 above, and further in view of Yen et al. (US 2015/0364371 A1).
Regarding claim 5, Lu in view of Lee teaches all limitations of the device of claim 1, but does not teach wherein an interface between the oxide-based etch-resistant layer and the gate dielectric cap is aligned with an interface between the oxide-based etch-resistant layer and one of the source/drain contacts.
Yen teaches a device (100 in Fig. 12 of Yen). The device comprises: gate structures (26); source/drain regions (24) at opposite sides of the gate structures; source/drain contact structures (34) where the top surface of the source/drain contacts are at the same level as the top surface of the gate structures (see Fig. 12 of Yen); etch stop layer (44) over the top surfaces of the source/drain contacts and the gate structures; ILD layer (46) over the etch stop layer; and gate contacts (64) extending through the ILD, the etch-stop layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the source/drain contacts are disclosed by Yen in order to have more freedom in routing electrical signals to the source/drain regions of the device.
As incorporated, the source/drain contacts 134a/b of Lu are replaced by the source/drain contacts 34 and 52/52B of Yen.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Lee, as applied to claim 1 above, and further in view of Hsieh et al. (US 10083863 B1).
Regarding claim 7, Lu in view of Lee teaches all limitations of the device of claim 1, but does not teach the device further comprising: a metal cap interposing the gate contact and the gate structure.
Hsieh teaches a device (Fig. 15 of Hsieh) comprising: a gate structure (209 in Fig. 15 of Hsieh) over a substrate (102); a gate contact structure (252) extending through an ILD layer (246) to electrically connect with the gate structure; a metal cap (242) interposing the gate contact and the gate structure which is made of tungsten.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed a metal cap structure (242 of Hsieh) as according to Hsieh in order to increase the electrical conductivity of the gate contact.
Regarding claim 8, Lu in view of Lee teaches all limitations of the device of claim 7, but does not explicitly teach wherein the metal cap comprises fluorine-free tungsten.
Hsieh discloses that the tungsten in a gate structure is a fluorine-free tungsten (column 14 lines 60-62 of Hsieh).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the metal cap structure with fluorine-free tungsten in order to increase reliability.
Claims 21 is rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Lee, as applied to claim 1 above, and further in view of Kim et al. (US 2018/0083002 A1).
Regarding claim 21, Lu in view of Lee teaches all limitations of the device of claim 1, but does not teach wherein a sidewall of the gate contact has a slope change, along a direction toward the gate structure, from a vertical shape to a tapered shape at an interface formed by the gate dielectric cap and the oxide-based etch-resistant layer.
Kim teaches a gate contact structure (CP2 and VC2 in Fig. 2A of Kim) to a gate structure (GL). The gate contact structure extends through an ILD (194), an etch stop layer (192), dielectric gate cap (180-186) to the gate structure (GL), wherein a sidewall of the gate contact has a slope change (slope change at interface of VC2 and CP2), along a direction toward the gate structure, from a vertical shape (sidewall of VC2) to a tapered shape (tapered sidewall of CP2) at an interface formed by the gate dielectric cap and the etch stop layer (see Fig. 2A of Kim).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate contact structure as disclosed by Kim in order to have more freedom in routing electrical signals to the gate structure.
Claims 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yen in view of Lee, Iwata et al. (US 2019/0296012 A1) and Kim.
Regarding claim 11, Lu teaches a device (100 in Fig. 12 of Yen), comprising:
a gate structure (26) over a substrate (20) ;
source/drain regions (24) at opposite sides of the gate structure;
source/drain contacts (42/42A) over the source/drain regions, respectively;
a gate dielectric cap (36) over the gate structure;
an etch-resistant layer (44) over the gate dielectric cap, wherein a bottom surface of the etch-resistant layer is in contact with a top surface of one of the source/drain contacts (as shown in Fig. 12, the bottom surface of ESL 44 forms an interface with the S/D contact 34);
an interlayer dielectric (ILD) layer (46) over the etch stop layer; and
a gate contact (64A; even though it is shown that only gate structure 26C has the gate contact 64A, it is inherent that each gate structure needs such contact in order to function as intended) over the gate structure, the gate contact extending through the ILD layer, and the etch-resistant layer to electrically connect with the gate structure (as shown in Fig. 12).
But Yen does not teach that the gate dielectric cap has opposite sidewalls interfacing the source/drain contacts; and the device comprising an etch stop layer over the etch-resistant layer, the etch stop layer having a thickness greater than a thickness of the etch-resistant layer; and the gate contact extending through the etch stop layer, wherein a sidewall of the gate contact has a slope change, along a downward direction, from a vertical shape to a tapered shape at an interface formed by the etch-resistant layer and the gate dielectric cap.
Lee teach a device (Fig. 4 of Lee) comprising: a gate electrode (460); a gate spacer (360); and a gate capping layer (480) covering a top surface of the gate electrode and top surface of the gate spacer (as shown in Fig. 4 and [0023] of Lee), and having opposite sidewalls interfacing the source/drain contacts (as shown in Fig. 4 of Lee); an oxide-base etch-resistant layer (silicon oxide layer 490, as described in [0035] of Lee) and a nitride-base etch stop layer (silicon nitride 500, as described in [0035] of Lee), and an ILD (510) above the oxide-base etch-resistant layer and the nitride-base etch stop layer.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have replaced the etch-resistant layer of Yen with the oxide-base etch-resistant layer and the nitride-base etch stop layer of Lee in order to have better etch preventing properties.
But Yen in view of Lee does not teach that the etch stop layer having a thickness greater than a thickness of the etch-resistant layer; and wherein a sidewall of the gate contact has a slope change, along a downward direction, from a vertical shape to a tapered shape at an interface formed by the etch-resistant layer and the gate dielectric cap.
Iwata teaches a device (702 in Fig. 12 of Iwata), comprising: source/drain contacts (782N) over source/drain epitaxial structures; a gate structure (752N-754) laterally between the source/drain contacts; a gate dielectric cap (758); an oxide-based etch-resistant layer (silicon oxide liner 761) over the gate dielectric cap; a nitride-based etch stop layer (silicon nitride liner 762) over the oxide-based etch-resistant layer; an ILD (770) over the nitride-based etch stop layer; the oxide-based etch-resistant layer is in the range of 1nm to 10nm and the nitride-based etch stop layer is in the range of 2nm to 20nm.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made thickness of the oxide-based etch-resistant layer in the range of 1nm to 10nm, the thickness of the nitride-based etch stop layer in the range of 2nm to 20nm, as disclosed by Iwata, since these are known working ranges of these layers.
But Yen-Lee-Iwata does not teach that wherein a sidewall of the gate contact has a slope change, along a downward direction, from a vertical shape to a tapered shape at an interface formed by the etch-resistant layer and the gate dielectric cap.
Kim teaches a gate contact structure (CP2 and VC2 in Fig. 2A of Kim) to a gate structure (GL). The gate contact structure extends through an ILD (194), an etch stop layer (192), dielectric gate cap (180-186) to the gate structure (GL), wherein a sidewall of the gate contact has a slope change (slope change at interface of VC2 and CP2), along a direction toward the gate structure, from a vertical shape (sidewall of VC2) to a tapered shape (tapered sidewall of CP2) at an interface formed by the gate dielectric cap and the etch stop layer (see Fig. 2A of Kim).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the gate contact structure as disclosed by Kim in order to have more freedom in routing electrical signals to the gate structure.
Regarding claim 15, Yen-Lee-Iwata-Kim teaches all limitations of the device of claim 11, and also teaches wherein the etch-resistant layer continuously extends across the source/drain contacts (see Fig. 12 of Yen).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yen in view of Lee and Iwata, and further in view of Frank.
Regarding claim 12, Yen-Lee-Iwata-Kim teaches all limitations of the device of claim 11, but does not teach wherein the thickness of the etch-resistant layer is less than a thickness of the gate dielectric cap.
Frank teaches a device (see Fig. 4 of Frank) comprising a gate dielectric cap (70L) is disposed a gate structure; the gate dielectric cap has thickness in the range from 3nm to 60 nm (column 11 lines 10-15 of Frank).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the gate dielectric cap to have thickness in the range from 3nm to 60nm, as disclosed by Frank, since these are known working ranges of these layers.
As incorporated, the thickness of the etch-resistant layer is less than a thickness of the gate dielectric cap.
Allowable Subject Matter
Claims 16-20, 22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 16, the prior art of record does not disclose or fairly suggest a device with “wherein a width at a top surface of the second gate contact is greater than a width at a top surface of the first gate contact” along with other limitations of the claim.
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898