DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (“Kim” US 2018/0323170), Otsubo et al. (“Otsubo” US 2018/0166394), and Kumura et al. (“Kumura” US 2019/0246521).
Regarding claim 1, Kim discloses a semiconductor device (Figures 9A-9B), comprising:
a substrate (910);
at least one electronic component (970) mounted on a first side of the substrate (lower side of the substrate 910 in Figure 9A);
a board-to-board connector (980 interconnect, construed as a board-to-board connector because the interconnect 980 is used to connect the substrate, i.e. one board, to another, external board, see para. [0094]) mounted on the first side of the substrate (lower side of the substrate 910);
a dielectric member (940, made of an encapsulant or dielectric material) or a discrete antenna package mounted on a second side (upper side of the substrate 910) of the substrate opposite to the first side of the substrate (lower side of the substrate 910);
an encapsulant (950) formed on the first side of the substrate (lower side of the substrate 910, see Figure 9A) and at least partially encapsulating the at least one electronic component (970, see Figure 9A);
a shielding layer (960) formed on the encapsulant (950, see Figure 9A which shows the shielding layer formed over and on side surfaces of the encapsulant 950),
wherein the encapsulant (950), the shielding layer (960), [the thermal interface layer and the metal lid] expose the board-to-board connector (980, see Figures 9A-9B)
Kim does not disclose wherein the shielding laver comprises: a wetting sublayer; a shielding sublayer formed on the wetting sublayer; and a protection sublayer formed on the shielding sublayer;
a thermal interface layer formed on the shielding layer; and
a metal lid formed on the thermal interface layer.
Otsubo discloses in Figure 15, however, a shielding layer (102) comprising a wetting sublayer (102a); a shielding sublayer (120b) formed on the wetting sublayer (102a, see Figure 15); and a protection sublayer (102c) formed on the shielding sublayer (102b, see Figure 15).
It would have been obvious to one having ordinary skill in the art to incorporate the structure of the shield layer of Otsubo into the shield layer of Kim for the purpose of improving corrosion resistance (Otsubo, para. [0004]).
Further, Kumura discloses in Figure 3A a thermal interface layer (1) formed on the shielding layer (2, formed of copper, which provides EMI shielding, thus is construed as a shielding layer, see para. [0132]); and a metal lid (5) formed on the thermal interface layer (1, see Figure 3A).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kumura into the teachings of Kim to include a thermal interface layer formed on the shielding layer and a metal lid of Lin formed on the thermal interface layer for the purpose of improving heat dissipation of the device (Kumura, para. [0132]).
Regarding claim 4, Otsubo discloses wherein the protection sublayer (102c) comprises stainless steel, organic solderability preservative, or nickel (para. [0004 discloses the protection sublayer 102c is formed of stainless steel).
Regarding claim 5, Otsubo discloses wherein the wetting sublayer (102a) comprises stainless steel or titanium (para. [0004] discloses the wetting sublayer is formed of stainless steel); and
the shielding sublayer (102b) comprises copper (para. [0004] discloses that the conductive film or shielding sublayer is formed of copper).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, Otsubo, and Kumura as applied to claim 1 above, and further in view of Kamoda et al. (“Kamoda” US 2022/0102239).
Regarding claim 6, Kamoda discloses that the encapsulant (sealing portion 23) is constructed that a top surface of the at least one electronic component (11) is exposed from the encapsulant (23) to be in contact with the shielding layer (32, component 11 is in contact with the shielding layer 32 through layers 17, 34, and 30).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kamoda into the teachings of Lin to include features such that the encapsulant is constructed that a top surface of the at least one electronic component is exposed from the encapsulant to be in contact with the shielding layer for the purpose of transferring heat from the component to the shield, improving heat dissipation capabilities (Kamoda, para. [0044]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, Otsubo, and Kumura as applied to claim 1 above, and further in view of Chang (US 2022/0384359).
Regarding claim 7, Chang discloses a thermal interface layer (160, Figure 1) that comprises a solder paste (para. [0041]).
It would have been obvious to one having ordinary skill in the art to use a solder paste for the thermal interface material as taught by Chang because substitution of one known element for another known equivalent element would result in the predictable result of using material to facilitate heat dissipation. Additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Response to Arguments
Applicant’s arguments with respect to the prior art rejections of record have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899