DETAILED ACTION
This Office Action is in response to Amendment filed June 22, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 18 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
(1) Regarding claim 18, Applicants originally disclosed in paragraph [0017] of current application that “Further, the epitaxial stack may be formed at a relatively high temperature’, and that “After fabrication of the epitaxial stack a cool down process may be performed to reduce a temperature of the chamber that the epitaxial stack is disposed in from the high temperature to a low temperature (e.g., to room temperature).” In addition, Applicants originally disclosed in paragraph [0026] of current application that “For example, during fabrication of the epitaxial stack 101, the one or more layers of the epitaxial stack 101 (e.g., the superlattice layers 108, the high resistivity buffer layer 112, the channel layer 114, etc.) may each be deposited and/or grown at a relatively high temperature (e.g., greater than 900 degrees Celsius) to have a relatively low initial tensile stress”, that “After depositing and/or growing the epitaxial stack 101, a cool down process is performed where a temperature of the epitaxial stack 101 is reduced from the high temperature to a low temperature (e.g., about 20 degrees Celsius).” However, Applicants did not originally disclose the step of “performing a cool down process after forming the active layer, wherein the cool down process comprises reducing a temperature of the processing chamber in a region at or around the substrate from a high temperature to a low temperature less than the high temperature” as recited on lines 3-6, because Applicants did not originally disclose measuring the temperature in a vague or indefinite area of “a region at or around the substrate”, which appears to be either an Applicants’ attempt to broaden the scope of the original disclosure in the amended claim 18, or Applicants’ unsurety on where the temperature is actually measured since “a region at or around the substrate” can be any arbitrary region in the processing chamber including a wall of the processing chamber or a sample holder.
(2) Further regarding claim 18, Applicants originally disclosed in paragraph [0084] of current application that “In an embodiment, the method further includes performing a cool down process after forming the active layer, wherein the cool down process comprises reducing a temperature of a chamber the substrate is disposed in from a high temperature to a low temperature, wherein the interlayer buffer layers are configured to reduce tensile stress on the channel layer and/or the plurality of superlattice layers during the cooling process (emphasis added).” However, Applicants did not originally disclose that “at least one of the interlayer buffer layers is configured to reduce tensile stress on at least one of the plurality of superlattice layers during the cool down process” as recited on lines 6-8, because (a) this newly added limitation can suggest that one of the interlayer buffer layers is configured to reduce tensile stress on one or more of the plurality of superlattice layers during the cool down process, and (b) however, as the underlined portions of paragraph [0084] of current application clearly indicate, Applicants originally disclosed that “the interlayer buffer layers are configured to reduce tensile stress on … the plurality of superlattice layers during the cooling process”.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. It is not clear how “the first superlattice layer has a first density of dislocations and the first interlayer buffer layer has a second density of dislocations greater than the first density of dislocations”, because (a) the limitation of claim 17 does not appear to claim an actual feature of the first superlattice layer and the first interlayer buffer layer since (i) Applicants basically claim that the dislocations are generated in the first interlayer buffer layer, which cannot actually happen in reality as the dislocations should be reduced continuously in an epitaxial growth direction, and (ii) Applicants do not specifically claim that the first superlattice layer is the bottommost superlattice layer, and the first interlayer buffer layer is the bottommost interlayer buffer layer, and therefore, the amended claim 17 still has more or less the same indefiniteness issue as before since instead of the density of dislocations continuously decreasing as more superlattice layers and more interlayer buffer layers are grown, the density of dislocations would exhibit a profile of alternating increase and decrease throughout the plurality of superlattice layers and the plurality of interlayer buffer layers, and (b) therefore, the claim limitation of the amended claim 17 still appears to be directed to a concept rather than an actual feature of the claimed semiconductor device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Hikosaka et al. (US 9,391,145) as evidenced by Lee et al. (“High-Power InGaN-Based LED With Tunneling-Junction-Induced Two-Dimensional Electron Gas at AlGaN/GaN Heterostructure,” IEEE TRANSACTIONS ON ELECTRON DEVICES 58 (2011) pp. 3058-3064) in view of Chiu et al. (US 2021/0327850)
Regarding claim 16, Hikosaka et al. disclose a method for forming a semiconductor device (Fig. 2), comprising: forming a seed layer (AlN buffer layer 62) (col. 4, lines 48-49) over a substrate (40), because the AlN buffer layer 62 would function as a seed layer for subsequently deposited semiconductor layer(s); forming a plurality of superlattice layers (pair of 51a and 52a, and pair of 51b and 52b) and a plurality of interlayer buffer layers (53a and 53b) over the seed layer, because (a) Applicants originally disclosed in paragraph [0031] of current application that “In some embodiments, the plurality of superlattice layers 108 respectively comprise one or more pairs of semiconductor layers 208, 210 that respectively comprise a first semiconductor layer 208 stacked with a second semiconductor layer 210 (emphasis added)”, (b) therefore, each of the claimed plurality of superlattice layers can be a single pair of two layers, and (c) in this case, the pair of layers 51a and 52a, and the pair of layers 51b and 52b can be referred to as a plurality of, or two or more, superlattice layers, wherein the interlayer buffer layers are stacked alternatingly with the superlattice layers, because (a) the phrase “stacked alternatingly” does not necessarily suggest that all of the interlayer buffer layers are in direct contact with at least one of the superlattice layers, and (b) for example, in a stack of layers A/B/C/A/B/C…, the sublayers A and B are stacked alternatingly with each other together with the sublayer C, wherein the superlattice layers (pair of 51a and 52a, and pair of 51b and 52b) are formed at a first temperature (temperatures corresponding to 51a/52a and 51b/52b in Fig. 2C) and the interlayer buffer layers are formed at a second temperature (temperature corresponding to 53a/53b in Fig. 2C), because (a) the terms “first temperature” and “second temperature” do not necessarily suggest that the first temperature is constant throughout the deposition of the superlattice layers, and the second temperature is constant throughout the deposition of the interlayer buffer layers, (b) an increasing temperature, a decreasing temperature or a varying temperature can be referred to as a first temperature or a second temperature, and (c) also, Applicants claimed in the previously presented claim 20 that “the plurality of interlayer buffer layers includes a first interlayer buffer layer and a second interlayer buffer layer overlying the first interlayer buffer layer, wherein the first interlayer buffer layer is formed at a lower temperature than the second interlayer buffer layer (emphasis added)”, which suggests that the second temperature at which the interlayer buffer layers are formed as recited on line 7 of claim 16 can actually be a plurality of temperatures, less than the first temperature, because the pair of layers 51a/52a and 51b/52b are deposited at higher temperatures than the layers 53a/53b as the GT or growth temperature chart shown in Fig. 2C of Hikosaka et al. indicate, wherein a first superlattice layer (pair of 51a and 52a) of the plurality of superlattice layers (pair of 51a and 52a, and pair of 51b and 52b) comprise a first III-V semiconductor material (GaN) doped with one or more dopants (Si in layer 52a) (col. 13, line 6), wherein a first interlayer buffer layer (53a) of the plurality of interlayer buffer layers (53a and 53b) over the first superlattice layer comprises a second III-V semiconductor material (AlGaN) doped with the one or more dopants as evidenced by Fig. 3 of Hikosaka et al. and Fig. 1 of Lee et al., because (a) Fig. 3 of Hikosaka et al. shows diffusion of Si dopants out of AlGaN layers in the stacked body 50 in Fig. 2 of Hikosaka et al. (col. 14, lines 28-29), (b) even though Hikosaka et al. and Lee et al. disclose different semiconductor devices, the kinetic and thermodynamic behaviors of the atoms constituting the component layers should be substantially the same, (c) as can be seen in Fig. 1 of Lee et al., the undoped GaN layer is unintentionally doped with Si diffused from the neighboring n-type AlGaN layer, and (d) therefore, Lee et al. provide further evidence that the AlGaN layer constituting the claimed first interlayer buffer layer 53a should inherently be doped with Si diffusing from the neighboring n-type GaN layer 52a constituting the claimed first superlattice layer 51a/52a at least unintentionally by the same kinetics of unintentional doping of the undoped GaN layer by the neighboring Si-doped n-type AlGaN layer disclosed by Lee et al. due to the temporal and spatial symmetry of the Laws of Physics.
Hikosaka et al. differ from the claimed invention by not comprising forming a channel layer over the plurality of superlattice layers; and forming an active layer over the channel layer.
Hikosaka et al. further disclose that a high electron mobility transistor (HEMT) can be formed (col. 3, lines 23-27).
In addition, Chiu et al. disclose a method for forming a semiconductor device or a HEMT (Fig. 1), comprising forming a superlattice layer (40) ([0021]), forming a channel layer (50) ([0021]) over the superlattice layer; and forming an active layer (60) ([0021]) over the channel layer.
Since both Hikosaka et al. and Chiu et al. teach a method for forming a semiconductor device or HEMT, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method disclosed by Hikosaka et al. can further comprise forming a channel layer over the plurality of superlattice layers, and forming an active layer over the channel layer as disclosed by Chiu et al., because as disclosed by Chiu et al., a GaN-based HEMT has been most commonly formed by employing a channel layer and a barrier layer due to the well-known electrical and mechanical characteristics of GaN and AlGaN each constituting the channel layer and barrier layer ([0029]-[0030] of Chiu et al.).
Regarding claims 19-21, Hikosaka et al. further disclose that the first temperature is within a range of about 950 to 1,200 degrees Celsius ((approximately) 1130oC in Fig. 2C), wherein the second temperature range is within a range of about 600 to 950 degrees Celsius ((approximately) 800oC in Fig. 2C) (claim 19), and the plurality of interlayer buffer layers (53a and 53b) includes a second interlayer buffer layer (53b) overlying the first interlayer buffer layer (53a), wherein the first interlayer buffer layer interfaces with a top surface of the first superlattice layer (pair of 51a and 52a) of the plurality of superlattice layers, and the second interlayer buffer layer interfaces with a top surface of a second superlattice layer (pair of 51b and 52b) of the plurality of superlattice layers (claim 20), forming the first superlattice layer (51a and 52a) comprises: performing a first epitaxial process to form a first semiconductor layer (51a) over the seed layer (60); and performing a second epitaxial process to form a second semiconductor layer (52a) over the first semiconductor layer (claim 21).
Allowable Subject Matter
Claims 25-30 and 36-30 are allowed, because Hikosaka et al. as evidenced by Lee et al. in view of Chiu et al. do not disclose the limitation “epitaxially growing the first interlayer buffer layer comprises in-situ doping by flowing a dopant precursor” newly recited in the amended claim 25, and the newly added limitation of the amended claim 29, which was the limitation of the previously presented claim 25.
Claims 22-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicants’ arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicants' amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 July 17, 2026
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