DETAILED ACTION
This Office Action is in response to Application filed June 6, 2023.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Group II and Species H drawn to the embodiment shown in Fig. 24 of current application in the reply filed on September 29, 2025 is acknowledged.
After Applicants filed new claims together with the Election on September 29, 2025 and the Examiner’s subsequent Restriction Requirement mailed November 28, 2025, Applicants’ election without traverse of Species A drawn to the material composition of the first interlayer buffer layer recited in the new claim 28 in the reply filed on January 28, 2026 is acknowledged.
The Examiner notes that the amended claim 31 and its dependent claims are not directed to the embodiment shown in Fig. 24 of current application, because (a) as discussed in the Restriction Requirement mailed November 28, 2025, the new claim 31 filed September 29, 2025 is distinct from the species whose features are recited in claim 28 filed September 29, 2025, (b) even after the additional amendment filed January 28, 2026, claims 31-35 do not appear to be directed to the Elected Species H drawn to the embodiment shown in Fig. 24 of current application since Applicants did not originally disclose that the semiconductor device shown in Fig. 24 of current application is formed where “the first superlattice layer, the second superlattice layer, the undoped GaN layer, and the AlGaN layer are formed at temperatures greater than the first temperature” recited on the last three lines of the amended claim 31, which is the growth temperature of the “interlayer buffer layer” recited on lines 5-6 of the further amended claim 31, (c) in other words, Applicants did not originally disclose any comparison of the growth temperatures of the undoped GaN layer, which is the layer 114, and the AlGaN layer, which is the layer 118, with respect to the claimed interlayer buffer layer, which is the bottommost layer 110 with respect to the embodiment shown in Fig. 24 of current application, and (d) while Applicants may have originally disclosed the relative growth temperatures recited in claim 31 with respect to the nonelected species shown in Fig. 1 of current application, the semiconductor device shown in Fig. 1 of current application and the semiconductor device shown in Fig. 24 of current application are markedly distinct from each other in terms of (i) the number of sublayers and/or detailed structure of the superlattice layers 108, see the blank spaces for the plurality of superlattice layers 108 in Fig. 1 of current application in comparison to the bilayer structure 208/210 of the plurality of superlattice layers 108 in Fig. 24 of current application, (ii) the source/drain electrodes 124/126 in Figs. 1 and 24 of current application, (iii) the doped semiconductor structure 120 in Figs. 1 and 24 of current application, etc., all of which may require distinct growth process parameters such as growth temperatures for the claimed first and second superlattice layer, the undoped GaN layer, the AlGaN layer and the (bottommost) interlayer buffer layer for the embodiments shown in Figs. 1 and 24 of current application.
Claim Objections
Claim 18 is objected to because of the following informalities: on line 3, “a chamber the temperature” should be amended, because it is not grammatical. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17, 18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 17, it is not clear how “the superlattice layers respectively have a first density of dislocations and the interlayer buffer layers respectively have a second density of dislocations greater than the first density of dislocations”, because (a) the limitation of claim 17 does not appear to claim an actual feature of the superlattices and interlayer buffer layers since (i) Applicants basically claim that the dislocations are generated in each of the interlayer buffer layers and then destroyed in in each of the superlattice layers with exactly the same efficacy to have “a first density” or a single first density, and “a second density” or a single second density, respectively, which cannot actually happen in reality as the dislocations should be reduced continuously in an epitaxial growth direction, and (ii) the two or more superlattice layers cannot “respectively have a first density of dislocations”, and the two or more interlayer buffer layers cannot “respectively have a second density of dislocations” as the two or more superlattice layers cannot have identical “first density of dislocations” and the two or more interlayer buffer layers cannot have identical “second density of dislocations”, and (b) therefore, the claim limitation of claim 17 appears to be directed to a concept rather than an actual feature of the claimed semiconductor device.
(2) Regarding claim 18, it is not clear whether the limitation “reducing a temperature of a chamber the substrate [sic] is disposed in from a high temperature to a low temperature” recited on lines 3-4 suggests that the method steps recited in claim 16 have been performed at elevated temperatures with the chamber having been heated since otherwise the temperature of the chamber cannot be reduced after the method steps recited in claim 16 have been performed, (b) however, heating the chamber is an energy-inefficient way of heating the substrate while the method steps recited in claim 16 are performed, and unless there is a thermally conductive medium between the chamber walls and the substrate, it would be very difficult, if not impossible, to heat the substrate to an elevated temperature, not to mention to the desired growth temperatures of the claimed component layers recited in claim 16, and (c) if arguendo there had been the thermally conductive medium inside the chamber, the growth processes recited in claim 16 would have been negatively, if not detrimentally, affected since atoms constituting the thermally conductive medium are likely to be incorporated into the component layers recited in claim 16 as unwanted impurities.
(3) Further regarding claim 18, it is not clear what the limitation “the interlayer buffer layers are configured to reduce tensile stress on the channel layer and/or the plurality of superlattice layers during the cool down process” recited on lines 4-6 suggests, because (a) it is not clear whether Applicants claim that each of “the interlayer buffer layers” is “configured to reduce tensile stress on the channel layer and/or” each of “the plurality of superlattice layers during the cool down process”, or “the interlayer buffer layers are” collectively “configured to reduce tensile stress on the channel layer and/or the plurality of superlattice layers during the cool down process” collectively since (i) each of the interlayer buffer layers is in contact with distinct material layers, (ii) at least one of the interlayer buffer layers is not in contact with the channel layer to affect the stress of the channel layer, and (iii) at least one of the interlayer buffer layers is not in contact with all of the plurality of superlattice layers to affect the stress of the plurality of superlattice layers, (b) it is not clear whether Applicants suggest that “the channel layer and/or the plurality of superlattice layers” were under tensile stress before the cool down process, and if so, it is not clear why “the channel layer and/or the plurality of superlattice layers” were under tensile stress before the cool down process, especially when Applicants do not claim the cause(s) of the tensile stress before the cool down process, (c) if arguendo the channel layer is grown directly on the topmost superlattice of the plurality of superlattice layers, Applicants basically claim that both the channel layer and the topmost superlattice layer of the plurality of superlattice layers in direct contact with each other are under tensile stress, which does not appear to be in compliance with the laws of physics since it appears that the Third Law of the Newtonian Mechanics stipulating the same magnitude of the action-reaction does not apply in such a situation, i.e. if one of the two layers in contact with each other is under tensile stress, the other of the two layers should be under compressive stress, vice versa, and (d) therefore, claim 18 may fail to comply with the Enablement requirement.
(4) Regarding claim 20, it is not clear how “the plurality of interlayer buffer layers includes a first interlayer buffer layer and a second interlayer buffer layer overlying the first interlayer buffer layer, wherein the first interlayer buffer layer is formed at a lower temperature than the second interlayer buffer layer” as recited in claim 20 when “a second temperature less than the first temperature” as recited on line 6-7 of claim 16, and whether the implicitly suggested two growth temperatures in claim 20 both satisfy the limitation recited on lines 6-7 of claim 16, or only one of the temperatures satisfies the limitation recited on lines 6-7 of claim 16, because (a) “a second temperature” recited in claim 16 appears to be a single temperature, but it appears that Applicants claim that “a second temperature” is actually two or more temperatures in claim 20, (b) in this case, it is not clear whether the comparison of the first and second temperature recited in claim 16 applies to both the temperatures recited in claim 20, or one of the temperatures recited in claim 20, and (c) furthermore, it is not clear whether claim 20 is directed to Applicants’ elected species drawn to the embodiment shown in Fig. 24 of current application since (i) Applicants did not originally disclose the two temperatures recited in claim 20 with regard to the elected species shown in Fig. 24 of current application, and (ii) the only time Applicants mentioned such two temperatures is in paragraph [0084] of current application where Applicants stated that “In an embodiment, the plurality of interlayer buffer layers includes a first interlayer buffer layer and a second interlayer buffer layer overlying the first interlayer buffer layer, wherein the first interlayer buffer layer is formed at a lower temperature than the second interlayer buffer layer”, which may not be pertinent to the embodiment shown in Fig. 24 of current application; if claim 20 is not directed to the elected species, claim 20 should be withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16, 19, 21, 22, 25-28 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Hikosaka et al. (US 9,391,145) in view of Chiu et al. (US 2021/0327850)
Regarding claim 16, Hikosaka et al. disclose a method for forming a semiconductor device (Fig. 2), comprising: forming a seed layer (AlN buffer layer 62) (col. 4, lines 48-49) over a substrate (40), because the AlN buffer layer 62 would function as a seed layer for subsequently deposited semiconductor layer(s); forming a plurality of superlattice layers (pair of 51a and 52a, and pair of 51b and 52b) and a plurality of interlayer buffer layers (53a and 53b) over the seed layer, because (a) Applicants originally disclosed in paragraph [0031] of current application that “In some embodiments, the plurality of superlattice layers 108 respectively comprise one or more pairs of semiconductor layers 208, 210 that respectively comprise a first semiconductor layer 208 stacked with a second semiconductor layer 210 (emphasis added)”, (b) therefore, each of the claimed plurality of superlattice layers can be a single pair of two layers, and (c) in this case, the pair of layers 51a and 52a, and the pair of layers 51b and 52b can be referred to as a plurality of, or two or more, superlattice layers, wherein the interlayer buffer layers are stacked alternatingly with the superlattice layers, because (a) the phrase “stacked alternatingly” does not necessarily suggest that all of the interlayer buffer layers are in direct contact with at least one of the superlattice layers, and (b) for example, in a stack of layers A/B/C/A/B/C…, the sublayers A and B are stacked alternatingly with each other together with the sublayer C, wherein the superlattice layers (pair of 51a and 52a, and pair of 51b and 52b) are formed at a first temperature (temperatures corresponding to 51a/52a and 51b/52b in Fig. 2C) and the interlayer buffer layers are formed at a second temperature (temperature corresponding to 53a/53b in Fig. 2C), because (a) the terms “first temperature” and “second temperature” do not necessarily suggest that the first temperature is constant throughout the deposition of the superlattice layers, and the second temperature is constant throughout the deposition of the interlayer buffer layers, (b) an increasing temperature, a decreasing temperature or a varying temperature can be referred to as a first temperature or a second temperature, and (c) Applicants further claim in claim 20 that “the plurality of interlayer buffer layers includes a first interlayer buffer layer and a second interlayer buffer layer overlying the first interlayer buffer layer, wherein the first interlayer buffer layer is formed at a lower temperature than the second interlayer buffer layer (emphasis added)”, which suggests that the second temperature at which the interlayer buffer layers are formed as recited on line 6 of claim 16 can actually be a plurality of temperatures, less than the first temperature, because the pair of layers 51a/52a and 51b/52b are deposited at higher temperatures than the layers 53a/53b as the GT or growth temperature chart shown in Fig. 2C of Hikosaka et al. indicate.
Hikosaka et al. differ from the claimed invention by not comprising forming a channel layer over the plurality of superlattice layers; and forming an active layer over the channel layer.
Hikosaka et al. further disclose that a high electron mobility transistor (HEMT) can be formed (col. 3, lines 23-27).
In addition, Chiu et al. disclose a method for forming a semiconductor device or a HEMT (Fig. 1), comprising forming a superlattice layer (40) ([0021]), forming a channel layer (50) ([0021]) over the superlattice layer; and forming an active layer (60) ([0021]) over the channel layer.
Since both Hikosaka et al. and Chiu et al. teach a method for forming a semiconductor device or HEMT, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method disclosed by Hikosaka et al. can further comprise forming a channel layer over the plurality of superlattice layers, and forming an active layer over the channel layer as disclosed by Chiu et al., because as disclosed by Chiu et al., a GaN-based HEMT has been most commonly formed by employing a channel layer and a barrier layer due to the well-known electrical and mechanical characteristics of GaN and AlGaN each constituting the channel layer and barrier layer ([0029]-[0030] of Chiu et al.).
Regarding claims 19 and 21, Hikosaka et al. further disclose that the first temperature is within a range of about 950 to 1,200 degrees Celsius ((approximately) 1130oC in Fig. 2C), wherein the second temperature range is within a range of about 600 to 950 degrees Celsius ((approximately) 800oC in Fig. 2C) (claim 19), forming a first superlattice layer (51a and 52a) in the plurality of superlattice layers comprises: performing a first epitaxial process to form a first semiconductor layer (51a) over the seed layer (60); and performing a second epitaxial process to form a second semiconductor layer (52a) over the first semiconductor layer (claim 21).
Regarding claim 22, Hikosaka et al. further disclose that the first epitaxial process comprises in-situ doping the second semiconductor layer (52a) with one or more dopants (Si) (col. 13, line 6).
Hikosaka et al. differ from the claimed invention by not showing that the first epitaxial process also comprises in-situ doping the first semiconductor layer (51a) with one or more dopants.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first semiconductor layer 51a of Hikosaka et al. can comprise one or more dopants doped by in-situ doping, because (a) the first semiconductor layer 51a of Hikosaka et al. is in direct contact with the first Si-containing layer 52a, (b) therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Si dopants contained in the first Si-containing layer 52a can thermally diffuse into the adjacent layers including the first semiconductor layer 51a since, as shown in Fig. 2C of Hikosaka et al., the growth process involves elevated temperatures at which the Si dopants would diffuse to a certain degree, and (c) furthermore, for the first semiconductor layer 51a to be bonded to the first Si-containing layer 52a, there should be intermixing of atoms between the two layers since otherwise the two layers would not be firmly bonded with each other, in which case, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first semiconductor layer 51a to comprise a first dopant of Si since Si dopants originally located at or near the top/bottom surface of the first Si-containing layer 52a would likely to migrate into the first semiconductor layer 51a, which can be referred to as an in-situ doping since Applicants do not specifically claim how the in-situ doping is performed.
Please refer to the explanations of the corresponding limitations above.
Regarding claim 25, Hikosaka et al. disclose a method for forming a semiconductor device (Fig. 2), comprising: epitaxially growing a seed layer (62) over a substrate (40) (col. 15, line 49 - col. 16, line 53), wherein the seed layer comprises a first III-V semiconductor material (AlN); epitaxially growing a lower buffer layer (63a, 63b or 63c) over the seed layer, wherein the lower buffer layer comprises a second III-V semiconductor material (AlGaN) different from the first III-V semiconductor material; epitaxially growing a first superlattice layer (pair of 51a and 52a) over the lower buffer layer; epitaxially growing a first interlayer buffer layer (53a) over the first superlattice layer; epitaxially growing a second superlattice layer (pair of 51b and 52b) over the first interlayer buffer layer; epitaxially growing an upper buffer layer (53b or 54b) over the second superlattice layer, wherein the upper buffer layer comprises a third III-V semiconductor material (AlGaN of 53b or AlGaN of 54b) different from the first and second III-V semiconductor materials (AlN of 62 and AlGaN of 63a/63b/63c), because (a) Hikosaka et al. disclose that “In such a case, it is favorable for stacking to be performed so that the Al composition ratio decreases in the upward direction from the foundation layer 60 (e.g., in the direction from the foundation layer 60 toward the functional layer 10)”, that “That is, it is favorable for the Al composition ratio of the second AlGaN foundation layer 63b to be lower than the Al composition ratio of the first AlGaN foundation layer 63a; and it is favorable for the Al composition ratio of the third AlGaN foundation layer 63c to be lower than the Al composition ratio of the second AlGaN foundation layer 63b” on lines 41-51 of column 6, and (b) therefore, at least one of the lower buffer layers 63a/63b/63c would have an AlGaN material composition different from an AlGaN material composition of the third III-V semiconductor material, while the AlGaN layer constituting the lower buffer layer is different from the first III-V semiconductor material of AlN.
Hikosaka et al. differ from the claimed invention by not showing that the first interlayer buffer layer comprises a first dopant, and by not comprising epitaxially growing a channel layer over the upper buffer layer; epitaxially growing an upper semiconductor layer over the channel layer; and forming a doped semiconductor structure over the upper semiconductor layer, wherein the doped semiconductor structure comprises a second dopant different from the first dopant.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first interlayer buffer layer 53a of Hikosaka et al. can comprise a first dopant, because (a) the first interlayer buffer layer or high Al composition layer 53a of Hikosaka et al. is in direct contact with the first Si-containing layer 52a (col. 13, line 6), (b) therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Si dopants initially contained in the first Si-containing layer 52a can thermally diffuse into the adjacent layers including the first interlayer buffer layer or high Al composition layer 53a since, as shown in Fig. 2C of Hikosaka et al., the first interlayer buffer layer or high Al composition layer 53a is grown at (approximately) 800oC at which Si dopants would inherently thermally diffuse to a certain degree, and (c) furthermore, for the first interlayer buffer layer or high Al composition layer 53a to be bonded to the underlying first Si-containing layer 52a, there should be intermixing of atoms between the two layers since otherwise the two layers would not be firmly bonded with each other, in which case, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first interlayer buffer layer or high Al composition layer 53a to comprise a first dopant of Si since Si dopants originally located at or near the top surface of the first Si-containing layer 52a would likely to migrate into the first interlayer buffer layer or high Al composition layer 53a.
Further regarding claim 25, Hikosaka et al. differ from the claimed invention by not comprising epitaxially growing a channel layer over an upper buffer layer; epitaxially growing an upper semiconductor layer over the channel layer; and forming a doped semiconductor structure over the upper semiconductor layer, wherein the doped semiconductor structure comprises a second dopant different from the first dopant.
Chiu et al. disclose a method for forming a semiconductor device (Fig. 1), comprising epitaxially growing a channel layer (50) ([0021] and [0050]) over an upper buffer layer (40); epitaxially growing an upper semiconductor layer (60) over the channel layer; and forming a doped semiconductor structure (901 or composite structure including 901) ([0031]) over the upper semiconductor layer, wherein the doped semiconductor structure comprises a second dopant (Mg) different from the first dopant (Si of Hikosaka et al.).
Since both Hikosaka et al. and Chiu et al. teach a method for forming a semiconductor device or HEMT, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the method disclosed by Hikosaka et al. can further comprise epitaxially growing a channel layer over an upper buffer layer; epitaxially growing an upper semiconductor layer over the channel layer; and forming a doped semiconductor structure over the upper semiconductor layer, wherein the doped semiconductor structure comprises a second dopant different from the first dopant, because (a) as disclosed by Chiu et al., a GaN-based HEMT has been most commonly formed by employing a channel layer and a barrier layer due to the well-known electrical and mechanical characteristics of GaN and AlGaN each constituting the channel layer and barrier layer ([0029]-[0030] of Chiu et al.), and (b) in addition, a Mg-doped gate layer has been commonly employed in forming GaN-based HEMT devices to provide an energy barrier between a barrier layer and a gate electrode, which has also been one of the most commonly employed configurations of GaN-based HEMT devices that allows one of ordinary skill in the art to control and optimize the isolation characteristics between the barrier layer and the gate electrode.
Regarding claims 26-28, Hikosaka et al. further disclose that the lower buffer layer (63a) is epitaxially grown at a first temperature (1020° C) (col. 15, line 62 - col. 16, line 3) and the first interlayer buffer layer (53a) is epitaxially grown at a second temperature ((approximately) 800oC in Fig. 2C) less than the first temperature (claim 26), wherein the upper buffer layer (54b) is epitaxially grown at a third temperature ((approximately) 1130oC in Fig. 2C) greater than the second temperature ((approximately) 800oC in Fig. 2C) (claim 27), and the first interlayer buffer layer (53a; AlGaN) comprises the first III-V semiconductor material (AlN) or the second III-V semiconductor material (AlGaN), because (a) the transitional phrase “comprises” does not preclude presence of other materials, and (b) AlGaN is a solid solution of AlN and AlGaN (claim 28).
Regarding claim 30, Chiu et al. further comprise for the method of claim 25 forming a pair of source/drain structures (90 and 92) ([0021]) over the upper semiconductor layer and on opposing sides of the doped semiconductor structure ((stricture including) 901); and forming a gate electrode (904 and/or 94) over the doped semiconductor structure.
Allowable Subject Matter
Claims 23, 24 and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tomabechi et al. (US 9,196,685)
Briere (US 8,957,454)
Briger et al. (US 2007/0056506)
Oishi et al. (US 8,405,064)
Chen et al. (US 11,387,356)
Sazawa et al. (US 2016/0149000)
Yanagihara (US 7,652,282)
Sato (US 8,264,001)
Yanagihara et al. (US 7,569,870)
Anderson et al. (US 10,516,076)
Gao et al. (US 8,981,382)
Hikosaka et al. (US 8,680,537)
Hung et al. (US 2013/0087762)
Shioda et al. (US 8,785,943)
Yamaguchi et al. (US 8,405,064)
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J. K./Primary Examiner, Art Unit 2815 March 19, 2026