DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Rejections Under 35 U.S.C. § 102, filed 12/29/2025, with respect to the rejection(s) of claim(s) 1 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) in view of Lin, Shih-Hao et al. (Pub No. US 20220367728 A1) (hereinafter, Lin).
6. Applicant’s arguments, see Rejections Under 35 U.S.C. § 102, filed 12/29/2025, with respect to the rejection(s) of claim(s) 14 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lee, Wei-Ju et al. (Pub No. US 20210126135 A1) (hereinafter, Lee).
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 7 and 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee, Wei-Ju et al. (Pub No. US 20210126135 A1) (hereinafter, Lee).
Lee, Fig 37A, Three-dimensional view of semiconductor device
PNG
media_image1.png
614
782
media_image1.png
Greyscale
Re Claim 7, (Original) Lee teaches a device comprising:
a semiconductor substrate (100; Fig 37A; ¶[0009]);
a first semiconductor channel (Lowest channel layer; 108; Fig 37C; ¶[0011]) over the substrate;
a second semiconductor channel (Middle channel layer; 108; Fig 37C; ¶[0011]) over the first semiconductor channel;
a gate structure (Metal gate structures; 170/270; Figs 32B/37A; ¶[0046]) wrapping around the first and second semiconductor channels;
a first inner spacer (Middle spacer below middle channel 108; 235; Fig 36C; ¶[0052]) abutting a lower surface (Below middle channel 108) of the second semiconductor channel, an upper surface (Above lower channel 108) of the first semiconductor channel and a first sidewall surface (Sidewall of 170, e.g. gates between channel layers 108) of the gate structure;
a second inner spacer (Lower spacer below lower channel 108; 235; Fig 36C; ¶[0052]) abutting a lower surface (Below lower channel 108) of the first semiconductor channel, an upper surface (Above substrate 100) of the substrate and a second sidewall (Second surface of 170, e.g. gate above substrate 100) surface of the gate structure;
a recess (Recesses; R1; Fig 19B; ¶[0028]) in the semiconductor substrate;
a liner layer (Semiconductor layer; 145; Fig 19B; ¶[0036]) in the recess , the liner layer having an upper surface (Top surface of 145; Fig 19B) that is substantially level with an upper surface (Top surface of 100; Fig 19B) of the substrate, the liner layer being a same material (Liner 145 and substrate 100 may be SiGe; ¶¶[0010, 0036]) as the semiconductor substrate;
a bottom isolation structure (Semiconductor layer; 150; Fig 37B; ¶[0055]) on the liner layer and abutting (150 shares a common boundary with 108) a sidewall (Sidewall of lower channel 108) of the second inner spacer; and
a source/drain region (Source/drain epitaxial layers; 260/262; Fig 37C; ¶[0053]) on the bottom isolation structure and physically isolated from the semiconductor substrate by the bottom isolation structure.
Re Claim 12, (Original) Lee teaches the device of claim 7, wherein the source/drain region includes:
a first epitaxial layer (Source/drain epitaxial layers; 162; Fig 37B; ¶[0043]) in direct contact with the first and second semiconductor channels;
a second epitaxial layer (Source/drain epitaxial layers covering epitaxial layer 162; 164; Fig 37B; ¶[0045]) on the first epitaxial layer; and
a source/drain contact (Source/drain contacts; 360; Fig 37C; ¶[0067]) on the first and second epitaxial layers.
Re Claim 13, (Original) Lee teaches the device of claim 12, wherein the second epitaxial layer (Source/drain epitaxial layers covering epitaxial layer 162; 164; Fig 37B; ¶[0045]) extends from a lower surface (Lower surface of 162) of the source/drain contact (Source/drain contacts; 360; Fig 37C; ¶[0067]) to a level (Extends to a level above lower channel 108) that is above the first semiconductor channel (Semiconductor layer; 108; Fig 37C; ¶[0011]).
Re Claim 14, (Currently Amended) Lee teaches a device, comprising:
a substrate (100; Fig 37A; ¶[0009]);
an N-type transistor (N-type transistor in first region; 100A; Fig 37A; ¶[0009]) on the substrate, including:
a first stack of first nanostructure channels (Left side stack of semiconductor layers; 108; Fig 37B; ¶[0011]);
a bottom isolation structure (Semiconductor layer/dielectric layer; 150/145’; Fig 37B; ¶¶[0040,0055]) comprising a dielectric material (Dielectric layer 145’ may be an oxide; ¶[0040]); and
a first source/drain region (Left side epitaxial layer; 164; Fig 37B; ¶[0045]) that is in direct contact with the first nanostructure channels and the bottom isolation structure, the first source/drain region being physically isolated from the substrate by the bottom isolation structure; and
a P-type transistor (N-type transistor in first region; 100B; Fig 37A; ¶[0009]) on the substrate, including:
a second stack of second nanostructure channels (Right side stack of semiconductor layers; 108; Fig 37B; ¶[0011]); and
a second source/drain region (Middle epitaxial layer; 164; Fig 37B; ¶[0045]) that is in direct contact with the second nanostructure channels and the substrate.
Re Claim 15, (Original) Lee teaches the device of claim 14, wherein the N-type transistor (N-type transistor in first region; 100A; Fig 37A; ¶[0009]) further includes a liner layer (Dielectric layer; 145'; Fig 37B; ¶[0055]) between the substrate (100; Fig 37A; ¶[0009]) and the bottom isolation structure (Semiconductor layer; 150; Fig 37B; ¶[0055]).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 1-2 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung), and further in view of Lin, Shih-Hao et al. (Pub No. US 20220367728 A1) (hereinafter, Lin).
Jung, Figs 2/3, Cross sections of semiconductor device
PNG
media_image2.png
703
406
media_image2.png
Greyscale
PNG
media_image3.png
679
510
media_image3.png
Greyscale
Re Claim 1, (Currently Amended) Jung teaches a device comprising:
a stack of nanostructure channels (Stack of semiconductor patterns; 124; Fig 2; ¶[0033]) over a substrate (100; Figs 2/3; ¶[0024]);
a gate structure (Gate electrode; 320; Fig 2; ¶[0037]) wrapping around the stack;
a source/drain region (Source/drain layer; 250; Fig 3; ¶[0025]) on the substrate, the source/drain region including:
a first epitaxial layer (Epitaxial layer; 230/234/830; Figs 3/31/34; ¶[0045]) comprising silicon germanium (SiGe) (Epitaxial layer 234 may be SiGe; ¶[0135]) in direct contact with the channels; and
a second epitaxial layer (Epitaxial layer; 240/244/820; Figs 3/31/34; ¶[0045]) comprising SiGe (Epitaxial layer 244 may be SiGe; ¶[0135]) on the first epitaxial layer,
the second epitaxial layer having higher germanium concentration (Per ¶[0142] epitaxial layer 244 may be greater germanium concentration than epitaxial layer 234) than the first epitaxial layer; and
a bottom isolation structure (Growth prevention pattern/air gap; 225/260; Fig 31; ¶[0030]) between the source/drain region and the substrate, the bottom isolation structure being a dielectric layer (May comprise of SiN; ¶[0030]) that is in direct contact with the source/drain region.
However, Jung does not teach the first and second epitaxial layers comprising SiGe being doped with n-type impurities.
In the same field of endeavor, Lin teaches the first (Epitaxial layer; 520; Fig 14; ¶[0035]) and second epitaxial layers (Epitaxial layer; 530; Fig 14; ¶[0039]) comprising SiGe (Epitaxial layers 520A/530A and 520B/530B may have SiGe; ¶¶[0057-0058]) being doped with n-type impurities (Epitaxial layers 520/530 may be n-type doped with P or As; ¶¶[0035, 0039]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used first and second epitaxial layers comprising SiGe being doped with n-type impurities, as taught by Lin for the device as taught by Jung. One would have been motivated to do this with a reasonable expectation of success because SiGe is highly soluble to n-type dopants such as Phosphorous. Further, Germanium further reduces the bandgap of the source/drain regions allowing for improved device speeds through a desired mobility cascade (Lin, ¶[0041]).
Re Claim 2, (Original) Jung teaches the device of claim 1, further comprising:
the substrate (100; Figs 30; ¶[0024]); and
a recess (Opening; 190; Fig 30; ¶[0069]) in the substrate underlying the bottom isolation structure (Growth prevention pattern/air gap; 225/260; Fig 31; ¶[0030]);
wherein the source/drain region (Source/drain layer; 250; Fig 31; ¶[0025]) extends into the recess.
Re Claim 6, (Original) Jung teaches the device of claim 1, wherein the source/drain region further comprises a third epitaxial layer (Twelth epitaxial layer; 840; Fig 34; ¶[0162]),
the third epitaxial layer being in direct contact with upper surfaces of the first epitaxial layer (Epitaxial layer; 830; Figs 34; ¶[0045]) and the second epitaxial layer (Epitaxial layer; 820; Figs 34; ¶[0045]),
the third epitaxial layer extending to a level (Per Fig 34 Twelth epitaxial layer 840 extends above channels 426) above an uppermost channel of the stack of nanostructure channels (Stack of semiconductor patterns; 426; Fig 34; ¶[0033]).
11. Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) in view of Lin, Shih-Hao et al. (Pub No. US 20220367728 A1) (hereinafter, Lin) as applied to claim 2 above, and further in view of Lee, Wei-Ju et al. (Pub No. US 20210126135 A1) (hereinafter, Lee).
Re Claim 3, (Original) Jung teaches the device of claim 2, wherein the bottom isolation structure (Growth prevention pattern/air gap; 225/260; Fig 31; ¶[0030]) lines an upper surface (Upper surface of active pattern 105 in which opening 190 is formed; Fig 30) of the recess (Opening; 190; Fig 30; ¶[0069]).
However, Jung in view of Lin does not teach wherein the bottom isolation structure extends to a level above the recess.
In the same field of endeavor, Lee teaches the bottom isolation structure (Epitaxial layer/Semiconductor layer; 162/150; Fig 37B; ¶[0055]) extends to a level (Extends slightly above recess occupied by 150/162) above the recess.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the bottom isolation structure to extend to a level above the recess, as taught by Lee for the device as taught by Jung in view of Lin. One would have been motivated to do this with a reasonable expectation of success to further prevent leakage current from one epitaxy structure to another through the base portion, thereby avoiding the punch-through effect, as suggested by Lee (¶[0050]).
Re Claim 4, (Original) Jung in view of Lin does not teach device of claim 3, wherein the bottom isolation structure has thickness in a range of about 1 nanometer (nm) to about 5 nm.
However, the ordinary artisan would have recognized the thickness of the first metal
seed layer to have a range of about 1 nm to about 5 nm, to be a result effective variable
affecting the material growth of the epitaxial layers located in source/drain regions which are of comparable size. Thus, it would have been obvious to modify the thickness of the bottom isolation structure within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. (See MPEP 2144.05 II.B)
Re Claim 5, (Original) Jung teaches the device of claim 3, wherein the bottom isolation structure (Growth prevention pattern/air gap; 225/260; Fig 31; ¶[0030]) includes SiN, SiCN, SiCON, SiOC, SiC or SiO (May comprise of SiN; ¶[0030]).
12. Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Wei-Ju et al. (Pub No. US 20210126135 A1) (hereinafter, Lee) as applied to claim 7 above, and further in view of More, Shahaji B. et al. (Pub No. US 20220037520 A1) (hereinafter, More).
More, Fig 17, Semiconductor device include four epitaxial layers
PNG
media_image4.png
507
425
media_image4.png
Greyscale
Re Claim 8, (Original) Lee does not teach the device of claim 7, wherein the source/drain region includes:
a first epitaxial layer having germanium concentration that is in a range of about 10% to about 50%; and
a second epitaxial layer having germanium concentration greater than that of the first epitaxial layer in a range of about 25% to about 70%.
In the same field of endeavor, More teaches the device of claim 7, wherein the source/drain region includes:
a first epitaxial layer (Second epitaxial layer; 50-2; Fig 17; ¶[0069]) having germanium concentration (15 - 25 atomic %; ¶0069]) that is in a range of about 10% to about 50%; and
a second epitaxial layer (Third epitaxial layer; 50-3; Fig 17; ¶[0072]) having germanium concentration (Ge content up to 30 atomic %; ¶[0072]) greater than that of the first epitaxial layer in a range of about 25% to about 70%.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a source/drain region with a first epitaxial layer having germanium concentration that is in a range of about 10% to about 50% and a second epitaxial layer having germanium concentration greater than that of the first epitaxial layer in a range of about 25% to about 70%, as taught by More for the device as taught by Lee. One would have been motivated to do this with a reasonable expectation of success in order to optimize compressive strain for PMOS transistors, such that the Ge content surrounding the channels causes lattice mismatch and thereby increases drive current.
Re Claim 9, (Original) Lee fails to disclose the exact dopant atomic ratios of the first and second epitaxial layers as claimed.
Nevertheless, as depicted in Figure 37C such features must possess particular dimension. The choice of 0.5% to 4% and 0.5% to 8%, respectively, is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Lee's dopant atomic ratios of the first and second epitaxial layers to be 0.5% to 4% and 0.5% to 8%, respectively, because this would be the best engineering design choice.
In addition, the selection of particular dopant atomic ratios as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
Re Claim 10, (Original) Lee fails to disclose the exact dopant concentration of the first and second epitaxial layers as claimed.
Nevertheless, as depicted in Figure 37C such features must possess particular dimension. The choice of 2.5E20 cm-3 to about 2E21 cm-3 and 2.5E20 cm-3 to about 4E21 cm-3, respectively, is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Lee's dopant concentration of the first and second epitaxial layers to be 2.5E20 cm-3 to about 2E21 cm-3 and 2.5E20 cm-3 to about 4E21 cm-3, respectively, because this would be the best engineering design choice.
In addition, the selection of particular dopant concentrations as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
Re Claim 11, (Original) Lee does not teach the device of claim 7, wherein the source/drain region includes:
a first epitaxial layer having germanium concentration that is in a range of about 10% to about 50%; and
a second epitaxial layer having germanium concentration greater than that of the first epitaxial layer in a range of about 25% to about 70%; and
a third epitaxial layer on upper surfaces of the first epitaxial layer and the second epitaxial layer, the third epitaxial layer having germanium concentration in a range of about 50% to about 70%.
In the same field of endeavor, More teaches the device of claim 7, wherein the source/drain region includes:
a first epitaxial layer (Second epitaxial layer; 50-2; Fig 17; ¶[0069]) having germanium concentration (15 - 25 atomic %; ¶0069]) that is in a range of about 10% to about 50%; and
a second epitaxial layer (Third epitaxial layer; 50-3; Fig 17; ¶[0072]) having germanium concentration (Ge content up to 30 atomic %; ¶[0072]) greater than that of the first epitaxial layer in a range of about 25% to about 70%.
a third epitaxial layer (Fourth epitaxial layer; 50-4; Fig 17; ¶0074]) on upper surfaces (Above portions of upper surfaces of 50-2 and 50-3; Fig 17) of the first epitaxial layer and the second epitaxial layer, the third epitaxial layer having germanium concentration (Ge content of 30-60 atomic %; ¶[0074]) in a range of about 50% to about 70%.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a source/drain region with a first epitaxial layer having germanium concentration that is in a range of about 10% to about 50% and a second epitaxial layer having germanium concentration greater than that of the first epitaxial layer in a range of about 25% to about 70% and a third epitaxial layer on upper surfaces of the first epitaxial layer and the second epitaxial layer, the third epitaxial layer having germanium concentration in a range of about 50% to about 70%, as taught by More for the device as taught by Lee. One would have been motivated to do this with a reasonable expectation of success in order to optimize compressive strain for PMOS transistors, such that the Ge content surrounding the channels causes lattice mismatch and thereby increases drive current.
13. Claims 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, Wei-Ju et al. (Pub No. US 20210126135 A1) (hereinafter, Lee) as applied to claim 14 above, and further in view of Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung).
Re Claim 16, (Original) Lee teaches the device of claim 14, wherein the first source/drain region includes:
a first epitaxial layer (Upper source/drain epitaxial layers; 162; Fig 37B; ¶[0043]) in direct contact with the first nanostructure channels (Left side stack of semiconductor layers; 108; Fig 37B; ¶[0011]); and
a second epitaxial layer (Upper portion of source/drain epitaxial layers covering uppermost epitaxial layer 162; 164; Fig 37B; ¶[0045]) on the first epitaxial layer.
However, Lee does not teach the second epitaxial layer having higher germanium concentration than the first epitaxial layer.
In the same field of endeavor, Jung teaches the second epitaxial layer (Epitaxial layer; 240/244/820; Figs 3/31/34; ¶[0045]) having higher germanium concentration (Per ¶[0142] epitaxial layer 244 may be greater germanium concentration than epitaxial layer 234) than the first epitaxial layer (Epitaxial layer; 230/234/830; Figs 3/31/34; ¶[0045]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a second epitaxial layer having higher germanium concentration than the first epitaxial layer, as taught by Jung for the device as taught by Lee. One would have been motivated to do this with a reasonable expectation of success because the first epitaxial layer is disposed adjacent to the channel layers, producing adequate compressive strain, whereas the second epitaxial layer requires a higher germanium concentration to produce the same compressive strain on the channel layers in order to have uniform electrical characteristics.
Re Claim 17, (Original) Lee teaches the device of claim 16, wherein the first epitaxial layer includes:
a plurality of first epitaxial sub-layers (Lower source/drain epitaxial layers; 162; Fig 37B; ¶[0043]), each being in direct contact with a respective one of the first nanostructure channels (Left side stack of semiconductor layers; 108; Fig 37B; ¶[0011]) and isolated (Lower source/drain epitaxial layers 162 are separated from upper source/drain epitaxial layers 162; Fig 37B) from others of the plurality of first epitaxial sub layers; and
a second epitaxial sub-layer (Lower portion of source/drain epitaxial layers covering lowermost epitaxial layer 162; 164; Fig 37B; ¶[0045]) on the plurality of first epitaxial sub-layers.
Re Claim 18, (Original) Lee teaches the device of claim 16, further comprising:
a third epitaxial layer (Epitaxial layer; 266; Fig 37C; ¶[0055]) on upper surfaces (Disposed over upper surfaces of 264/262; Fig 37C) of the first epitaxial layer (Upper source/drain epitaxial layers; 162; Fig 37B; ¶[0043]) and the second epitaxial layer (Upper portion of source/drain epitaxial layers covering uppermost epitaxial layer 162; 164; Fig 37B; ¶[0045]), the third epitaxial layer extending to a level above an upper surface of an uppermost first nanostructure channel (Left side uppermost semiconductor layer; 108; Fig 37B; ¶[0011]) of the first stack.
Re Claim 19, (Original) Lee does not teach the device of claim 16, wherein the second source/drain region includes:
a third epitaxial layer in direct contact with the second nanostructure channels; and
a fourth epitaxial layer on the third epitaxial layer, the fourth epitaxial layer having higher germanium concentration than the third epitaxial layer.
In the same field of endeavor, Jung teaches the device of claim 16, wherein the second source/drain region includes:
a third epitaxial layer (Tenth epitaxial layer; 820; Fig 49; ¶[0164]) in direct contact with the second nanostructure channels (Right or left channels; 426; Fig 49; ¶[0164]); and
a fourth epitaxial layer (Twelth epitaxial layer; 840; Fig 49; ¶[0164])bon the third epitaxial layer, the fourth epitaxial layer having higher germanium concentration (Per ¶[0164] 840 has greater germanium concentration than 820) than the third epitaxial layer.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a third epitaxial layer in direct contact with the second nanostructure channels and a fourth epitaxial layer on the third epitaxial layer, the fourth epitaxial layer having higher germanium concentration than the third epitaxial layer, as taught by Jung for the device as taught by Lee. One would have been motivated to do this with a reasonable expectation of success in order to optimize compressive strain for PMOS transistors, such that the Ge content surrounding the channels causes lattice mismatch and thereby increases drive current.
14. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee, Wei-Ju et al. (Pub No. US 20210126135 A1) (hereinafter, Lee) in view of Jung, Sujin et al. (Pub No. US 20200365692 A1) (hereinafter, Jung) as applied to claim 19 above, and further in view of More, Shahaji B. et al. (Pub No. US 20220037520 A1) (hereinafter, More).
Re Claim 20, (Original) Lee in view of Jung does not teach the device of claim 19, wherein germanium concentration is:
in a range of about 10% to about 50% in the first epitaxial layer;
in a range of about 25% to about 70% in the second epitaxial layer;
in a range of about 10% to about 35% in the third epitaxial layer; and
in a range of about 25% to about 80% in the fourth epitaxial layer.
In the same field of endeavor, More teaches the device of claim 19, wherein germanium concentration is:
in a range of about 10% to about 50% (15 - 25 atomic %; ¶0069]) in the first epitaxial layer (Second epitaxial layer; 50-2; Fig 17; ¶[0069]);
in a range of about 25% to about 70% (Ge content up to 30 atomic %; ¶[0072]) in the second epitaxial layer (Third epitaxial layer; 50-3; Fig 17; ¶[0072]) ;
in a range of about 10% to about 35% (Ge content of 30-60 atomic %; ¶[0074]) in the third epitaxial layer (Fourth epitaxial layer; 50-4; Fig 17; ¶0074]); and
in a range of about 25% to about 80% (20-60%; ¶0076]) in the fourth epitaxial layer (Fifth epitaxial layer; 50-5; Fig 17; ¶0076]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a germanium concentration in a range of about 10% to about 50% in the first epitaxial layer, in a range of about 25% to about 70% in the second epitaxial layer, in a range of about 10% to about 35% in the third epitaxial layer and in a range of about 25% to about 80% in the fourth epitaxial layer, as taught by More for the device as taught by Lee in view of Jung. One would have been motivated to do this with a reasonable expectation of success in order to optimize compressive strain for PMOS transistors, such that the Ge content surrounding the channels causes lattice mismatch and thereby increases drive current.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Kim, Da Hye et al. (Pub No. US20230420519A1) discloses a semiconductor device having improved performance and reliability. The semiconductor device may include a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction. A plurality of gate structures may be on the lower pattern and spaced apart in the first direction, and a source/drain pattern, which may include a semiconductor liner film and a semiconductor filling film on the semiconductor liner film. A liner recess that is defined by an inner surface of the semiconductor liner film may include a plurality of width extension regions, and a width of each width extension region in the first direction may increase and then decreases, as a distance increases in the second direction from an upper surface of the lower pattern.
[2] More, Shahaji et al. (Pub No. US20220059703A1) discloses a semiconductor device includes semiconductor nanostructures disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor nanostructures, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor nanostructures, a gate electrode layer disposed on the gate dielectric layer and wrapping around each channel region, and insulating spacers disposed in spaces, respectively. The spaces are defined by adjacent semiconductor nanostructures, the gate electrode layer and the source/drain region. The source/drain epitaxial layer includes multiple doped SiGe layers having different Ge contents and at least one of the source/drain epitaxial layers is non-doped SiGe or Si.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
/T.E.D./
Examiner
Art Unit 2817