Prosecution Insights
Last updated: April 19, 2026
Application No. 18/330,233

ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREOF

Non-Final OA §102§103
Filed
Jun 06, 2023
Examiner
PRASAD, NEIL R
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Siliconware Precision Industries Co. Ltd.
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
591 granted / 694 resolved
+17.2% vs TC avg
Moderate +9% lift
Without
With
+9.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
26 currently pending
Career history
720
Total Applications
across all art units

Statute-Specific Performance

§103
56.1%
+16.1% vs TC avg
§102
28.7%
-11.3% vs TC avg
§112
4.7%
-35.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 694 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/24/2026 has been entered. Response to Arguments Applicant's arguments filed 2/24/2026 have been fully considered but they are not persuasive. Applicant amends the claims to introduce a “heat dissipation body” that is between the electronic element and heat dissipation structure. However, Tain’s thermal conductive layer (106) includes two portions: a lower portion (106 lower), in contact with the top surface of the electronic element (104) which reads on the claimed “heat dissipation body” and an upper wider portion (106 upper), which reads on the claimed “heat dissipation structure.” This forms the exact T-shaped structure (26/25) provided in Figure 2D of applicant’s disclosure, where the lower body portion (25) laterally overlaps with the circuit area (23), and the upper structure (26) is above and wider than the lower body (25). Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 5-13, and 15-18, and 20 are rejected under 35 U.S.C. 102(1)(a) as being anticipated by Tain et al. (US Publication No. 2009/0294947). Regarding claim 1, Tain discloses an electronic package, comprising: an encapsulation layer (110) a first electronic element (104 above) embedded in the encapsulation layer (110) a second electronic element (104 below) embedded in the encapsulation layer (110) and spaced apart from the first electronic element (104 above) a circuit structure (122) disposed on the encapsulation layer (110) and electrically connected (connected through vias 116) to the first electronic element (104 above) and the second electronic element (104 below), wherein the circuit structure (112) has a hollow area corresponding to the first electronic element (104 above) a heat dissipation structure (106 upper portion) disposed in the hollow area (126 displaced by 106) and thermally connected to the first electronic element (104 above), wherein a heat dissipation body (106 lower portion) is disposed in the hollow area and between the first electronic component (104) and the heat dissipation structure (106 upper portion) PNG media_image1.png 322 686 media_image1.png Greyscale Regarding claim 2, Tain discloses the heat dissipation structure (106) includes a heat dissipation member (106) disposed in the hollow area (displaced by 106) and a heat dissipation material filled in the hollow area (Figure 1B). Regarding claim 3, Tain discloses the heat dissipation member (106) is a metal frame (106 is inline with the outer frame portion surrounding 102 in Figures 4B-4C). Regarding claim 5, Tain discloses the heat dissipation structure (106) is in a shape of a plug and inserted into the hollow area (Figures 4B-4C). Regarding claim 6, Tain discloses the hollow area (displaced by 106) penetrates through the circuit structure (122) (Figure 1B). Regarding claim 7, Tain discloses the hollow area (displaced by 106) is free from penetrating through the circuit structure (Figure 1A). Regarding claim 8, Tain discloses the heat dissipation structure (106) is extended on the circuit structure (122). Regarding claim 9, Tain discloses the first electronic element (104) is provided with a heat dissipation body (106/128) corresponding to the hollow area (displaced by 106). Regarding claim 10, Tain discloses the heat dissipation body (106) is a heat sink (128). Regarding claim 11, Tain discloses a method of manufacturing an electronic package, comprising: embedding a first electronic element (104 above) and a second electronic element (104 below) in an encapsulation layer (110) in a manner of being spaced apart from each other forming a circuit structure (122) on the encapsulation layer (110) to electrically connect the circuit structure (122) to the first electronic element (104 above) and the second electronic element (104 below), wherein the circuit structure (122) has a hollow area (displaced by 104) corresponding to the first electronic element (104 above) disposing a heat dissipation structure (106 upper portion) in the hollow area to connect the heat dissipation structure to the first electronic element, wherein a heat dissipation body (106 lower portion) is disposed on the first electronic element (104) and in the hollow area (within encapsulant 110 and displaced by 106) Regarding claim 12, Tain discloses the heat dissipation structure (106) includes a heat dissipation member (106) disposed in the hollow area (displaced by 106) and a heat dissipation material filled in the hollow area (Figure 1B). Regarding claim 13, Tain discloses the heat dissipation member (106) is a metal frame (106 is inline with the outer frame portion surrounding 102 in Figures 4B-4C). Regarding claim 15, Tain discloses the heat dissipation structure (106) is in a shape of a plug and inserted into the hollow area (Figures 4B-4C). Regarding claim 16, Tain discloses the hollow area (displaced by 106) penetrates through the circuit structure (122) (Figure 1B). Regarding claim 17, Tain discloses the hollow area (displaced by 106) is free from penetrating through the circuit structure (Figure 1A). Regarding claim 18, Tain discloses the heat dissipation structure (106) is extended on the circuit structure (122). Regarding claim 20, Tain discloses the heat dissipation body (106) is a heat sink (128). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Tain et al. (US Publication No. 2009/0294947) in view of Choi et al. (US Publication No. 2020/0144192). Regarding claim 4, Tain discloses the limitations as discussed in the rejection of claim 2 above. Tain is silent regarding the heat dissipation material is liquid metal. However, Choi discloses a heat sink which includes a liquid cooled plate and a low melting point metal bonding material (paragraph 71). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the heat dissipation material of Tain to include liquid metal, as taught by Choi, since it can improve adhesion and therefore the effectiveness of the heat dissipation unit (paragraph 108). Regarding claim 14, Tain discloses the limitations as discussed in the rejection of claim 12 above. Tain is silent regarding the heat dissipation material is liquid metal. However, Choi discloses a heat sink which includes a liquid cooled plate and a low melting point metal bonding material (paragraph 71). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the heat dissipation material of Tain to include liquid metal, as taught by Choi, since it can improve adhesion and therefore the effectiveness of the heat dissipation unit (paragraph 108). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NEIL R PRASAD whose telephone number is (571) 270-3129. The examiner can normally be reached M-F 9am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /N.R.P/ 3/5/2026Examiner, Art Unit 2897 /JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jun 06, 2023
Application Filed
Aug 06, 2025
Non-Final Rejection — §102, §103
Nov 10, 2025
Response Filed
Nov 18, 2025
Final Rejection — §102, §103
Feb 24, 2026
Request for Continued Examination
Mar 04, 2026
Response after Non-Final Action
Mar 05, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598873
DISPLAY PANEL AND ELECTRONIC DEVICE INCLUDING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12599014
PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Apr 07, 2026
Patent 12575287
Foldable Display Apparatus
2y 5m to grant Granted Mar 10, 2026
Patent 12568836
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Mar 03, 2026
Patent 12563727
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+9.2%)
2y 3m
Median Time to Grant
High
PTA Risk
Based on 694 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month