Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II (original claims 17-20 and new claims 21-38) in the reply filed on December 22, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 27-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US 11031457).
Regarding claim 27, Li discloses a method for forming an integrated chip, comprising:
depositing a conductive base layer (i.e. FEOL) over a semiconductor substrate (106) [Fig. 1 and col. 4, lines 45-48];
depositing a first dielectric layer (104) over the conductive base layer [Fig. 1];
performing an etching process on the first dielectric layer (104) to form a plurality of openings (trenches for layer 102) in the first dielectric layer (104), wherein the plurality of openings expose a top surface of the conductive base layer (106) [Fig. 1, col. , lines 59-67, and col. 4, lines 1-7 and 45-48];
forming a plurality of conductive pillar structures (102) in the plurality of openings and on the conductive base layer [Fig. 1, col. , lines 59-67, and col. 4, lines 1-7 and 45-48];
removing the first dielectric layer (104) [Fig. 2]; and
forming a plurality of capacitor dielectric layers (912,914,916) and a plurality of conductive layers (904,906,908,910) over and around the plurality of conductive pillar structures (102), wherein adjacent conductive layers (904,906,908,910) in the plurality of conductive layers are separated by a corresponding capacitor dielectric layer (912,914,916) in the plurality of capacitor dielectric layers [Fig. 9].
Regarding claim 28, Li discloses wherein forming the plurality of conductive pillar structures comprises: depositing a conductive material (102) in the plurality of openings and over the first dielectric layer; and performing a planarization process on the conductive material [Fig. 1, col. 3, lines 59-67, and col. 4, lines 1-7].
Regarding claim 29, Li discloses wherein the conductive pillar structures (102) are formed in the plurality of openings by chemical vapor deposition or electroplating [col. 3, lines 59-60: “metallization techniques”. And, col. 6, lines 13-17, describes electroplating as one of the known “metallization techniques”].
Allowable Subject Matter
Claims 17-26 and 33-36 are allowed.
Claims 30-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
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