DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 08 Jun 2023 for application number 18/331,745. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-16 and 21-24 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-16 and 21-24, drawn to Invention I., Species I. in the reply filed on 27 Jan 2026 is acknowledged.
Non-elected claims 17-20 have been cancelled.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 requires that source/drain portions are formed before a bottom portion. However, the Specification does not provide support for this. On the contrary, the bottom portion is formed before the source/drain portions.
Dependent claims 2-8 are rejected because they inherit the deficiency.
Claim 3 recites, the one of the two source/drain portions is entirely separated from the protrusion through the bottom portion. The Drawings clearly show that the source/drain portions are not separated from the protrusion, i.e. fin (see Fig. 8, for example), but contact it.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 requires that source/drain portions are formed before a bottom portion. However, it is unclear how this is possible, when the bottom portions are located under the source/drain portions, i.e. the bottom portions would have to formed before the source/drain portions.
Dependent claims 2-8 are rejected because they inherit the deficiency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7, 9-10, 13, and 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. [hereinafter as Yu] (US 2021/0408247 A1).
In reference to claim 1, Yu teaches A method for manufacturing a semiconductor structure, comprising:
forming a channel portion [first and second nanostructures 54 and 55; Fig. 9A, para 0040] on a protrusion [fin 66; Fig. 9A, para 0040];
forming two source/drain portions [source/drain regions are formed in the first and second recesses 86 and 87; Fig. 9C, para 0040; see Fig. 12C, source/drain regions 92 on either side of 66; para 0046] on the protrusion [66] respectively at two opposite sides of the channel portion [54/55], the two source/drain portions [92] including a first semiconductor material that is doped with dopant impurities [paras 0049-0051 disclose that 92 are doped semiconductor material]; and
forming a bottom portion [second epitaxial material 89; Fig. 12C, paras 0046-0047] which is disposed between the protrusion [66] and one of the two source/drain portions [92], the bottom portion [89] including a second semiconductor material [para 0047 discloses that 89 may be silicon germanium] that is different from the first semiconductor material [paras 0049-0051 disclose that 92 may be silicon, for example] and that is capable of trapping the dopant impurities when the dopant impurities in the first semiconductor material diffuse toward the protrusion [since 89 and 92 are different materials, the silicon germanium of 89, for instance, would exhibit the claimed trapping property].
In reference to claim 2, Yu teaches The method as claimed in claim 1, wherein the two source/drain portions [92] are spaced apart from each other in a first direction [horizontal direction in Fig. 12C], the channel portion [54/*55] including channel layers spaced apart from each other in a second direction [vertical direction in Fig. 12C] transverse to the first direction, a bottommost one of the channel layers being spaced apart from the protrusion in the second direction [bottom 54/55 is spaced apart from 66 in the vertical direction].
In reference to claim 3, Yu teaches The method as claimed in claim 2, wherein: the bottom portion [89] is separated from the channel layers [54/55] through the one of the two source/drain portions [92]; and
the one of the two source/drain portions [92] is entirely separated from the protrusion [bottom region of 66, i.e. the substrate portion] through the bottom portion [89].
In reference to claim 4, Yu teaches The method as claimed in claim 2, wherein the bottom portion [89] has an upper surface at a level lower than [89 has an upper surface that is lower than a lower surface of bottommost 54/55] a level of a lower surface of the bottommost one of the channel layers [54/55].
In reference to claim 7, Yu teaches The method as claimed in claim 1, wherein the first semiconductor material includes a group IV element [paras 0049-0051 disclose that 92 may be silicon, a group IV element] and the dopant impurities doped in the group IV element [paras 0049-0051 disclose that 92 are doped semiconductor material], the dopant impurities including a group III element or a group V element [paras 0049-0051 disclose that 92 are doped semiconductor material; the dopants may be boron or phosphorus, for example (Group III and V elements, respectively)].
In reference to claim 9, Yu teaches A method for manufacturing a semiconductor structure, comprising:
forming a protrusion [fin 66; Fig. 9A, para 0040] on a substrate [substrate 50; Fig. 9A, para 0041], the protrusion [66] having a p-region and an n-region displaced from the p-region [paras 0018-0019 disclose the regions, i.e. protrusions, may be n or p-type];
forming a first device [first and second nanostructures 54 and 55; Fig. 9A, para 0040] on the p-region [paras 0018-0019 disclose the regions, i.e. protrusions, may be n or p-type] of the protrusion [66], the first device including a first channel portion [54/55],
two first source/drain portions [source/drain regions are formed in the first and second recessed 86 and 87; Fig. 9C, para 0040; see Fig. 12C, source/drain regions 92 on either side of 66; para 0046] including a p-type semiconductor material that is doped with a p-type dopant [para 0050 discloses 92 may be p-type], and
a first bottom portion [second epitaxial material 89; Fig. 12C, paras 0046-0047] which is disposed between the protrusion [66] and one of the two first source/drain portions [92], and which is capable of trapping the p-type dopant when the p-type dopant in the one of the two first source/drain portions diffuses toward the protrusion [since 89 and 92 are different materials, the silicon germanium of 89, for instance, would exhibit the claimed trapping property]; and
forming a second device [first and second nanostructures 54 and 55; Fig. 9A, para 0040] on the n-region [paras 0018-0019 disclose the regions, i.e. protrusions, may be n or p-type] of the protrusion [66], the second device including
a second channel portion [54/55],
two second source/drain portions [92] including an n-type semiconductor material that is doped with an n-type dopant [para 0050 discloses 92 may be n-type], and
a second bottom portion [89] which is disposed between the protrusion [66] and one of the two second source/drain portions [92], and which is capable of trapping the n-type dopant when the n-type dopant in the one of the two second source/drain portions diffuses toward the protrusion [since 89 and 92 are different materials, the silicon germanium of 89, for instance, would exhibit the claimed trapping property].
In reference to claim 10, Yu teaches The method as claimed in claim 9, wherein the first bottom portion [89] and the second bottom portion [89] are made of a same material [para 0047 discloses that 89 may be silicon germanium].
In reference to claim 13, Yu teaches The method as claimed in claim 9, wherein the first channel portion [54/55] and the second channel portion [54/55] are simultaneously formed [these are simultaneously formed; Fig. 9A, para 0040], and
the first bottom portion [89] and the second bottom portion [89] are simultaneously formed [89 are simultaneously formed; Fig. 12C, paras 0046-0047] before forming [89 is formed before 92] the two first source/drain portions [92] and the two second source/drain portions [92].
In reference to claim 15, Yu teaches The method as claim in claim 9, wherein the two first source/drain portions [92] are respectively disposed at two opposite sides of the first channel portion [54/55] in a first direction [horizontal direction in Fig. 12C], the two second source/drain portions [92] being respectively disposed at two opposite sides of the second channel portion [54/55] in the first direction [horizontal direction in Fig. 12C], each of the first channel portion [54/55] and the second channel portion [54/55] including channel layers [54/55] spaced apart from each other in a second direction transverse to the first direction [vertical direction in Fig. 12C], the second direction being normal [vertical direction perpendicular to surface of 50] to an upper surface of the substrate [50].
In reference to claim 16, Yu teaches The method as claimed in claim 15, wherein the first bottom portion [89] is separated from the channel layers [54/55] of the first channel portion through the one of the two first source/drain portions [92], and
the second bottom portion [89] is being separated from the channel layers [54/55] of the second channel portion through the one of the two second source/drain portions [92].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Kim et al. [hereinafter as Ha] (US 2022/0181498 A1).
In reference to claim 5, Yu teaches invention of claim 2.
Yu teaches The method as claimed in claim 2, further comprising:
forming a gate structure [dummy gates 76; Fig. 6C, para 0034] around the channel layers [54/55]; and
forming pairs of inner spacers [inner spacers 90; Fig. 11C, para 0048] that are disposed to separate the gate structure [76] from the two source/drain portions [92].
However, Yu does not explicitly teach one inner spacer in a bottommost one of the pairs of inner spacers being covered by the bottom portion.
Yu and Ha teach one inner spacer [90] in a bottommost one of the pairs of inner spacers [90] being covered by the bottom portion [semiconductor blocking film 151 would cover the spacer of Yu; Fig. 2, para 0102].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yu and Ha before the effective filing date of the claimed invention, to include the semiconductor blocking film as disclosed by Ha into the semiconductor device of Yu in order to obtain a bottom layer that covers a bottommost inner spacer.
One of ordinary skill in the art would be motivated to obtain a bottom layer that covers a bottommost inner spacer to provide the predictable result of preventing short-channel leakage and preserving threshold voltage.
Claim(s) 6 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Smith et al. [hereinafter as Smith] (US 2024/0047342 A1).
In reference to claim 6, Yu teaches the invention of claim 2.
However, Yu does not explicitly teach The method as claimed in claim 2, wherein the bottom portion has a thickness ranging from 0.5 nm to 10 nm.
Yu and Smith teach wherein the bottom portion [89 of Yu] has a thickness ranging from 0.5 nm to 10 nm [Smith, para 0040 discloses a barrier layer that minimizes dopant diffusion that can be, for example, 10-40 angstroms or 2-5 angstroms thick, which are within the claimed range].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yu and Smith before the effective filing date of the claimed invention, to include the barrier layer thickness as disclosed by Smith into the semiconductor device of Yu in order to obtain a bottom layer that is between 0.5 and 10 nm.
One of ordinary skill in the art would be motivated to obtain a bottom layer that is between 0.5 and 10 nm to provide the predictable result of providing a layer thick enough to minimize diffusion but thin enough to minimize impact on resistance [Smith, para 0040].
In reference to claim 14, Yu teaches the invention of claim 9.
However, Yu does not explicitly teach The method as claimed in claim 9, wherein one of the first bottom portion and the second bottom portion has a thickness ranging from 0.5 nm to 10 nm.
Yu and Smith teach wherein one of the first bottom portion [89 of Yu] and the second bottom portion [89 of Yu] has a thickness ranging from 0.5 nm to 10 nm [Smith, para 0040 discloses a barrier layer that minimizes dopant diffusion that can be, for example, 10-40 angstroms or 2-5 angstroms thick, which are within the claimed range].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yu and Smith before the effective filing date of the claimed invention, to include the barrier layer thickness as disclosed by Smith into the semiconductor device of Yu in order to obtain a bottom layer that is between 0.5 and 10 nm.
One of ordinary skill in the art would be motivated to obtain a bottom layer that is between 0.5 and 10 nm to provide the predictable result of providing a layer thick enough to minimize diffusion but thin enough to minimize impact on resistance [Smith, para 0040].
Claim(s) 8, 11-12, and 21-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Kim et al. [hereinafter as Kim] (US 2024/0251569 A1).
In reference to claim 8, Yu teaches the invention of claim 1.
However, Yu does not explicitly teach The method as claimed in claim 1, wherein the second semiconductor material is silicon doped with carbon, antimony, gallium, or combinations thereof.
Yu and Kim teach wherein the second semiconductor material is silicon [Yu, para 0047 discloses that 89 may be made of silicon] doped with carbon, antimony, gallium, or combinations thereof [Kim, para 0021 discloses silicon doped with carbon, antimony, gallium, etc.].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yu and Kim before the effective filing date of the claimed invention, to include the doping as disclosed by Kim into the semiconductor device of Yu in order to obtain a bottom layer that is silicon doped with carbon, antimony, or gallium.
One of ordinary skill in the art would be motivated to obtain a bottom layer that is silicon doped with carbon, antimony, or gallium to provide the predictable result of optimum diffusion resistance due to these elements’ slow diffusion rates and unique atomic sizes.
In reference to claim 11, Yu teaches the invention of claim 9.
Yu teaches The method as claimed in claim 9, wherein each of the first bottom portion [89] and the second bottom portion [89] includes a group IV semiconductor material [para 0047 discloses that 89 contains carbon].
However, Yu does not explicitly teach trapping elements doped in the group IV semiconductor material, the trapping elements including carbon, antimony, gallium, or combinations thereof.
Kim teaches trapping elements doped in the group IV semiconductor material, the trapping elements including carbon, antimony, gallium, or combinations thereof [para 0021 discloses silicon doped with carbon, antimony, gallium, etc.].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yu and Kim before the effective filing date of the claimed invention, to include the doping as disclosed by Kim into the semiconductor device of Yu in order to obtain a bottom layer that is silicon doped with carbon, antimony, or gallium.
One of ordinary skill in the art would be motivated to obtain a bottom layer that is silicon doped with carbon, antimony, or gallium to provide the predictable result of optimum diffusion resistance due to these elements’ slow diffusion rates and unique atomic sizes.
In reference to claim 12, Yu and Kim teach the invention of claim 11.
Although Kim does not explicitly teach The method as claim in claim 11, wherein the trapping elements are in an atomic percentage ranging from 0.02% to 10% based on total atoms of the group IV semiconductor material and the trapping elements, it would have been obvious to one of ordinary skill in the art to dope at these percentages, as these percentages are well-known in the art (known as “degenerate doping”) as percentages provide reliable methods for pinning dopant atoms in place without causing the semiconductor’s lattice to completely break down or lose its electrical activity.
In reference to claim 21, Yu teaches A method for manufacturing a semiconductor structure, comprising:
forming a laminated structure on a protrusion [layers including first and second nanostructures 54 and 55 to make fin 66; Fig. 9A, para 0040], the laminated structure including a channel portion [54/55] and a sacrificial portion, the channel portion including channel layers, the sacrificial portion including sacrificial layers which are disposed to alternate with the channel layers [para 0019 outlines alternating semiconductor layers; one set of layers is removed and the other set may be patterned to be the channel layers];
forming a dummy gate portion [dummy gates 76; Fig. 6C, para 0034] over the laminated structure [layers including first and second nanostructures 54 and 55];
patterning the laminated structure to form two source/drain recesses [recesses 86 and 87; Fig. 9C, para 0040 in the laminated structure [layers including first and second nanostructures 54 and 55];
depositing two bottom portions [second epitaxial material 89; Fig. 12C, paras 0046-0047] respectively in the two source/drain recesses [86/87]; and
depositing two source/drain portions [source/drain regions are formed in the first and second recesses 86 and 87; Fig. 9C, para 0040; see Fig. 12C, source/drain regions 92 on either side of 66; para 0046] respectively on the two bottom portions [89] so as to respectively fill the two source/drain recesses [86/87], the two source/drain portions [92] including a second semiconductor material [paras 0049-0051 disclose that 92 may be silicon, for example] which is doped with dopant impurities [paras 0049-0051 disclose that 92 are doped semiconductor material].
However, Yu does not explicitly teach the two bottom portions including a first semiconductor material which is doped with trapping elements; the dopant impurities being different from the trapping elements.
Yu and Kim teach the two bottom portions [89 of Yu] including a first semiconductor material which is doped with trapping elements [Kim, para 0021 discloses silicon doped with carbon, antimony, gallium, etc.]; the dopant impurities [Yu, paras 0049-0051 disclose that 92 are doped semiconductor material; the dopants may be boron or phosphorus, for example] being different from the trapping elements [Kim, para 0021 discloses silicon doped with carbon, antimony, gallium, etc.].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Yu and Kim before the effective filing date of the claimed invention, to include the doping as disclosed by Kim into the semiconductor device of Yu in order to obtain a bottom layer that is silicon doped with carbon, antimony, or gallium.
One of ordinary skill in the art would be motivated to obtain a bottom layer that is silicon doped with carbon, antimony, or gallium to provide the predictable result of optimum diffusion resistance due to these elements’ slow diffusion rates and unique atomic sizes.
In reference to claim 22, Yu and Kim teach the invention of claim 21.
Yu teaches The method as claimed in claim 21, wherein the two source/drain recesses [86/87] extend through the laminated structure [layers including first and second nanostructures 54 and 55] into the protrusion [66], such that the two bottom portions [89] are formed in the protrusion [66].
In reference to claim 23, Yu and Kim teach the invention of claim 21.
Yu teaches The method as claimed in claim 21, wherein the two bottom portions [89] are spaced apart from a bottommost one of the channel layers [bottom 54/55 is spaced apart from 66 in the vertical direction].
In reference to claim 24, Yu and Kim teach the invention of claim 21.
Kim teaches The method as claimed in claim 21, wherein the trapping elements include carbon, antimony, gallium, or combinations thereof [para 0021 discloses silicon doped with carbon, antimony, gallium, etc.].
Examiner’s Note
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0).
Chuang et al. (US-20230065208-A1) discloses the forming of bottom portions [Fig. 6I].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW CHUNG whose telephone number is (571)272-5237. The examiner can normally be reached M-F 9-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDREW CHUNG/
Examiner, Art Unit 2898
Prosecution Insights