Attorney Docket Number: 083120-8017US01
Filing Date: 06/09/2023
Claimed Priority Date: 06/13/2022 (CN 202210661400.1)
Inventors: Choi et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 11/24/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 11/24/2025 in reply to the previous Office action mailed on 08/25/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-3, 5, and 7-10.
Initial Remarks
With regards to all page, paragraph, and/or line citations from non-U.S. foreign references, please refer to the original non-English versions of the documents, which are attached to this Office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2023/0065147) in view of Braganca, Jr. (US 2021/0296268).
Regarding claim 1, Wang (see, e.g., figs. 1A-1H and 2A-2F) shows most aspects of the instant invention, including a method for forming a semiconductor device 10, comprising:
providing a substrate SUB;
providing a first semiconductor die 100 having a first die surface (side of 100 closest to SUB) and a second die surface RS opposite to the first die surface, wherein the semiconductor die is singulated from a semiconductor wafer 110’ (see, e.g., par.0028);
attaching the first die surface to the substrate via an interconnect structure 170/180 comprising solder 180 (see, e.g., pars.0024/ll.24-25 and 0027/ll.1-3);
reflowing the solder of the interconnect structure after attaching the first die surface to the substrate (see, e.g., par.0032/ll.10-13)
after the reflowing the solder of the interconnect structure (see, e.g., par.0032/ll.10-13), forming a back side metallization (BSM) layer 202 on the second die surface;
providing a thermal interface material (TIM) layer 204 having a first TIM surface (side of 204 closest to SUB) and a second TIM surface (side of 204 farthest from SUB) opposite to the first TIM surface;
attaching the first TIM surface to the BSM layer; and
attaching a heatsink 208/300 to the second TIM surface (see, e.g., par.0050/ll.19-22)
Although Wang shows most aspects of the instant invention, including that a reflow process is performed on Wang’s solder-comprising interconnect structure after Wang’s die is connected via Wang’s solder-comprising interconnect structure to Wang’s substrate (see, e.g., par.0032/ll.10-13), Wang fails to explicitly specify the exact method for reflowing the solder of the interconnect structure, including if Wang’s second die surface is irradiated with a laser beam, wherein the laser beam passes through the semiconductor die. Braganca, Jr., in the same field of endeavor and in a similar device to Wang, also teaches solder to be suitable material for interconnect structures 114 connecting a die 104 and a substrate 120 (see, e.g., Braganca, Jr.: fig. 2a and par.0006/ll.6-12). Braganca, Jr., further teaches that using a laser beam 134 to irradiate the second surface (top of 104) of a die 104, so as to reflow the solder of the interconnect structure, can mount the die to the substrate in a shorter time cycle while reducing the likelihood of damaging the die (see, e.g., Braganca, Jr.: fig. 2a and par.0006/ll.6-12).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Wang’s already-desired reflow process comprise irradiating Wang’s second die surface with a laser beam, such that the laser beam passes through the semiconductor die and reflows the solder of the interconnect structure, wherein it is recognized that reflowing the solder of the interconnect structure after connecting Wang’s die to Wang’s substrate is already desired and taught by Wang, as taught by Braganca, Jr., so as to mount Wang’s die to Wang’s substrate in a shorter time cycle while reducing the likelihood of damaging Wang’s die.
Accordingly, since Wang expresses that Wang’s reflow process is initiated/performed before forming Wang’s BSM layer (see, e.g., par.0032/ll.10-13), it would be further apparent that the reflow process comprising laser beam irradiation, as taught by Braganca, Jr. to mount Wang’s die to Wang’s substrate in a shorter time cycle while reducing the likelihood of damaging Wang’s die, would subsequently necessarily teach the limitation “after irradiating the second die surface with the laser beam, forming a back side metallization (BSM) layer on the second die surface”, wherein “after reflowing the solder of the interconnect structure” is replaced by “after irradiating the second die surface with the laser beam”, as taught by Braganca, Jr..
Regarding claim 2, Wang (see, e.g., figs. 1A-1H and 2A-2F) shows that providing the semiconductor die comprises:
providing the semiconductor wafer 100’ comprising the semiconductor die 100;
singulating the semiconductor die from the semiconductor wafer (see, e.g., par.0028); and
identifying the semiconductor die as a known good die (KGD) by inspection and electrical testing (see, e.g., par.0017)
Regarding claim 3, Wang (see, e.g., figs. 2A-2F) shows forming an underfill encapsulant UF between the semiconductor die 100 and the substrate SUB and surrounding the interconnect structure 170/180.
Regarding claim 8, Wang (see, e.g., par.0036/ll.10-11) shows that the TIM layer 204 comprises indium, or an indium-silver alloy.
Regarding claim 9, Wang (see, e.g., figs. 2A-2F) shows that the heatsink 208/300 comprises a lid 300 and a surface finish layer 208 attached the lid, and the heatsink is attached to the TIM layer 204 via the surface finish layer.
Claims 1, 3, 5, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Bozorg-Grayeli (US 2021/0225729) in view of Wang and Braganca, Jr..
Regarding claim 1, Bozorg-Grayeli (see, e.g., figs. 1 and 10A-10F) shows most aspects of the instant invention, including a method 100 for forming a semiconductor device 1001, comprising:
providing a substrate 210;
providing a semiconductor die 205 having a first die surface (side of 205 closest to 210) and a second die surface (side of 205 farthest from 210) opposite to the first die surface;
attaching the first die surface to the substrate via an interconnect structure 211 comprising solder (see, e.g., par.0029/ll.9-10);
performing a reflow process, wherein the reflow process is performed on the interconnect structure comprising solder (see, e.g., fig. 10D and par.0051/ll.4-5);
after initiating the reflow process, forming a back side metallization (BSM) layer 1051 on the second die surface (see, e.g., par.0050/ll.1-4);
providing a thermal interface material (TIM) layer 1050 having a first TIM surface (side of 1050 closest to 205) and a second TIM surface (side of 1050 farthest from 205) opposite to the first TIM surface;
attaching the first TIM surface to the BSM layer (see, e.g., fig. 10D); and
attaching a heatsink 890 to the second TIM surface
Although Bozorg-Grayeli teaches most aspects of the instant invention, and further teaches that Bozorg-Grayeli’s semiconductor device may comprise more than one die (see, e.g., par.0029/ll.4-5), Bozorg-Grayeli fails to explicitly specify that Bozorg-Grayeli’s die is singulated from a semiconductor wafer. Wang, in the same field of endeavor, teaches a process for providing a semiconductor die, wherein Wang teaches that the semiconductor die is singulated from a semiconductor wafer (see, e.g., Wang: figs. 1A-1F and par.0028). Wang teaches that singulating a semiconductor die from a semiconductor wafer effectively allows the rendering of a plurality of semiconductor dies from the singular wafer near-simultaneously, thereby asserting the efficient production of a plurality of dies (see, e.g., Wang: par.0028).
Wang is evidence showing that one of ordinary skill in the art would appreciate that a semiconductor die singulated from a semiconductor wafer would be equivalent to a semiconductor die provided by another method, and that such differences would result in no unexpected changes in the performance of the semiconductor device of Bozorg-Grayeli. That is, the semiconductor dies of both Wang and Bozorg-Grayeli would yield the predictable result of providing a suitable integrated circuit structure capable of mechanical and electrical integration with various other conductive components of a semiconductor device.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a semiconductor die singulated from a semiconductor wafer, as taught by Wang, or a semiconductor die provided by another method, as taught by Bozorg-Grayeli, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable integrated circuit structure capable of mechanical and electrical integration with various other conductive components of a semiconductor device. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Additionally, Wang is evidence that at the time of filing the invention it would have been obvious that one of ordinary skill in the art would find particular incentive to provide a semiconductor die wherein the semiconductor die is singulated from a semiconductor wafer, so as to effectively render a plurality of semiconductor dies near-simultaneously, wherein Bozorg-Grayeli already teaches and appreciates the inclusion of multiple semiconductor dies in a semiconductor device, thereby improving the efficiency of die production.
Furthermore, although Bozorg-Grayeli shows most aspects of the instant invention, including that a reflow process is performed on Bozorg-Grayeli’s solder-comprising interconnect structure after Bozorg-Grayeli’s die is connected via Bozorg-Grayeli’s solder-comprising interconnect structure to Bozorg-Grayeli’s substrate (see, e.g., fig. 10D and par.0051/ll.4-5), that laser beams may be effectively employed in Bozorg-Grayeli’s semiconductor device production (see, e.g., par.0044/ll.15), and that the solder of solder-comprising interconnect structures may be reflowed (see, e.g., par.0051/ll.4-5), Bozorg-Grayeli fails to explicitly specify that Bozorg-Grayeli’s solder of the interconnect is reflowed and the exact method for reflowing the solder of the interconnect structure, including if Bozorg-Grayeli’s second die surface is irradiated with a laser beam, wherein the laser beam passes through the semiconductor die. Braganca, Jr., in the same field of endeavor and in a similar device to Bozorg-Grayeli, also teaches solder to be suitable material for interconnect structures 114 connecting a die 104 and a substrate 120 (see, e.g., Braganca, Jr.: fig. 2a and par.0006/ll.6-12). Braganca, Jr., further teaches that using a laser beam 134 to irradiate the second surface (top of 104) of a die 104, so as to reflow the solder of the interconnect structure, can mount the die to the substrate in a shorter time cycle while reducing the likelihood of damaging the die (see, e.g., Braganca, Jr.: fig. 2a and par.0006/ll.6-12).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Bozorg-Grayeli’s reflow process comprise irradiating Bozorg-Grayeli’s second die surface with a laser beam, such that the laser beam passes through the semiconductor die and reflows the solder of the interconnect structure, wherein it is recognized that reflowing the solder of interconnect structures is already taught by Bozorg-Grayeli (see, e.g., par.0051/ll.4-5), as taught by Braganca, Jr., so as to mount Bozorg-Grayeli’s die to Bozorg-Grayeli’s substrate in a shorter time cycle while reducing the likelihood of damaging Bozorg-Grayeli’s die.
Accordingly, since Bozorg-Grayeli expresses that Bozorg-Grayeli reflow process is initiated before forming Bozorg-Grayeli’s BSM layer (see, e.g., par.0050/ll.1-4), it would be further apparent that the reflow process comprising laser beam irradiation, as taught by Braganca, Jr. to mount Bozorg-Grayeli’s die to Bozorg-Grayeli’s substrate in a shorter time cycle while reducing the likelihood of damaging Bozorg-Grayeli’s die, would subsequently necessarily teach the limitation “after irradiating the second die surface with the laser beam, forming a back side metallization (BSM) layer on the second die surface”, wherein “after initiating the reflow process” is replaced by “after irradiating the second die surface with the laser beam”, as taught by Braganca, Jr..
Regarding claim 3, Bozorg-Grayeli (see, e.g., figs. 10A-10F) shows forming an underfill encapsulant 230 between the semiconductor die 205 and the substrate 210 and surrounding the interconnect structure 211.
Regarding claim 5, Bozorg-Grayeli (see, e.g., par.0050/ll.12-13) shows that the BSM layer 1051 comprises one or more materials selected from a group consisting of silver, stainless steel, and copper (e.g., copper).
Regarding claim 9, Bozorg-Grayeli (see, e.g., fig. 10F) shows that the heatsink 890 comprises a lid 880 and a surface finish layer 870 attached to the lid, and the heatsink is attached to the TIM layer 1050 via the surface finish layer.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Wang/Braganca, Jr. in view of Xiao (CN 103441109A) and Bozorg-Grayeli.
Regarding claim 5, Wang/Braganca, Jr. shows most aspects of the instant invention (see paragraphs 6-9 above). Wang further teaches that Wang’s BSM layer comprises a metal material including gallium, and that Wang’s metal material is not necessarily limited to only comprising gallium (see, e.g., pars.0035/ll.4 and claim 3 of Wang, wherein the use of phrases such as “includes gallium” and “comprises gallium” indicate that Wang’s BSM layer is not necessarily limited to gallium alone). Wang, however, fails to explicitly specify that Wang’s BSM layer comprises one or more materials selected from a group consisting of silver, stainless steel, and copper. Xiao, in the same field of endeavor, teaches that BSM layers may comprise multiple layers of varying materials, and teaches a multi-layer BSM layer comprising a copper layer closest to a TIM layer (see, e.g., Xiao: figs. 4 and 9-10 and pars.0024/ll.1-2 and 6-8). Furthermore, Bozorg-Grayeli, also in the same field of endeavor and in a similar device to Wang, teaches a method for forming a semiconductor device comprising forming a BSM layer including at minimum gallium, wherein Bozorg-Grayeli teaches that BSM layers comprising both gallium and copper function equivalently to BSM layers comprising at least gallium (see, e.g., Bozorg-Grayeli: fig. 10F and par.0050/ll.9 and 12-13).
Xiao is evidence showing that one of ordinary skill in the art would appreciate that a BSM layer comprising a single layer of gallium would be equivalent to a BSM layer comprising multiple layers, such as a BSM multi-layer structure including gallium and, e.g., copper, and that such differences would result in no unexpected changes in the performance of the semiconductor device of Wang. Furthermore, Bozorg-Grayeli is evidence showing that one of ordinary skill in the art would appreciate that a BSM layer comprising gallium would be equivalent to a BSM layer comprising gallium and copper, and that such differences would result in no unexpected changes in the performance of the semiconductor device of Wang. That is, the BSM layers of both Xiao and Wang or Bozorg-Grayeli and Wang would yield the predictable result of providing a suitable metal layer established between the backside of a semiconductor die and a TIM layer capable of appropriately supporting the TIM layer and a heatsink.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have either a BSM layer comprising multiple layers, including gallium and, e.g., copper, as taught by Xiao, or a BSM layer comprising a single layer of gallium, as taught by Wang, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable metal layer established between the backside of a semiconductor die and a TIM layer capable of appropriately supporting the TIM layer and a heatsink. Additionally, it would have been alternatively obvious at the time of filing the invention to one of ordinary skill in the art to have either a BSM layer comprising gallium and copper, as taught by Bozorg-Grayeli, or a BSM layer comprising gallium, as taught by Wang, because these were recognized in the semiconductor art as equivalents for their use as BSM layer materials, and selecting among known equivalents would be within the level of ordinary skill in the art. Furthermore, both would yield the predictable result of providing a suitable metal layer established between the backside of a semiconductor die and a TIM layer capable of appropriately supporting the TIM layer and a heatsink. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Claims 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Wang/Braganca, Jr. in view of Xiao.
Regarding claim 7, Wang/Braganca, Jr. shows most aspects of the instant invention (see paragraphs 6-9 above). Wang further teaches that Wang’s TIM layer has a first TIM surface (side of 204 closest to SUB) and a second TIM surface (side of 204 farthest from SUB), wherein the first TIM surface is attached to the BSM layer and the heatsink is attached to the second TIM surface (see, e.g., figs. 2A-2F). Wang, however, fails to explicitly specify that soldering flux is formed on the first TIM surface and the second TIM surface, wherein the first TIM surface is attached to the BSM layer via the soldering flux on the first TIM surface, and the heatsink is attached to the second TIM surface via the soldering flux on the second TIM surface.
Xiao, in the same field of endeavor and in a similar device to Wang, teaches a method for forming a semiconductor device 1a comprising forming soldering flux 183 on a first TIM surface (bottom of 18) and a second TIM surface (top of 18), wherein the first TIM surface (bottom of 18) is attached to a BSM layer 16 via the soldering flux on the first TIM surface, and the heatsink 21, 20 is attached to the second TIM surface (top of 18) via the soldering flux on the second TIM surface (see, e.g., Xiao: figs. 4 and 9-10 and par.0038/ll.4-5). Xiao teaches that the inclusion of such soldering flux on the first and second TIM surfaces, such that the first TIM surface is attached to the BSM layer via the soldering flux on the first TIM surface and the heatsink is attached to the second TIM surface via the soldering flux on the second TIM surface, allows the soldering flux to act as oxide-removing material, which can promote bonding between layers by preventing bonding failures due to oxidation (see, e.g., Xiao: par.0030/ll.1-3 and 6-7).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Wang’s method further comprise forming soldering flux on Wang’s first TIM surface and second TIM surface, wherein the first TIM surface is attached to the BSM layer via the soldering flux on the first TIM surface, and the heatsink is attached to the second TIM surface via the soldering flux on the second TIM surface, as shown and taught by Xiao, so as to prevent bonding failures between Wang’s TIM surfaces and BSM layer or heatsink due to oxidation, thereby ensuring bonding reliability in Wang’s device.
Regarding claim 10, Wang/Braganca, Jr. shows most aspects of the instant invention (see paragraphs 6-9 above). Furthermore, Wang teaches that Wang’s TIM layer may comprise many materials, including, for example, solder (see, e.g., par.0036/ll.10-11). Wang, however, fails to explicitly specify that Wang’s method further comprises reflowing the TIM layer to solder to the TIM layer and the BSM layer together and solder the TIM layer and the heatsink together. Xiao, in the same field of endeavor and in a similar device to Wang, shows a method for forming a semiconductor device 1a comprising reflowing a TIM layer 18 to solder the TIM layer and a BSM layer 16 together and solder the TIM layer and a heatsink 21, 20 together (see, e.g., Xiao: figs. 4 and 9-10 and pars.0032/ll.1-3 and 0038/ll.6-8). Xiao teaches that reflowing a TIM layer to solder the TIM and other layers of a semiconductor device together results in the TIM and other layers being tightly joined, thereby asserting enhanced bonding, while simultaneously promoting the formation of respective intermetallic compounds between the TIM layer and other layers, e.g., the BSM layer and the heatsink (see, e.g., Xiao: figs. 4 and 9-10 and pars.0032/ll.1-3 and 0038/ll.6-8).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Wang’s method further comprise reflowing the TIM layer to solder to the TIM layer and the BSM layer together and solder the TIM layer and the heatsink together, as taught by Xiao, so as to better tightly join and enhance the bonding between Wang’s TIM and Wang’s BSM layer and heatsink while simultaneously promoting the formation of intermetallic compounds between Wang’s TIM layer and BSM layer and Wang’s TIM and heatsink, respectively.
Response to Arguments
Applicant’s amendments to the drawings have overcome the objections to the drawings put forth in the previous Office action mailed on 08/25/2025. Accordingly, the objections to the drawings put forth in the previous Office action are hereby withdrawn.
Applicant’s arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814