DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Claim Rejections – 35 U.S.C. § 102, filed 1/05/2026, with respect to the rejections of claims 1-2 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chen, Chun-Han et al. (Pub No. US 20210366786 A1) (hereinafter, Chen).
6. Applicant’s arguments, see Claim Rejections – 35 U.S.C. § 102, filed 1/05/2026, with respect to the rejections of claim 3 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chen, Chun-Han et al. (Pub No. US 20210366786 A1) (hereinafter, Chen) in view of Ching, Kuo-Cheng et al. (Pub No. US 20170053916 A1) (hereinafter, Ching).
7. Applicant’s arguments, see Claim Rejections – 35 U.S.C. § 102, filed 1/05/2026, with respect to the rejections of claim 9 under 35 U.S.C. § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chen, Chun-Han et al. (Pub No. US 20210366786 A1) (hereinafter, Chen) in view of Yang, Che-Yu et al. (Pub No. US 20200105938 A1) (hereinafter, Yang).
8. Applicant’s arguments with respect to claim(s) 4-7 and 10-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
9. Examiner notes the applicant did not respond to the objection of the specification and respectfully requests the applicant to submit a response to the objection of the specification.
For above mentioned reasons, the rejection is deemed proper and considered final.
Specification
10. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“FinFET Device with Dielectric Features for Parasitic Capacitance Reduction”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
12. Claims 1-2 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, Chun-Han et al. (Pub No. US 20210366786 A1) (hereinafter, Chen).
Chen, Fig 2: Fin structure arising from a substrate
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Re Claim 1, (Currently Amended) Chen teaches a semiconductor structure, comprising:
a fin structure (Fins; 52; Fig 2; ¶[0014]) arising from a substrate (50; Fig 2; ¶[0014]) and extending lengthwise along a direction (Extending along direction of side located on label 50N/50P of substrate 50; Fig 2);
an isolation feature (STI regions; 56; Fig 2; ¶[0014]) disposed over the substrate and around the fin structure;
Chen, Figs 6A/6B: FinFET device cross-sections in orthogonal planes
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a gate structure (Gate electrodes; 84; Fig 6A; ¶[0015]) wrapping over a channel region (Exposed portions of fin 52; Fig 6A; ¶[0015]) of the fin structure and disposed on the isolation feature;
a first gate spacer (Gate dielectrics; 82; Fig 6A; ¶[0015]) extending along a sidewall (Sidewall of 84; Fig 6A) of the gate structure and a top surface (Top surface of 56; Figs 6A/6B; Note: Fig 6A intersects with Fig 6B, rendering 82 to extend along 56) of the isolation feature;
a second gate spacer (Gate spacers; 66; Fig 6A; ¶[0015]) disposed over the first gate spacer;
a filler dielectric layer (First ILD layer; 76; Fig 6B; ¶[0048]) disposed over the second gate spacer;
an epitaxial feature (Functional layers; 70A/70B; Fig 6A; ¶[0015]) disposed over a source/drain region (70; Fig 6A; ¶[0015]) of the fin structure, a portion (Side portions of 70 disposed over portions of 76; Fig 6B) of the epitaxial feature being disposed over the filler dielectric layer;
a contact etch stop layer (CESL) (Etch stop layer/dielectric CESL/semiconductor CESL; 100/74/70C; Figs 6A/6B; ¶[0048]) disposed over the epitaxial feature and the filler dielectric layer (Etch stop layer 100 disposed over filler dielectric 76 and epitaxial feature 98/70A/70B; Figs 12A/12B); and
Chen, Figs 12A/12B: FinFET showing ILD and CESL layers
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an interlayer dielectric (ILD) layer (Second ILD layer; 102; Figs 12A/12B) disposed over and interfacing (Second ILD layer 102 interfaces and is disposed over etch stop layer 100; Figs 12A/12B) the CESL,
wherein a portion (Portions of 74; Fig 12A) of the CESL extends between the epitaxial feature and a sidewall of gate structure along the direction (Referring to Figs 1 and 12A/12B, etch stop layer 74 extends between gate spacers 66, i.e. part of the gate structure, and source/drain regions 70; ¶[0048]).
Re Claim 2, (Currently Amended) Chen teaches the semiconductor structure of claim 1, wherein a portion (Portion of 76 between 84 and 70B; Figs 6A/6B) of the filler dielectric layer (First ILD layer; 76; Fig 6B; ¶[0048]) is disposed between a sidewall (Sidewall of functional layers 70A/70B; Figs 6A/6B) of the epitaxial feature (Functional layers; 70A/70B; Fig 6A; ¶[0015]) and the sidewall of the gate structure (Gate electrodes; 84; Fig 6A; ¶[0015]) along the direction (Extending along direction of side located on label 50N/50P of substrate 50; Fig 2).
Examiner notes Figs 6A/6B do no directly show the filler dielectric layer disposed directly between a sidewall of the epitaxial features and gate structure, however, according to Figure 2 of Chen, the filler dielectric layer intersects the gate structure and is disposed between the sidewalls of the epitaxial feature and gate structure at the interface with the gate structure.
Re Claim 8, (Original) Chen teaches the semiconductor structure of claim 1,
wherein the first gate spacer (Gate dielectrics; 82; Fig 6A; ¶[0015]) comprises a first thickness (Thickness of 82 in x-direction; Fig 6A),
wherein the second gate spacer (Gate spacers; 66; Fig 6A; ¶[0015]; 66 may be silicon nitride, silicon carbonitride, silicon oxycarbonitride per ¶[0033]) comprises a second thickness (Thickness of 66 in x-direction; Fig 6A),
wherein the filler dielectric layer (First ILD layer; 76; Fig 6B; ¶[0048]) comprises a third thickness (Thickness in x-direction of 76; Fig 6A) greater than the first thickness or the second thickness.
Claim Rejections - 35 USC § 103
13. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Chun-Han et al. (Pub No. US 20210366786 A1) (hereinafter, Chen) as applied to claim 1 above, and further in view of Ching, Kuo-Cheng et al. (Pub No. US 20170053916 A1) (hereinafter, Ching).
Re Claim 3, (Currently Amended) Chen teaches the semiconductor structure of claim 1,
wherein a composition (82 may include silicon oxide, silicon nitride or metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb; ¶[0051]) of the first gate spacer (Gate dielectrics; 82; Fig 6A; ¶[0015]) is different from a composition (66 may be silicon nitride, silicon carbonitride, silicon oxycarbonitride; ¶[0033]) of the second gate spacer (Gate spacers; 66; Fig 6A; ¶[0015]),
wherein the composition of the second gate spacer is different from the composition (Per ¶[0048]) composition of 76 may be silicate glass such as phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG)) of the filler dielectric layer (First ILD layer; 76; Fig 6B; ¶[0048]).
However, Chen does not teach wherein the gate structure comprises a gate dielectric layer and a work function layer over the gate dielectric layer,
wherein the gate dielectric layer interfaces the first gate spacer.
In the same field of endeavor, Ching teaches wherein the gate structure (Gate structure; 140; Fig 6C; ¶[0034]) comprises a gate dielectric layer (Gate dielectric layer; 142; Fig 6C; ¶[0034]) and a work function layer (Work function metal layer; 144; Fig 6C; ¶[0034]) over the gate dielectric layer,
wherein the gate dielectric layer interfaces the first gate spacer (Gate spacer; 130; Fig 6C; ¶[0027]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have made the gate structure comprise a gate dielectric layer and a work function layer over the gate dielectric layer, wherein the gate dielectric layer interfaces the first gate spacer, as taught by Ching for the semiconductor device as taught by Chen. One would have been motivated to do this with a reasonable expectation of success because the addition of the work function metal layer surrounding the gate structure yields tuning precision off the threshold voltage applied to the gate, ensuring lower power consumption and higher performance.
15. Claims 4, 9 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Chun-Han et al. (Pub No. US 20210366786 A1) (hereinafter, Chen) as applied to claim 1 above, and further in view of Yang, Che-Yu et al. (Pub No. US 20200105938 A1) (hereinafter, Yang).
Re Claim 4, (Original) Chen teaches the semiconductor structure of claim 1,
wherein the dielectric constant (K value of greater than about 7.0; ¶[0051]) of the first gate spacer (Gate dielectrics; 82; Fig 6A; ¶[0015]) is greater than a dielectric constant (Dielectric constant of Silicon Nitride may be up to 10.07; ¶[0033]) of the second gate spacer (Gate spacers; 66; Fig 6A; ¶[0015]; 66 may be silicon nitride, silicon carbonitride, silicon oxycarbonitride per ¶[0033]).
However, Chen does not teach wherein a dielectric constant of the filler dielectric layer is greater than a dielectric constant of the first gate spacer.
In the same field of endeavor, Yang teaches wherein a dielectric constant (May be silicon nitride, k value of approximately 7.0; ¶[0038]) of the filler dielectric layer (ILD; 270; Fig 11B; ¶[0019]) is greater than a dielectric constant (May be SiCN, k value of approximately 3.7 to 5.3; ¶[0029]) of the first gate spacer (First spacer layer; 226; Fig 11C; ¶[0029]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have made the dielectric constant of the filler dielectric layer greater than a dielectric constant of the first gate spacer, as taught by Yang for the semiconductor device as taught by Chen. One would have been motivated to do this with a reasonable expectation of success because the low dielectric constant material of the first gate spacer is required in order to reduce parasitic capacitance, whereas a high dielectric constant material of the filler dielectric layer is designed to reduce gate leakage current.
Re Claim 9, (Currently Amended) Chen teaches a semiconductor structure, comprising:
a substrate (50; Fig 2; ¶[0014]);
a fin structure (Fins; 52; Fig 2; ¶[0014]) arising from the substrate and extending lengthwise along a direction (Extending along direction of side located on label 50N/50P of substrate 50; Fig 2);
an isolation feature (STI regions; 56; Fig 2; ¶[0014]) disposed over the substrate and around the fin structure;
a gate structure (Gate electrodes; 84; Fig 6A; ¶[0015]) wrapping over a channel region (Exposed portions of fin 52; Fig 6A; ¶[0015]) of the fin structure and disposed on the isolation feature;
a first gate spacer (Gate dielectrics; 82; Fig 6A; ¶[0015]) extending along a sidewall (Sidewall of 84; Fig 6A) of the gate structure and a top surface (Top surface of 56; Figs 6A/6B; Note: Fig 6A intersects with Fig 6B, rendering 82 to extend along 56) of the isolation feature;
an epitaxial feature (Functional layers; 70A/70B; Fig 6A; ¶[0015]) disposed over a source/drain region (70; Fig 6A; ¶[0015]) of the fin structure, the epitaxial feature comprising a first portion and a second portion (Side portions of 70 disposed over portions of 76; Fig 6B) overhanging the isolation feature,
wherein, along the direction, the first portion and the second portion are spaced apart from the gate structure by a filler dielectric layer (First ILD layer; 76; Fig 6B; ¶[0048]) and a contact etch stop layer (CESL) (Etch stop layer/dielectric CESL/semiconductor CESL; 100/74/70C; Figs 6A/6B; ¶[0048]) over the filler dielectric layer,
wherein the CESL interfaces a top surface (100 is disposed over 76; Fig 12B) of the filler dielectric layer,
wherein the CESL comprises silicon nitride (Silicon nitride, silicon oxide, silicon oxynitride; ¶[0048]) and has a dielectric constant between about 6.4 and about 7 (Silicon nitride may be about 7.0).
However, Chen does not teach wherein the filler dielectric layer comprises silicon oxynitride and has a dielectric constant between about 5 and about 6.4.
In the same field of endeavor, Yang teaches wherein the filler dielectric layer (ILD; 270; Fig 11B; ¶[0019]) comprises silicon oxynitride (Silicon oxynitride; ¶[0038]) and has a dielectric constant between about 5 and about 6.4 (Silicon oxynitride may have a dielectric constant greater than 5, as SiON is a high-k dielectric material with k greater than 5 per ¶[0042]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a filler dielectric layer comprises silicon oxynitride and has a dielectric constant between about 5 and about 6.4, as taught by Yang for the semiconductor structure as taught by Chen. One would have been motivated to do this with a reasonable expectation of success because SiON provides better thermal stability which may be useful for thermally insulating the gate and source/drain regions.
Re Claim 12, (Original) Chen teaches the structure of claim 9, wherein a dielectric constant (Dielectric constant of silicate glass is approximately 3.9; ¶[0048]) of the filler dielectric layer (First ILD layer; 76; Fig 6B; ¶[0048]) is smaller than a dielectric constant (Dielectric constant of silicon nitride, silicon oxide, silicon oxynitride is approximately 7.0; ¶[0048]) of the CESL (Dielectric CESL/semiconductor CESL; 74/70C; Figs 6A/6B; ¶[0048]).
Re Claim 13, (Original) Chen teaches the structure of claim 9, wherein the CESL (Dielectric CESL/semiconductor CESL; 74/70C; Figs 6A/6B; ¶[0048]) comprises silicon nitride (Silicon nitride, silicon oxide, silicon oxynitride; ¶[0048]).
However, Chen does not teach wherein the filler dielectric layer comprises silicon oxynitride.
In the same field of endeavor, Yang teaches wherein the filler dielectric layer (ILD; 270; Fig 11B; ¶[0019]) comprises silicon oxynitride (Silicon oxynitride; ¶[0038]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a filler dielectric layer comprises silicon oxynitride, as taught by Yang for the semiconductor structure as taught by Chen. One would have been motivated to do this with a reasonable expectation of success because SiON provides better thermal stability which may be useful for thermally insulating the gate and source/drain regions.
16. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Chun-Han et al. (Pub No. US 20210366786 A1) (hereinafter, Chen) in view of Yang, Che-Yu et al. (Pub No. US 20200105938 A1) (hereinafter, Yang) as applied to claim 1 above, and further in view of Lin, Chien-Chih et al. (Pub No. US 20210313441 A1) (hereinafter, Lin).
Re Claim 5, (Currently Amended) Chen teaches the semiconductor structure of claim 1,
wherein the second gate spacer (Gate spacers; 66; Fig 6A; ¶[0015]; 66 may be silicon nitride, silicon carbonitride, silicon oxycarbonitride or combinations of each per ¶[0033]) comprises silicon oxide or silicon oxycarbide (SiOCN comprises of SiOC).
However, Chen does not teach wherein the first gate spacer comprises silicon oxycarbonitride or silicon oxycarbide,
and the filler dielectric layer comprise silicon oxynitride.
In the same field of endeavor, Yang teaches wherein the first gate spacer (First spacer layer; 226; Fig 11C; ¶[0029]) comprises silicon oxycarbonitride or silicon oxycarbide (May comprise any combination of silicon, oxygen, carbon, nitrogen; ¶[0029]),
and the filler dielectric layer (ILD; 270; Fig 11B; ¶[0019]) comprise silicon oxynitride (Silicon oxynitride; ¶[0038]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a first gate spacer comprising of silicon oxycarbonitride or silicon oxycarbide and a filler dielectric layer comprising silicon oxynitride, as taught by Yang for the semiconductor structure as taught by Chen. One would have been motivated to do this with a reasonable expectation of success because the SiOC and SiON spacers and dielectric fill layers are a high-k dielectric which provide increased capacitance, reduced leakage current and enhanced gate control, and additionally SiON provides better thermal stability which may be useful for thermally insulating the gate and source/drain regions.
However, Chen in view of Yang does not teach wherein an oxygen content of the second gate spacer is greater than an oxygen content of the first gate spacer.
In the same field of endeavor, Lin teaches wherein an oxygen content (20 at. % to 70 at. %; ¶[0036]) of the second gate spacer (Second main layer; 72C; Figs 5B/5C; ¶[0036]) is greater than an oxygen content (20 at. % to 50 at. %; ¶[0036]) of the first gate spacer (First main layer; 72B; Figs 5B/5C; ¶[0035].
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used an oxygen content of the second gate spacer layer is greater than an oxygen content of the first gate spacer, as taught by Lin for the semiconductor structure as taught by Chen. One would have been motivated to do this with a reasonable expectation of success because the second gate spacer can have a relative permittivity that is from about 10% to about 40% less than the first main layer, thus decreasing parasitic capacitance of the FinFETS, as suggested by Lin (¶[0038]).
17. Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Chun-Han et al. (Pub No. US 20210366786 A1) (hereinafter, Chen) as applied to claim 1 above, and further in view of Ho, Byron et al. (Pub No. US 20190164961 A1) (hereinafter, Ho).
Ho, Figs 9A/9B: FinFET structures comprising epitaxial features higher than filler dielectric layers
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Re Claim 6, (Currently Amended) Chen teaches wherein the CESL (Etch stop layer/dielectric CESL/semiconductor CESL; 100/74/70C; Figs 6A/6B; ¶[0048]) interfaces (74 interfaces 76; Fig 6B) the filler dielectric layer (First ILD layer; 76; Fig 6B; ¶[0048]).
However, Chen does not teach the semiconductor structure of claim 1, wherein a top surface of the epitaxial feature is higher than a top surface of the filler dielectric layer.
In the same field of endeavor, Ho teaches the semiconductor structure of claim 1, wherein a top surface (Top surface of 910; Figs 9A/9B) of the epitaxial feature (Source or drain structures; 910; Figs 9A/9B; ¶[0185]) is higher than a top surface (Top surface of 714; Figs 9A/9B) of the filler dielectric layer (Patterned dielectric material (the layer directly below 910); 714; Figs 9A/9B; ¶[0171]; Note: 714 is split into two portions).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a top surface of the epitaxial feature which is higher than a top surface of the filler dielectric layer, as taught by Lin for the semiconductor structure as taught by Chen. One would have been motivated to do this with a reasonable expectation of success because raising the epitaxial feature above the filler dielectric allows for a wider path for current, reducing parasitic capacitance and improving device performance.
Re Claim 7, (Original) Chen does not teach the semiconductor structure of claim 1, wherein top surfaces of the first gate spacer and the second gate spacer are higher than a top surface of the filler dielectric layer.
In the same field of endeavor, Ho teaches the semiconductor structure of claim 1, wherein top surfaces (Top surfaces of second portion of 714, e.g. on side of gate electrodes, and top surface of 922; Fig 9A) of the first gate spacer (Portion of 714 on side of gate electrode; Fig 9A) and the second gate spacer (Gate dielectric layer; 922; Fig 9A; ¶[0186]) are higher than a top surface of the filler dielectric layer (Patterned dielectric material (the layer directly below 910); 714; Fig 9A; ¶[0171]; Note: 714 is split into two portions).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a top surface of the epitaxial feature which is higher than a top surface of the filler dielectric layer, as taught by Lin for the semiconductor structure as taught by Chen. One would have been motivated to do this with a reasonable expectation of success because a longer spacer structure which is placed higher than the dielectric filler material below the source/drain region helps extend the gate's influence and control over the channel, suppressing the lateral electric fields that emanate from the source and drain regions, thereby enhancing overall device performance.
18. Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Chun-Han et al. (Pub No. US 20210366786 A1) (hereinafter, Chen) in view of Yang, Che-Yu et al. (Pub No. US 20200105938 A1) (hereinafter, Yang) as applied to claim 9 above, and further in view of Yeh, Hsin-Hao et al. (Pub No. US 20190386111 A1) (hereinafter, Yeh).
Re Claim 10, (Currently Amended) Chen teaches the structure of claim 9, wherein the filler dielectric layer (First ILD layer; 76; Fig 6B; ¶[0048]) is spaced apart from sidewalls (Sidewalls of 70; Fig 6A) of the source/drain region (70; Fig 6A; ¶[0015]) of the fin structure (Fins; 52; Fig 2; ¶[0014]) and the isolation feature (STI regions; 56; Fig 2; ¶[0014]) by a first gate spacer (Gate dielectrics; 82; Fig 6A; ¶[0015]) and a second gate spacer (Gate spacers; 66; Fig 6A; ¶[0015]),
However, Chen in view of Yang does not teach wherein a portion of the second gate spacer is vertically disposed between the first gate spacer and the isolation feature.
In the same field of endeavor, Yeh teaches wherein a portion of the second gate spacer (First gate spacer; 76; Fig 15B; ¶[0030]) is vertically disposed between the first gate spacer (Second gate spacer; 80; Fig 15B; ¶[0051]) and the isolation feature (STI regions; 56; Figs 1/15A/15B; ¶[0019]; Note: Referring to Fig 1, the isolation feature is disposed underneath the gate spacers, although not explicitly shown in Figs 15A/15B).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a portion of the second gate spacer is vertically disposed between the first gate spacer and the isolation feature, as taught by Yeh for the semiconductor structure as taught by Chen in view of Yang. One would have been motivated to do this with a reasonable expectation of success because the second gate spacer disposed underneath the first gate spacer and above the isolation feature such that current leakage may be prevented between the source/drain region.
Re Claim 11, (Original) Chen teaches the structure of claim 10, wherein a thickness (Thickness in x-direction of 76; Fig 6A) of the filler dielectric layer (First ILD layer; 76; Fig 6B; ¶[0048]) is greater than a thickness (Thickness of 82 in x-direction; Fig 6A) of the first gate spacer (Gate dielectrics; 82; Fig 6A; ¶[0015]) or a thickness (Thickness of 66 in x-direction; Fig 6A) of the second gate spacer (Gate spacers; 66; Fig 6A; ¶[0015]; 66 may be silicon nitride, silicon carbonitride, silicon oxycarbonitride per ¶[0033]).
Allowable Subject Matter
19. Claims 14-20 are allowed.
The closest prior art Chen, Chun-Han et al. (Pub No. US 20210366786 A1) (hereinafter, Chen) either singularly or in combination fails to anticipate or render obvious
“A method, comprising:
forming a fin structure on a substrate, the fin structure comprising a channel region and a source/drain region adjacent the channel region;
forming an isolation feature over the substrate and around the fin structure;
forming a dummy gate stack over the channel region of the fin structure;
depositing a first gate spacer layer and a second gate spacer layer over the substrate, including over the dummy gate stack and the fin structure;
depositing a filler dielectric layer over the second gate spacer layer;
after the depositing of the filler dielectric layer, anisotropically etching the fin structure to form a source/drain recess over the source/drain region;
epitaxially grown a source/drain feature over the source/drain recess;
isotropically etching back the filler dielectric layer; and
after the isotropically etching back, depositing a contact etch stop layer (CESL) over the source/drain feature and the filler dielectric layer,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, Chen fails to teach "after depositing of the filler dielectric layer, anisotropically etching the fin structure to for a source/drain recess over the source/drain region." Given that the filler dielectric layer is deposited over the second gate spacer layer, as required by claim 14, there exists no prior art of record which discloses anisotropically etching a source/drain recess after the filler dielectric layer is deposited.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Ye, Xin-Hao et al. (Pub No. CN110610861A) discloses a FinFET device which includes opposite sides a plurality of side wall on the substrate to form a gate stack, the gate stack is deposited on the first gate spacer, the gate stack of the upper epitaxially growing a plurality of source/drain regions, depositing a second gate spacer on the first gate spacer, to form gas spacer under the second gate spacer. gas spacer can be disposed laterally to the source/drain regions and the gate stack.
[2] Pan, Sheng-Liang et al. (Pub No. TW202143311A) discloses a method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817
/T.E.D./
Examiner
Art Unit 2817