DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 2/24/2026 is acknowledged. Claims 1, 3, 5 and 9-11 are amended, claims 12-20 are cancelled, and claims 21-29 are newly added.
Therefore, claims 1-11 and 21-29 have been fully considered in examination.
Claim Objections
Claims 1 and 27 are objected to because of the following informalities: The abbreviation “CFET” is used without being spelled out upon first use as “complementary field-effect transistor (CFET)”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-11 and 21-29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ),
second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject
matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the
applicant), regards as the invention.
Regarding claim 1, the claim recites “perform annealing to the first plurality of gate dielectric layers” which is inconsistent with the verb form used throughout the remainder of the claim. This grammatical inconsistency renders the metes and bounds of the claim unclear.
Regarding claims 1, 9, and 27 recite the term “iteratively” without specifying how many times the steps of depositing, annealing, and removing are repeated within the dipole loop process. Since annealing is performed as part of each iteration, the total number of times each gate dielectric layer is annealed directly depends on the number of iterations. It is unclear how many iterations are required or performed, rendering the scope of the claim indefinite.
Claims 2-8, 10, 11, 21-26, 28, and 29 are also rejected being dependent on rejected claims 1, 9, and 27.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-11 and 23-29 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US11387342B1), and further in view of Frougier (US11894436B2) and Chan (US12009400B2).
Regarding claim 1, Zhang teaches a method of forming a semiconductor device (Fig. 14, semiconductor structure 100), comprising:
forming a structure (Fig. 14, nanosheet stack of FET 20) having a plurality of gate dielectric layers wrapping around a plurality of channels (plurality of gate dielectric layers 32 wrapping around a channel material layer 18);
performing a dipole loop process to drive first dipole dopants into the plurality of gate dielectric layers, wherein the first dipole loop process includes iteratively depositing dipole dopant layers over the plurality of gate dielectric layers (Claim 14, diffusing the dipole layer 34 into the gate dielectric surrounding the layers of semiconductor channel material of the second subset of the nanosheet stacks), perform annealing to the plurality of gate dielectric layers (Claim 16, crystallizing the gate dielectric comprises annealing the gate dielectric to form the crystallized gate dielectric layer), and removing the first dipole dopant layers (Fig. 12, dipole layer 34 may be removed from the Structure A),
after performing the first and second dipole loop processes, depositing a gate metal over the plurality of gate dielectric layers (Fig. 14, work function metal 40).
But Zhang does not teach a method of forming a semiconductor device, comprising: forming a CFET structure having a bottom gate region and a top gate region, the bottom gate region having a first plurality of gate dielectric layers wrapping around a first plurality of channels, the top gate region having a second plurality of gate dielectric layers wrapping around a second plurality of channels; performing a first dipole loop process to drive first dipole dopants into the first plurality of gate dielectric layers, wherein the first dipole loop process includes iteratively depositing first dipole dopant layers over the first plurality of gate dielectric layers, perform annealing to the first plurality of gate dielectric layers, and removing the first dipole dopant layers, and wherein a first gate dielectric layer of the first plurality of gate dielectric layers is annealed at least one time and a second gate dielectric layer of the first plurality of gate dielectric layers is annealed at least two times; performing a second dipole loop process to drive second dipole dopants into the second plurality of gate dielectric layers, wherein the second dipole loop process includes iteratively depositing second dipole dopant layers over the second plurality of gate dielectric layers, perform annealing to the second plurality of gate dielectric layers, and removing the second dipole dopant layers, and wherein a third gate dielectric layer of the second plurality of gate dielectric layers is annealed at least one time and a fourth gate dielectric layer of the second plurality of gate dielectric layers is annealed at least two times.
However, Frougier teaches a method of forming a semiconductor device (Fig. 13, CFET structure 100), comprising:
forming a CFET structure (Fig. 13, CFET structure 100) having a bottom gate region and a top gate region, the bottom gate region having a first plurality of gate dielectric layers wrapping around a first plurality of channels (Fig. 13, HKMG stack 1310 including gate dielectric wrapping around lower nanosheet channel layers 130 of the bottom FET, below the dielectric separation layer), the top gate region having a second plurality of gate dielectric layers wrapping around a second plurality of channels (Fig. 13, HKMG stack 1310 including gate dielectric wrapping around upper nanosheet channel layers 130 of the top FET, above the dielectric separation layer).
Thus, by using the CFET structure of Frougier in the method of forming a semiconductor device of Zhang, the method would comprise performing a first dipole loop process to drive first dipole dopants into the first plurality of gate dielectric layers of the bottom gate region, wherein the first dipole loop process includes iteratively depositing first dipole dopant layers over the first plurality of gate dielectric layers, perform annealing to the first plurality of gate dielectric layers, and removing the first dipole dopant layers; performing a second dipole loop process to drive second dipole dopants into the second plurality of gate dielectric layers of the top gate region, wherein the second dipole loop process includes iteratively depositing second dipole dopant layers over the second plurality of gate dielectric layers, perform annealing to the second plurality of gate dielectric layers, and removing the second dipole dopant layers.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify a semiconductor structure of Zhang (US11387342B1) and further integrating the CFET structure having independently processed bottom and top gate regions disclosed by Frougier (US11894436B2). The combination of these familiar elements can improve by achieving multiple threshold voltages in a CFET structure through independent gate stack engineering for each of the top FET and bottom FET (Abstract, the top FET of the first CFET includes a first work function metal, and the top FET of the second CFET includes a second work function metal; Fig. 13, independent gate dielectric processing for top and bottom FET regions of the CFET).
But Zhang in view of Frougier still does not specify wherein a first gate dielectric layer of the first plurality of gate dielectric layers is annealed at least one time and a second gate dielectric layer of the first plurality of gate dielectric layers is annealed at least two times; wherein a third gate dielectric layer of the second plurality of gate dielectric layers is annealed at least one time and a fourth gate dielectric layer of the second plurality of gate dielectric layers is annealed at least two times.
However, Chan teaches a first gate dielectric layer of the first plurality of gate dielectric layers is annealed at least one time (Fig. 1, gate dielectric portions 246C and 246D receive dipole materials from dipole layer 304 during process 404. Gate dielectric portion 246C corresponds well to a gate dielectric portion exposed to one drive-in anneal step) and a second gate dielectric layer of the first plurality of gate dielectric layers is annealed at least two times (Fig. 1, gate dielectric portion 246D is affected by both process 402 and process 404; two drive-in/anneal operations);
wherein a third gate dielectric layer of the second plurality of gate dielectric layers is annealed at least one time (Fig. 1, gate dielectric portions 246C and 246D receive dipole materials from dipole layer 304 during process 404. Gate dielectric portion 246C corresponds well to a gate dielectric portion exposed to one drive-in anneal step) and a fourth gate dielectric layer of the second plurality of gate dielectric layers is annealed at least two times (Fig. 1, gate dielectric portion 246D is affected by both process 402 and process 404; two drive-in/anneal operations).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the combination of Zhang (US11387342B1) and Frougier (US11894436B2) and further integrating the method of forming a dielectric layer with differential anneal counts disclosed by Chan (US12009400B2). The combination of these familiar elements can improve by adjusting the threshold voltages of individual transistors within both the bottom gate region and the top gate region of the CFET structure through controlling the number of drive-in anneal operations applied to each gate dielectric layer (Para [0036], adjust the threshold voltages of individual transistors).
Regarding claim 3, the combination of Zhang, Frougier, and Chan teaches the method of claim 1 as set forth above.
Zhang further teaches, before performing the annealing to the first plurality of gate dielectric layers, the first dipole loop process further includes: depositing the first dipole dopant layers over the second plurality of gate dielectric layers (Fig. 9, dipole layer 34 is formed over gate dielectric layers of both Structure A and Structure B); forming a hard mask over the bottom gate region but leaving the top gate region exposed, wherein the hard mask covers the first dipole dopant layers over the first plurality of gate dielectric layers while exposing the first dipole dopant layers over the second plurality of gate dielectric layers (Fig. 10, second sacrificial gate 36 and second blanket sacrificial layer 38 formed over Structure B while Structure A remains unprotected, covering dipole dopant layers over the bottom gate region while exposing dipole dopant layers over the top gate region); removing the first dipole dopant layers over the second plurality of gate dielectric layers (Fig. 12, dipole layer 34 is removed from Structure A selective to the crystallized gate dielectric 32); and removing the hard mask (Fig. 12, second blanket sacrificial layer 38 and second sacrificial gate 36 removed from Structure B).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to apply Zhang's selective masking and removal technique to the CFET structure of Frougier to independently control dipole dopant diffusion into the bottom gate region versus the top gate region, as this represents a straightforward extension of Zhang's demonstrated selective protection technique to a stacked CFET device structure to achieve independent threshold voltage control in each gate region (Frougier, Abstract, achieving multiple threshold voltages through independent gate stack engineering for top and bottom FET).
Regarding claim 4, the combination of Zhang, Frougier, and Chan teaches the method of claim 1 as set forth above.
Zhang further teaches, before performing the annealing to the second plurality of gate dielectric layers, the second dipole loop process further includes: forming a hard mask over the bottom gate region but leaving the top gate region exposed, the hard mask covers the first plurality of gate dielectric layers while exposing the second plurality of gate dielectric layers (Fig. 10, second sacrificial gate 36 and second blanket sacrificial layer 38 formed over Structure B covering the gate dielectric layers of Structure B while leaving Structure A exposed); depositing the second dipole dopant layers over the hard mask when depositing the second dipole dopant layers over the second plurality of gate dielectric layers (Fig. 9-10, dipole layer 34 deposited over both Structure A and Structure B including over the second blanket sacrificial layer 38 of Structure B while being deposited directly over gate dielectric layers of Structure A); and removing the hard mask (Fig. 12, second blanket sacrificial layer 38 and second sacrificial gate 36 removed). Chan further teaches a hard mask scheme wherein a first region's gate dielectric layers are protected while second region dipole dopant layers are deposited and annealed (Fig. 1, masking is used to selectively expose gate dielectric layers to dipole deposition processes 402 and 404).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to apply selective hard masking during the second dipole loop process to protect the already-processed bottom gate region's gate dielectric layers while performing dipole deposition and anneal on the top gate region, as this is a natural extension of the selective protection techniques taught by Zhang and Chan to prevent unintended dipole incorporation into previously processed gate dielectric layers (Chan, Para [0036], adjust the threshold voltages of individual transistors).
Regarding claim 5, the combination of Zhang, Frougier, and Chan teaches the method of claim 1 as set forth above.
Zhang teaches a dipole patterning process, the dipole patterning process includes masking the CFET structure before performing each dipole loop of the first or the second dipole loop processes (Fig. 5, organic polymer layer 30 covers Structure B nanosheet stacks while leaving Structure A nanosheet stacks exposed; Fig. 10, second blanket sacrificial layer 38 selectively covers certain regions before dipole drive-in anneal).
Chan further teaches wherein before performing a first dipole loop, the dipole patterning process exposes a first portion of the CFET structure, the first portion includes a first CFET device gate region having the second and the fourth gate dielectric layers (Fig. 1, gate dielectric portion 246D is exposed during both process 402 and process 404, corresponding to a first CFET device gate region having gate dielectric layers to receive at least two anneal cycles, corresponding to the second and fourth gate dielectric layers); wherein before performing a second dipole loop, the dipole patterning process exposes a second portion of the CFET structure, second portion includes the first CFET device gate region having the second and the fourth gate dielectric layers and a second CFET device gate region having the first and third gate dielectric layers (Fig. 1, gate dielectric portion 246C is only exposed during process 404, corresponding to a second CFET device gate region having gate dielectric layers to receive one anneal cycle, corresponding to the first and third gate dielectric layers, wherein the second portion now includes both the first and second CFET device gate regions).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to implement this sequential exposure patterning scheme in a CFET structure to achieve graduated dipole incorporation enabling multiple distinct threshold voltages, as this directly follows from the selective dipole patterning techniques taught by Zhang and Chan extended to the CFET architecture of Frougier (Frougier, Abstract, achieving multiple threshold voltages; Chan, Para [0036], adjust the threshold voltages of individual transistors).
Regarding claim 6, the combination of Zhang, Frougier, and Chan teaches the method of claim 5 as set forth above.
The additional limitation that performing the first or second dipole loop process in combination with the dipole patterning process results in multiple gate threshold voltages in the CFET structure, wherein performing n dipole loops results in (n+1) gate threshold voltages is merely a statement of the natural result that flows directly from the dipole patterning process already taught by the combination. Zhang teaches that different numbers of dipole anneal cycles applied to different gate dielectric layers produce different threshold voltages (col. 12, selective crystallization of the gate dielectric yields at least four different techniques to control or adjust the threshold voltages of nanosheet devices; the Structure A and the Structure B with the diffused dipole material can be designed and fabricated with different threshold voltages). Chan teaches that gate dielectric layers receiving different numbers of drive-in anneal operations have correspondingly different dipole concentrations and thus different threshold voltages (Fig. 1, gate dielectric portion 246C exposed to one drive-in anneal step produces a first threshold voltage, gate dielectric portion 246D affected by both process 402 and process 404 produces a second threshold voltage; Para [0036], adjust the threshold voltages of individual transistors).
Thus, when the dipole patterning process of claim 5 is applied wherein each successive dipole loop exposes an incrementally larger portion of the CFET structure, the number of distinct dipole concentration levels — and therefore the number of distinct threshold voltages — is a direct mathematical consequence of the number of loops performed. The (n+1) relationship is not a separately patentable feature but rather a functional description of the inherent result of the patterning scheme already taught by the prior art combination, as each gate dielectric layer receiving 0 through n cumulative anneal cycles produces a distinct threshold voltage as directly taught by Chan and Zhang.
Regarding claim 7, the combination of Zhang, Frougier, and Chan teaches the method of claim 1 as set forth above.
Zhang teaches a dipole patterning process, the dipole patterning process includes masking the CFET structure before performing each dipole loop of the first or the second dipole loop processes (Fig. 5, organic polymer layer 30 selectively covers certain nanosheet stacks; Fig. 10, second blanket sacrificial layer 38 selectively protects certain regions before anneal).
Chan teaches wherein before performing a first dipole loop, the dipole patterning process exposes a first portion of the CFET structure, the first portion includes a first CFET device gate region having the second and the fourth gate dielectric layers and a second CFET device gate region having the first and third gate dielectric layers (Fig. 1, process 402 exposes gate dielectric portions 246D of a first CFET device gate region and gate dielectric portions of a second CFET device gate region, corresponding to a first portion including the first CFET device gate region having the second and fourth gate dielectric layers and a second CFET device gate region having the first and third gate dielectric layers); wherein before performing a second dipole loop, the dipole patterning process exposes a second portion of the CFET structure, the second portion includes the first CFET device gate region having the second and the fourth gate dielectric layers (Fig. 1, process 404 exposes only gate dielectric portions 246D of the first CFET device gate region, corresponding to a second portion including only the first CFET device gate region having the second and fourth gate dielectric layers).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to implement this alternative sequential patterning scheme in the CFET structure of Frougier using Zhang's masking techniques and Chan's differential anneal approach to achieve a different multi-Vt distribution than that of claim 5, as the selection between different patterning sequences to achieve desired threshold voltage distributions represents a routine design choice well within the skill of the art (Chan, Para [0036]; Frougier, Abstract).
Regarding claim 8, the combination of Zhang, Frougier, Chan, and Guha teaches the method of claim 7 as set forth above.
The additional limitation that performing the first or second dipole loop process in combination with the dipole patterning process results in multiple gate threshold voltages in the CFET structure, wherein performing n dipole loops results in (2n) gate threshold voltages is a functional description of the inherent result that flows from the combination of (1) the reverse-order patterning scheme of claim 7, and (2) the use of different dipole dopant materials for the bottom gate region versus the top gate region as recited in claim 2 (lanthanum for the first dipole dopants, zinc for the second dipole dopants).
Specifically, Zhang teaches that the material of the dipole layer may be selected to produce different threshold voltage shifts depending on whether an NFET or PFET device is desired (col. 9, adjusting the material of the dipole layer may be another method to alter or change the threshold voltage for the nanosheet transistors; lanthanum oxide (La2O3) dipole layer may typically lower the threshold voltage of an NFET device and may typically raise the threshold voltage of a PFET device). Guha teaches that different dipole layer materials shift the threshold voltage of the FET in different directions (Claim 5, the material that forms the dipole layer is chosen to shift the threshold voltage of the FET in a desired direction; Claim 6, zinc oxide is a suitable dipole layer material). Frougier teaches that the top FET and bottom FET of a CFET are independently processed with different gate stack materials to achieve different threshold voltages (Abstract, the top FET of the first CFET includes a first work function metal and the top FET of the second CFET includes a second work function metal).
Thus, under the claim 7 patterning scheme where the bottom gate region uses lanthanum as the first dipole dopant and the top gate region uses zinc as the second dipole dopant, a gate dielectric layer in the bottom gate region receiving k anneal cycles with lanthanum produces a different threshold voltage from a gate dielectric layer in the top gate region receiving k anneal cycles with zinc, even when the number of anneal cycles is identical. The (2n) relationship is the inherent result of independently combining n distinct dipole concentration levels in the bottom gate region with n distinct dipole concentration levels in the top gate region using two different dipole dopant materials, producing 2×n distinct threshold voltages (Chan, Para [0036], adjust the threshold voltages of individual transistors).
Regarding claim 9, Zhang teaches a method of forming a semiconductor device (Fig. 14, semiconductor structure 100), comprising:
forming stacks of semiconductor channels over a substrate (Fig. 1, nanosheet stack 20 including semiconductor channel material layers 18 on substrate 10), each stack having a plurality of gate dielectric layers wrapping around each semiconductor channel (Fig. 14, gate dielectric layers 32 and 40 wrapping around channel material layers 18);
performing a first dipole loop process to drive first dipole dopants of various concentrations into a first plurality of the gate dielectric layers (Claim 14, diffusing the dipole layer 34 into the gate dielectric surrounding the layers of semiconductor channel material), wherein the first dipole loop process includes iteratively and selectively driving the first dipole dopants into the first plurality of the gate dielectric layers (Fig. 9-12, iterative process of depositing dipole layer 34, annealing, and removing);
performing a second dipole loop process to drive second dipole dopants of various concentrations into a second plurality of the gate dielectric layers (Fig. 9-12, dipole layer 34 formed over Structure B gate dielectric layers and diffused via annealing);
depositing a gate metal over the first and second plurality of the gate dielectric layers (Fig. 14, work function metal 40).
But Zhang does not teach a method of forming a semiconductor device, comprising: forming stacks of semiconductor channels over a substrate, each stack having top semiconductor channels for a top device over bottom semiconductor channels for a bottom device; forming gate dielectric layers over the channel regions and wrapping around each semiconductor channel of each stack of the semiconductor channels; performing a first dipole loop process to drive first dipole dopants of various concentrations into a first plurality of the gate dielectric layers wrapping around the bottom semiconductor channels for the bottom device, wherein the first dipole loop process includes iteratively and selectively driving the first dipole dopants into the first plurality of the gate dielectric layers such that a first gate dielectric layer of the first plurality of gate dielectric layers has a greater concentration of the first dipole dopants than a second gate dielectric layer of the first plurality of gate dielectric layers; performing a second dipole loop process to drive second dipole dopants of various concentrations into a second plurality of the gate dielectric layers wrapping around the top semiconductor channels for the top device, wherein the second dipole loop process includes iteratively and selectively driving the second dipole dopants into the second plurality of the gate dielectric layers such that a third gate dielectric layer of the second plurality of gate dielectric layers has a greater concentration of the second dipole dopants than a fourth gate dielectric layer of the second plurality of gate dielectric layers.
However, Frougier teaches a method of forming a semiconductor device (Fig. 13, CFET structure 100), comprising:
forming stacks of semiconductor channels over a substrate (Fig. 1B, nanosheet stack including alternating layers of silicon germanium 140, 150 and silicon 130 over substrate 110), each stack having top semiconductor channels for a top device over bottom semiconductor channels for a bottom device (Fig. 13, upper nanosheet channel layers 130 of the top FET above the dielectric separation layer, and lower nanosheet channel layers 130 of the bottom FET below the dielectric separation layer);
forming gate dielectric layers over the channel regions and wrapping around each semiconductor channel of each stack of the semiconductor channels (Fig. 13, HKMG stack 1310 including gate dielectric wrapping around both top and bottom semiconductor channels).
Thus, by using the CFET structure of Frougier in the method of forming a semiconductor device of Zhang, the method would comprise performing a first dipole loop process to drive first dipole dopants of various concentrations into a first plurality of the gate dielectric layers wrapping around the bottom semiconductor channels for the bottom device, wherein the first dipole loop process includes iteratively and selectively driving the first dipole dopants into the first plurality of the gate dielectric layers; performing a second dipole loop process to drive second dipole dopants of various concentrations into a second plurality of the gate dielectric layers wrapping around the top semiconductor channels for the top device, wherein the second dipole loop process includes iteratively and selectively driving the second dipole dopants into the second plurality of the gate dielectric layers.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify a semiconductor structure of Zhang (US11387342B1) and further integrating the CFET structure having independently processed bottom and top gate regions disclosed by Frougier (US11894436B2). The combination of these familiar elements can improve by achieving multiple threshold voltages in a CFET structure through independent gate stack engineering for each of the top FET and bottom FET (Abstract, the top FET of the first CFET includes a first work function metal, and the top FET of the second CFET includes a second work function metal; Fig. 13, independent gate dielectric processing for top and bottom FET regions of the CFET).
But Zhang in view of Frougier still does not specify wherein a first gate dielectric layer of the first plurality of gate dielectric layers has a greater concentration of the first dipole dopants than a second gate dielectric layer of the first plurality of gate dielectric layers; wherein a third gate dielectric layer of the second plurality of gate dielectric layers has a greater concentration of the second dipole dopants than a fourth gate dielectric layer of the second plurality of gate dielectric layers.
However, Chan teaches that gate dielectric layers exposed to a greater number of drive-in anneal operations accumulate a greater concentration of dipole dopants than gate dielectric layers exposed to fewer anneal operations (Fig. 1, gate dielectric portion 246D is affected by both process 402 and process 404, receiving a greater concentration of dipole dopants than gate dielectric portion 246C which receives dipole materials only during process 404; Para [0036], adjust the threshold voltages of individual transistors), thereby establishing that iteratively and selectively driving dipole dopants into gate dielectric layers produces a first gate dielectric layer having a greater concentration of the first dipole dopants than a second gate dielectric layer exposed to fewer iterations.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify the combination of Zhang (US11387342B1) and Frougier (US11894436B2) and further integrating the method of forming a dielectric layer with differential dipole dopant concentrations disclosed by Chan (US12009400B2). The combination of these familiar elements can improve by adjusting the threshold voltages of individual transistors within both the bottom device and the top device of the CFET structure through controlling the concentration of dipole dopants driven into each gate dielectric layer (Para [0036], adjust the threshold voltages of individual transistors).
Regarding claim 10, the combination of Zhang, Frougier, and Chan teaches the method of claim 9 as set forth above.
Zhang further teaches that the first dipole loop process includes iteratively performing at least two times: depositing first dipole dopant layers over the gate dielectric layers (Fig. 9, dipole layer 34 formed over gate dielectric layers of both Structure A and Structure B); forming a hard mask over the bottom device but leaving the top device exposed (Fig. 10, second sacrificial gate 36 and second blanket sacrificial layer 38 formed over Structure B while Structure A remains exposed); removing the first dipole dopant layers over the top device (Fig. 12, dipole layer 34 removed from Structure A); removing the hard mask (Fig. 12, second blanket sacrificial layer 38 and second sacrificial gate 36 removed); annealing to drive the first dipole dopants into the first plurality of gate dielectric layers (Fig. 11, annealing step causes dipole layer 34 to diffuse into gate dielectric 24); and removing the first dipole dopant layers (Fig. 12, dipole layer 34 removed).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to apply Zhang's selective masking and iterative dipole drive-in technique to the CFET structure of Frougier to achieve differential dipole dopant concentrations in the first plurality of gate dielectric layers of the bottom device, as this represents a straightforward extension of Zhang's demonstrated selective protection technique to achieve independent and graded threshold voltage control in the bottom device gate region (Frougier, Abstract; Chan, Para [0036]).
Regarding claim 11, the combination of Zhang, Frougier, and Chan teaches the method of claim 9 as set forth above.
Zhang further teaches that the second dipole loop process includes iteratively performing at least two times: forming a hard mask over the bottom device but leaving the top device exposed (Fig. 10, second sacrificial gate 36 and second blanket sacrificial layer 38 formed over Structure B while Structure A remains exposed); depositing second dipole dopant layers over exposed gate dielectric layers in the top device while the hard mask covers the gate dielectric layers in the bottom device (Fig. 9-10, dipole layer 34 deposited over Structure A gate dielectric layers while second blanket sacrificial layer 38 covers Structure B gate dielectric layers); removing the hard mask (Fig. 12, second blanket sacrificial layer 38 and second sacrificial gate 36 removed); annealing to drive the second dipole dopants into the second plurality of gate dielectric layers (Fig. 11, annealing step causes dipole layer 34 to diffuse into gate dielectric 24); and removing the second dipole dopant layers (Fig. 12, dipole layer 34 removed). Chan further teaches that a hard mask scheme is used to selectively expose gate dielectric layers of a second region to dipole deposition and anneal operations while protecting gate dielectric layers of a first region (Fig. 1, masking used to selectively expose gate dielectric layers during processes 402 and 404).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to apply selective hard masking during the second dipole loop process to protect the already-processed bottom device gate dielectric layers while performing iterative dipole deposition and anneal on the top device, achieving differential dipole dopant concentrations in the second plurality of gate dielectric layers of the top device (Frougier, Abstract; Chan, Para [0036]).
Regarding claim 23, the combination of Zhang, Frougier, and Chan teaches the method of claim 9 as set forth above.
Zhang further teaches wherein one or more iterations of the first dipole loop process selectively drive the first dipole dopants into the first plurality of gate dielectric layers in one gate region to the exclusion of another gate region (Fig. 5, organic polymer layer 30 selectively covers Structure B nanosheet stacks while leaving Structure A nanosheet stacks exposed such that dipole dopants are driven into Structure A gate dielectric layers to the exclusion of Structure B gate dielectric layers; Fig. 10-11, second blanket sacrificial layer 38 protects Structure B gate dielectric layers while annealing drives dipole dopants into Structure A gate dielectric layers only).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to implement selective dipole drive-in operations targeting one gate region to the exclusion of another to achieve differential dipole concentrations enabling multiple threshold voltages across different gate regions of the CFET structure (Frougier, Abstract; Chan, Para [0036]).
Regarding claim 24, the combination of Zhang, Frougier, and Chan teaches the method of claim 23 as set forth above.
Zhang further teaches wherein the first gate dielectric layer and the second gate dielectric layer of the first plurality of gate dielectric layers are in different gate regions (Fig. 10-11, Structure A gate dielectric layers receive dipole dopants from dipole layer 34 during anneal while Structure B gate dielectric layers are protected, establishing that gate dielectric layers receiving different dipole dopant concentrations are located in different gate regions). Chan further teaches that gate dielectric layers in different gate regions are exposed to different numbers of anneal operations (Fig. 1, gate dielectric portions 246C and 246D are in different gate regions receiving different numbers of drive-in anneal operations).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to implement selective dipole drive-in operations such that the first gate dielectric layer and the second gate dielectric layer of the first plurality of gate dielectric layers are in different gate regions, as gate dielectric layers receiving different dipole dopant concentrations through selective drive-in operations are by definition located in different gate regions (Frougier, Abstract; Chan, Para [0036]).
Regarding claim 25, the combination of Zhang, Frougier, and Chan teaches the method of claim 9 as set forth above.
Zhang further teaches wherein one or more iterations of the second dipole loop process selectively drive the second dipole dopants into the second plurality of gate dielectric layers in one gate region to the exclusion of another gate region (Fig. 9-11, dipole layer 34 formed over Structure B gate dielectric layers and selectively driven into Structure B gate dielectric layers during anneal while Structure A is protected by second blanket sacrificial layer 38 and second sacrificial gate 36, such that second dipole dopants are driven into Structure B gate dielectric layers to the exclusion of Structure A gate dielectric layers).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to implement selective second dipole drive-in operations targeting one gate region to the exclusion of another to achieve differential dipole concentrations in the top device gate dielectric layers enabling multiple threshold voltages (Frougier, Abstract; Chan, Para [0036]).
Regarding claim 26, the combination of Zhang, Frougier, and Chan teaches the method of claim 25 as set forth above.
Zhang further teaches wherein the third gate dielectric layer and the fourth gate dielectric layer of the second plurality of gate dielectric layers are in different gate regions (Fig. 9-12, Structure B gate dielectric layers receiving dipole dopants during anneal are in a different gate region from Structure A gate dielectric layers that are protected during the same anneal step). Chan further teaches that gate dielectric layers in different gate regions are exposed to different numbers of anneal operations resulting in different dipole dopant concentrations (Fig. 1, gate dielectric portions 246C and 246D in different gate regions receiving different numbers of drive-in anneal operations).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to implement selective second dipole drive-in operations such that the third gate dielectric layer and the fourth gate dielectric layer of the second plurality of gate dielectric layers are in different gate regions, as gate dielectric layers receiving different second dipole dopant concentrations through selective drive-in operations are by definition located in different gate regions (Frougier, Abstract; Chan, Para [0036]).
Regarding claim 27, Zhang teaches a method of forming a semiconductor device (Fig. 14, semiconductor structure 100), comprising:
forming a structure having a plurality of gate dielectric layers wrapping around a plurality of channels (Fig. 14, gate dielectric layers 32 and 40 wrapping around channel material layers 18 of nanosheet stacks 20); performing a first dipole loop process to drive first dipole dopants into the first plurality of gate dielectric layers, wherein the first dipole loop process includes iteratively driving the first dipole dopants into the multiple gate regions such that in each iteration, the first dipole dopants are driven into some gate regions to the exclusion of other gate regions (Fig. 5, organic polymer layer 30 selectively exposes Structure A while protecting Structure B; Fig. 10-11, second blanket sacrificial layer 38 selectively protects Structure B while annealing drives dipole dopants into Structure A to the exclusion of Structure B); performing a second dipole loop process to drive second dipole dopants into the second plurality of gate dielectric layers, wherein the second dipole loop process includes iteratively driving the second dipole dopants into the multiple gate regions such that in each iteration, the second dipole dopants are driven into some gate regions to the exclusion of other gate regions (Fig. 9-12, dipole layer 34 selectively driven into Structure B gate dielectric layers during anneal while Structure A is protected); after performing the first and second dipole loop processes, depositing a gate metal over the first and second plurality of gate dielectric layers (Fig. 14, work function metal 40).
But Zhang does not teach a method of forming a semiconductor device, comprising: forming a CFET structure having multiple gate regions adjacent to each other, each gate region having a bottom gate portion and a top gate portion, the bottom gate portion having a first plurality of gate dielectric layers wrapping around a first plurality of channels, the top gate portion having a second plurality of gate dielectric layers wrapping around a second plurality of channels.
However, Frougier teaches forming a CFET structure having multiple gate regions adjacent to each other (Fig. 13, CFET structure 100 showing multiple gate regions along the X cross-section), each gate region having a bottom gate portion and a top gate portion (Fig. 13, each gate region includes HKMG stack 1310 wrapping around lower nanosheet channel layers 130 of the bottom FET below the dielectric separation layer forming the bottom gate portion, and upper nanosheet channel layers 130 of the top FET above the dielectric separation layer forming the top gate portion), the bottom gate portion having a first plurality of gate dielectric layers wrapping around a first plurality of channels (Fig. 13, gate dielectric of HKMG stack 1310 wrapping around lower channel layers 130), the top gate portion having a second plurality of gate dielectric layers wrapping around a second plurality of channels (Fig. 13, gate dielectric of HKMG stack 1310 wrapping around upper channel layers 130).
Thus, by using the CFET structure of Frougier in the method of Zhang, the method would comprise forming a CFET structure having multiple gate regions adjacent to each other, each gate region having a bottom gate portion having a first plurality of gate dielectric layers wrapping around a first plurality of channels and a top gate portion having a second plurality of gate dielectric layers wrapping around a second plurality of channels, performing a first dipole loop process iteratively driving first dipole dopants into some gate regions to the exclusion of other gate regions, and performing a second dipole loop process iteratively driving second dipole dopants into some gate regions to the exclusion of other gate regions.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to modify a semiconductor structure of Zhang (US11387342B1) and further integrating the CFET structure having multiple adjacent gate regions with independently processed bottom and top gate portions disclosed by Frougier (US11894436B2). The combination of these familiar elements can improve by achieving multiple threshold voltages across multiple gate regions of a CFET structure through iterative selective dipole drive-in operations (Frougier, Abstract; Zhang, col. 12; Chan, Para [0036]).
Regarding claim 28, the combination of Zhang, Frougier, and Chan teaches the method of claim 27 as set forth above.
Zhang further teaches wherein the first dipole dopants and the second dipole dopants are opposite-type dopants (col. 9, lanthanum oxide (La2O3) dipole layer may typically lower the threshold voltage of an NFET device and may typically raise the threshold voltage of a PFET device; aluminum oxide (Al2O3) dipole layer may typically increase the threshold voltage of an NFET device and may typically lower the threshold voltage of a PFET device, thereby teaching that lanthanum-based and aluminum-based dipole dopants are opposite-type dopants with respect to their threshold voltage effects on NFET and PFET devices).
It would have been obvious to a person of ordinary skill in the art to select opposite-type dipole dopants for the first and second dipole loop processes applied to the bottom gate portion and top gate portion respectively of the CFET structure of Frougier, in order to independently tune the threshold voltages of the bottom FET and top FET in opposite directions to achieve a desired complementary threshold voltage distribution across the multiple gate regions of the CFET structure (Zhang, col. 9; Frougier, Abstract).
Regarding claim 29, the combination of Zhang, Frougier, and Chan teaches the method of claim 27 as set forth above.
Zhang further teaches wherein each iteration of the first dipole loop process includes: depositing, in a number of gate regions, first dipole dopant layers over the first plurality of gate dielectric layers (Fig. 9, dipole layer 34 deposited over gate dielectric layers of both Structure A and Structure B in two gate regions); annealing to drive the first dipole dopants into the respective first plurality of gate dielectric layers (Fig. 11, annealing step drives dipole layer 34 into gate dielectric 24); and removing the first dipole dopant layers after the annealing (Fig. 12, dipole layer 34 removed from Structure A).
Chan further teaches wherein the number of gate regions increases after each iteration, and wherein each iteration after a first iteration includes driving the first dipole dopants into gate dielectric layers in gate regions driven into in a prior iteration (Fig. 1, process 402 drives dipole dopants into gate dielectric portion 246D in a first gate region during a first iteration; process 404 drives dipole dopants into both gate dielectric portion 246D of the first gate region again and gate dielectric portion 246C of a second gate region during a second iteration, wherein the number of gate regions increases from one to two and the second iteration includes driving dipole dopants into the first gate region driven into in the prior first iteration).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the invention, to implement this incrementally expanding gate region exposure scheme for the first dipole loop process in the CFET structure of Frougier, as Chan directly teaches this iterative expanding exposure pattern as a means of achieving graduated dipole dopant concentrations across multiple gate regions to produce multiple distinct threshold voltages (Chan, Fig. 1, Para [0036]; Frougier, Abstract).
Claims 2 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US11387342B1) in view of Frougier (US11894436B2), Chan (US12009400B2), and further in view of Guha (US7821081).
Regarding claims 2 and 21, the combination of Zhang, Frougier, and Chan teaches the methods of claims 1 and 9 as set forth above.
But the combination of Zhang, Frougier, and Chan does not expressly teach wherein the first dipole dopants include lanthanum, and the second dipole dopants include zinc.
However, Zhang teaches that lanthanum oxide (La2O3) is used as the dipole layer material and that after annealing, the dipole material lanthanum oxide (La2O3) can be detected within the gate dielectric layer, thereby teaching that lanthanum is the dipole dopant element driven into the gate dielectric (col. 11, the dipole material, for example lanthanum oxide (La2O3), from the dipole layer 34 can be detected within the gate layer 24 and at the interface between the gate layer 24 and the interfacial layer). Guha further teaches that zinc oxide is a suitable dipole layer material for shifting the threshold voltage of a high-k FET, wherein zinc functions as the dipole dopant element (Claim 6, a material from which the dipole layer is formed comprises zinc oxide; Claim 5, the material is selected based on a desired direction of threshold voltage shift).
It would have been obvious to a person of ordinary skill in the art to select lanthanum as the first dipole dopants and zinc as the second dipole dopants, as Zhang expressly teaches that different dipole dopant materials are selected to independently adjust threshold voltages of different FET device types (col. 9, adjusting the material of the dipole layer may be another method to alter or change the threshold voltage for the nanosheet transistors), and Guha establishes zinc oxide as a known dipole material for threshold voltage tuning.
Regarding claim 22, the combination of Zhang, Frougier, and Chan teaches the method of claim 9 as set forth above.
But the combination of Zhang, Frougier, and Chan does not expressly teach wherein the first dipole dopants include zinc, and the second dipole dopants include lanthanum.
However, Guha teaches that zinc oxide is a suitable dipole layer material for shifting the threshold voltage of a high-k FET, wherein zinc functions as the dipole dopant element (Claim 6, a material from which the dipole layer is formed comprises zinc oxide; Claim 5, the material is selected based on a desired direction of threshold voltage shift). Zhang teaches that lanthanum oxide (La2O3) can be detected within the gate dielectric layer after annealing, thereby teaching lanthanum as the dipole dopant element driven into the gate dielectric (col. 11, the dipole material, for example lanthanum oxide (La2O3), from the dipole layer 34 can be detected within the gate layer 24 and at the interface between the gate layer 24 and the interfacial layer).
It would have been obvious to a person of ordinary skill in the art to select zinc as the first dipole dopants and lanthanum as the second dipole dopants, as this represents a straightforward reversal of the dopant assignment between the bottom and top devices of the CFET structure that would be routinely considered by a person of ordinary skill in the art when independently tuning the threshold voltages of the bottom and top FET devices (Zhang, col. 9, adjusting the material of the dipole layer may be another method to alter or change the threshold voltage for the nanosheet transistors; Frougier, Abstract, achieving multiple threshold voltages through independent gate stack engineering).
Conclusion
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897
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