Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/ Restrictions
Applicant's election of group II: claims 1-16, cancellation of 17-20 and submission of new claims 21-24 in the “Response to Election / Restriction Filed - 12/03/2025”. This office action considers claims 1-16, 21-24, in “Claims - 12/03/2025”, pending for prosecution.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-4, 6, 21-22, 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 20210408234 A1 – hereinafter Huang).
Regarding Claim 1, Huang teaches a semiconductor structure (see the entire document; Fig. 2; specifically, ([0017] - [0026]), and as cited below), comprising:
a substrate (110 – Fig. 2 – [0026]);
a vertical stack comprising nanostructures (130 – [0022]), wherein the nanostructures are suspended over and vertically arranged over the substrate (110 – see Fig. 2);
a gate structure (160 – [0026]), wrapping around each of the nanostructures (130), wherein the gate structure (160) comprises a gate dielectric layer (160a, 160b) and a gate electrode (160c) formed on the gate dielectric layer (160a, 160b);
inner spacers (150 – [0026])), formed on opposite sides of the gate structure (160), between the nanostructures (130), and separating the nanostructures from each other; and
gate spacers (170 – [0025]), formed on the opposite sides of the gate structure (160) and over a topmost one of the nanostructures (top 130),
wherein the gate dielectric layer (160a, 160b) comprises a first portion (160a) formed on the nanostructures (130) and a second portion (160b) extending from the first portion ([0019] – “Si nano-sheet layers or nano-wires 130 and includes a silicon oxide (SiO.sub.2) dielectric layer 160a (“gate dielectric 160a”) with a thickness between about 1.5 nm and about 3.5 nm, a high-k dielectric 160b (e.g., a hafnium-based dielectric) (“high-k gate dielectric 160b”)”), wherein the first portion (160b) and the second portion (160a) have a first thickness (first thickness) and a second thickness (second thickness), respectively, and
wherein the first thickness is greater than the second thickness ([0019] – “dielectric
layer 160a (“gate dielectric 160a”) with a thickness between about 1.5 nm and about 3.5 nm”; [0017] – “a gate dielectric stack with a silicon oxide layer at a thickness between about 1.5 nm and about 3.5 nm and a high-k dielectric layer at a thickness of about 1.5 nm” – therefore, thickness of 160a is greater than 160b).
Regarding Claim 2, Huang teaches the semiconductor structure of claim 1, wherein a difference between the first thickness and the second thickness is in a range from about 1 nm to about 3 nm ([0017]).
Regarding Claim 3, Huang teaches the semiconductor structure of claim 1, wherein the second portion (160b) protrudes from the first portion (160a) and is in contact with the inner spacers (that is 160b is in contact with 150 as seen in Fig. 2).
Regarding Claim 4, Huang teaches the semiconductor structure of claim 3, wherein the second portion (160b) partially covers sidewalls of the inner spacers (150), such that parts of the sidewalls of the inner spacers (150) are in direct contact with the gate electrode (that is, 150 is contact with gate electrode 160c).
Regarding Claim 6, Huang teaches the semiconductor structure of claim 1, wherein the second portion (160b) is formed on sidewalls of the inner spacers (that is 160b is in contact with 150 as shown in Fig. 2).
Regarding Claim 21, Huang teaches a semiconductor structure (see the entire document; Fig. 2; specifically, ([0017] - [0026]), and as cited below), comprising:
a plurality of nanostructures (130 – Fig. 2 - [0022]), arranged over a base portion (110 – Fig. 2 – [0026]) in a vertical direction;
an isolation structure (180 – [0019]), disposed around the base portion (110);
a gate structure (160 – [0026]), comprising interfacial layers (160d) wrapped around each of the nanostructures (130), a gate dielectric layer (160a, 160b) over the interfacial layers (160d), and a gate electrode layer (160c) over the gate dielectric layer (160a, 160b), wherein the gate dielectric layer (160a, 160b) comprises horizontal portions (160a) formed on the interfacial layers (160d) and vertical portions )160b) extending from the horizontal portions (160a);
source/drain features (140 – [0019]), disposed on opposite sides of the gate structure (160) in a first direction (horizontal) and attached to the nanostructures (130), wherein the first direction is different from the vertical direction; and
inner spacers (150 – [0026]), formed on the opposite sides of the gate structure (160) in the first direction (horizontal) and between the nanostructures (130) in the vertical direction, wherein the inner spacers (150) space apart the nanostructures (130) and the source/drain features (140),
wherein a first thickness of the horizontal portions (160a) of the gate dielectric layer in the vertical direction is different from a second thickness of the vertical portions (160b) of the gate dielectric layer in the first direction ([0019] – “dielectric
layer 160a (“gate dielectric 160a”) with a thickness between about 1.5 nm and about 3.5 nm”; [0017] – “a gate dielectric stack with a silicon oxide layer at a thickness between about 1.5 nm and about 3.5 nm and a high-k dielectric layer at a thickness of about 1.5 nm”).
Regarding Claim 22, Huang teaches the semiconductor structure of claim 1, wherein each of the nanostructures (130) comprises terminal portions (end portions) connected to the source/drain features (140) and a middle portion (middle 130) extending between the terminal portions (end portions), wherein third thicknesses of the terminal portions are greater than a fourth thickness of the middle portion (Fig. 2 shows thickness of end portions of 130 is greater than middle portions of 130 due to the presence of 160d cutting into the middle 130), and wherein the inner spacers (150) are disposed between the terminal portions in the vertical direction (see Fig. 2).
Regarding Claim 24, Huang teaches the semiconductor structure of claim 21, wherein the vertical portions (160b) of the gate dielectric layer are formed on sidewalls of the inner spacers (150 – Fig. 2), and the second thickness of the vertical portions is smaller than the first thickness of the horizontal portions of the gate dielectric layer ([0019] – “dielectric layer 160a (“gate dielectric 160a”) with a thickness between about 1.5 nm and about 3.5 nm”; [0017] – “a gate dielectric stack with a silicon oxide layer at a thickness between about 1.5 nm and about 3.5 nm and a high-k dielectric layer at a thickness of about 1.5 nm” – therefore, thickness of 160a is greater than 160b).
Allowable Subject Matter
Claims 5, 7, 23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REASON FOR ALLOWANCE
Claims 8-16 are allowed over prior art.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
Regarding claim 8, the reference(s) of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge do(es) not teach or render obvious, at least to the skilled artisan, the instant invention regarding a method in their entirety (the individual limitations may be found just not in combination with proper motivation).
The most relevant prior art reference(s) (US 20210408234 A1 to Huang) substantially teach(es) some of limitations in claim 8 as indicated in the rejections of claims 1 and 21, “wherein the first gate dielectric layer comprises a first portion formed on the first nanostructures, a second portion formed on sidewalls of the first inner spacers, and a third portion formed on sidewalls of the second inner spacers, and wherein a second thickness of the second portion and a third thickness of the third portion are smaller than a first thickness of the first portion.” as recited in claim 8. Therefore, the claim 8 is deemed patentable over the prior art.
Regarding claims 9-16, they are allowed due to their dependencies on claim 1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached on (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898