DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species III, claims 1, 2, 4-13, 19 and 20, in the reply filed on 02/11/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-13 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeh et al. US 10,475,762 B1.
Regarding claims 1, 2 and 4-8, Yeh discloses:
A semiconductor device (Fig. 2), comprising:
a supporting structure (18 including 10);
a die stack (28/128), disposed over the supporting structure and comprising:
a first semiconductor die (28) comprising a substrate (19); and
a second semiconductor die (128),
wherein the first semiconductor die is between the second semiconductor die and the supporting structure, and a material of the supporting structure (18 including 10; col 2 lines 51-61) is different from a material of the substrate of the first semiconductor die (19; col 4 lines 11-16); and
a redistribution circuit structure (50), disposed over the die stack and electrically coupled (through TSVs 27 and 127) to the first semiconductor die and the second semiconductor die.
(claim 2) 18 including 10; col 2 lines 51-61.
(claims 4 and 5) Fig. 2; at least the bottom portion is electrically isolated and thermally coupled.
(claims 6 and 7) based on the materials of the supporting substrate (col 2 lines 51-61) and the substrate of the first semiconductor die (col 4 lines 11-16).
(claim 8) as noted in col 9 lines 1-17; die 28 and 128 can be configured face to face in Fig. 2, thereby having a metal-to-metal bonding region and dielectric-to-dielectric bonding region.
Regarding claims 9-13, Yeh discloses:
A semiconductor device (Figs. 1E and 2), comprising:
at least one first die (28) comprising a substrate (19), having a first back side (bottom) and a first front side (top) opposite to the first back side;
a supporting carrier (18 including 10), disposed on the first back side of the at least one first die, wherein a thermal conductivity of the supporting carrier is greater than a thermal conductivity of the substrate of the at least one first die (based on material choice of 18 including 10; col 2 lines 51-61 and 19; col 4 lines 11-16);
a routing structure (50), disposed on and electrically coupled (through TSVs 27 and 127) to the at least one first die; and
a plurality of terminals (51), disposed over and electrically coupled to the routing structure.
(claim 10) col 5 lines 4-20; 28 bonded to 18 using metal-to-metal and dielectric-to-dielectric bonding.
(claim 11) based on the materials of the supporting substrate (col 2 lines 51-61) and the substrate of the first semiconductor die (col 4 lines 11-16).
(claim 12) as shown in Fig. 2; at least one second die (128).
(claim 13) as noted in col 9 lines 1-17; die 28 and 128 can be configured face to face in Fig. 2, thereby having a metal-to-metal bonding region and dielectric-to-dielectric bonding region.
Regarding claims 19, Yeh discloses:
A method of manufacturing a semiconductor device (Fig. 2), comprising:
bonding at least one first die (28) to at least one second die (128), the at least one first die comprising a substrate (19) and having a first back side (bottom) and a first front side (top) opposite to the first back side, and the at least one second die (128) being mounted to the first front side of the at least one first die;
bonding a supporting carrier (18 including 10) to the first back side of the at least one first die, a material of the supporting carrier (18 including 10; col 2 lines 51-61) is different from a material of the substrate of the at least one first die (19; col 4 lines 11-16);
forming a routing structure (50) on and electrically coupled (through TSVs 27 and 127) to the at least one second die; and
disposing a plurality of terminals (51) over and electrically coupled to the routing structure, the routing structure being disposed between the plurality of terminals and the at least one second die.
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to teach or clearly suggest the limitation of claim 20 stating “wherein prior to bonding the supporting carrier to the first back side of the at least one first die and after bonding the at least one first die to the at least one second die, the method further comprises: thinning down the substrate of the at least one first die from the first back side”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERROL V FERNANDES/Primary Examiner, AU 2893