Prosecution Insights
Last updated: October 01, 2026
Application No. 18/332,761

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Final Rejection §102
Filed
Jun 12, 2023
Examiner
FERNANDES, ERROL V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
701 granted / 821 resolved
+17.4% vs TC avg
Moderate +11% lift
Without
With
+10.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
22 currently pending
Career history
830
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.3%
+22.3% vs TC avg
§102
33.3%
-6.7% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 821 resolved cases

Office Action

§102
DETAILED ACTION The following office action is being sent in response to the applicant’s amendments mailed on 06/23/2026. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 2 and 4-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeh et al. US 10,475,762 B1. Regarding claims 1, 2 and 4-8, Yeh discloses: A semiconductor device (Fig. 2), comprising: a supporting structure (18 including 10); a die stack (28/128), disposed over the supporting structure and comprising: a first semiconductor die (28) comprising a substrate (19); and a second semiconductor die (128), wherein the first semiconductor die is between the second semiconductor die and the supporting structure, and a material of the supporting structure (18 including 10; col 2 lines 51-61) is different from a material of the substrate of the first semiconductor die (19; col 4 lines 11-16); and a redistribution circuit structure (50), disposed over the die stack and electrically coupled (through TSVs 27 and 127) to the first semiconductor die and the second semiconductor die, wherein an interface between the supporting structure and the die stack is free of a metal region (col 4 lines 2-17; 26 includes 24 dielectric layer while col 3 lines 20-40; 15 includes 13 dielectric layer ... 24 and 13 at least contact each other thereby meeting the claim requirement). (claim 2) 18 including 10; col 2 lines 51-61. (claims 4 and 5) Fig. 2; at least the bottom portion is electrically isolated and thermally coupled. (claims 6 and 7) based on the materials of the supporting substrate (col 2 lines 51-61) and the substrate of the first semiconductor die (col 4 lines 11-16). (claim 8) as noted in col 9 lines 1-17; die 28 and 128 can be configured face to face in Fig. 2, thereby having a metal-to-metal bonding region and dielectric-to-dielectric bonding region. Allowable Subject Matter Claims 9-13, 19 and 20 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or clearly suggest the limitation of claims 9 and 19 stating “the substrate of the at least one first die is directly bonded to the supporting carrier”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on (571) 270-30423042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Show 1 earlier event
Mar 23, 2026
Non-Final Rejection mailed — §102
Apr 21, 2026
Interview Requested
Apr 28, 2026
Applicant Interview (Telephonic)
Apr 28, 2026
Examiner Interview Summary
Jun 23, 2026
Response Filed
Aug 12, 2026
Final Rejection mailed — §102
Sep 21, 2026
Examiner Interview Summary
Sep 21, 2026
Applicant Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12745469
SOLID-STATE IMAGING ELEMENT AND IMAGING SYSTEM
4y 1m to grant Granted Sep 22, 2026
Patent 12740098
TRANSISTORS WITH MITIGATED FREE BODY EFFECT
3y 0m to grant Granted Sep 15, 2026
Patent 12740124
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING
3y 0m to grant Granted Sep 15, 2026
Patent 12727494
SEMICONDUCTOR PACKAGE INCLUDING INTERPOSER
3y 9m to grant Granted Sep 01, 2026
Patent 12727460
INTEGRATED CIRCUIT STRUCTURE WITH RECESSED TRENCH CONTACT AND DEEP BOUNDARY VIA
3y 9m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+10.8%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 821 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month