DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Do(USPGPUB DOCUMENT: 2016/0300817, hereinafter Do) in view of Lin (USPGPUB DOCUMENT: 2014/0252573, hereinafter Lin).
Re claim 1 Do discloses in Fig 5g (flipped 180 degrees) a modular semiconductor device(left/right 240/220), comprising: an encapsulant layer(240) with an encapsulant bottom surface(bottom of 240) and an encapsulant top surface(top of 240), wherein the encapsulant layer(240) comprises a component region(region of left/right 124); a semiconductor component(324/124) disposed within the component region(region of left/right 124), wherein the semiconductor component(324/124) comprises a component conductive pattern(332/132/334/134) exposed from the encapsulant bottom surface(bottom of 240); and an interposer layer(210/340) laminated on the encapsulant layer(240) and having an interposer bottom surface(top/bottom of 210/340) and an interposer top surface(top/bottom of 210/340), wherein the interposer top surface(top/bottom of 210/340) is in contact with the encapsulant bottom surface(bottom of 240);
Do does not discloses wherein the encapsulant layer comprises an interlayer connection region; an interlayer connection array disposed within the interlayer connection region, wherein the interlayer connection array comprises one or more conductive vias each extending between the encapsulant bottom surface and the encapsulant top surface; wherein the interposer layer(210/340) comprises an interposer conductive pattern on the interposer bottom surface(top/bottom of 210/340), and an interposer interconnection structure(222) which is electrically coupled to the component conductive pattern(332/132/334/134), the interposer conductive pattern and the one or more conductive vias(280).
Lin discloses wherein the encapsulant layer(364) comprises an interlayer connection region(region of 350); an interlayer connection array(array of 356) disposed within the interlayer connection region(region of 350), wherein the interlayer connection array(array of 356) comprises one or more conductive vias(left/right 356) each extending between the encapsulant bottom surface(bottom of 350) and the encapsulant top surface(top of 350); wherein the interposer layer(360/402/406) comprises an interposer conductive pattern(left/right408) on the interposer bottom surface, and an interposer interconnection structure(358b/left404/right404) which is electrically coupled to the interposer conductive pattern and the one or more conductive vias(left/right 356).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lin to the teachings of Do in order to have improvements in electrical interconnection and packaging materials [0008, Lin]. In doing so, and an interposer interconnection structure(358b/404 of Lin) which is electrically coupled to the component conductive pattern(332/132/334/134 of Do),
Re claim 2 Do and Lin disclose the modular semiconductor device of claim 1, wherein the semiconductor component(324/124) comprises a semiconductor die or a semiconductor package.
Re claim 3 Do and Lin disclose the modular semiconductor device of claim 1, wherein the conductive vias(280) comprises conductive posts, conductive pillars or solder balls.
Re claim 4 Do and Lin disclose the modular semiconductor device of claim 1, wherein the encapsulant layer(240) has a thickness equal to that of the semiconductor component(324/124).
Re claim 5 Do and Lin disclose the modular semiconductor device of claim 1, wherein the modular semiconductor device(left/right 240/220) is formed as a single piece.
Re claim 6 Do discloses in Fig 5g (flipped 180 degrees) an electronic device, comprising:
a substrate(372) comprising a substrate interconnection structure (366/364/362/360 in 372);a base semiconductor(left/right 324) component mounted on the substrate and electrically coupled to the substrate interconnection structure (by way of 334); one or more base vias(left/right 280) mounted on the substrate and electrically coupled to the substrate interconnection structure;
a first modular semiconductor device stacked over the base semiconductor component and the one or more base vias,
wherein the first modular semiconductor device(left/right 240/220) comprises: an encapsulant layer(240) with an encapsulant bottom surface(bottom of 240) and an encapsulant top surface(top of 240), wherein the encapsulant layer(240) comprises a component region(region of left/right 124);
a semiconductor component(324/124) disposed within the component region(region of left/right 124), wherein the semiconductor component(324/124) comprises a component conductive pattern(332/132/334/134) exposed from the encapsulant bottom surface(bottom of 240); and an interposer layer(210/340) laminated on the encapsulant layer(240) and having an interposer bottom surface(top/bottom of 210/340) and an interposer top surface(top/bottom of 210/340), wherein the interposer top surface(top/bottom of 210/340) is in contact with the encapsulant bottom surface(bottom of 240);
Do does not discloses wherein the encapsulant layer(240) comprises an interlayer connection region(region of 210/340); an interlayer connection array(array of 280) disposed within the interlayer connection region(region of 210/340),wherein the interlayer connection array(array of 280) comprises one or more conductive vias(280) each extending between the encapsulant bottom surface(bottom of 240) and the encapsulant top surface(top of 240); and wherein the interposer layer(210/340) comprises an interposer conductive pattern on the interposer bottom surface(top/bottom of 210/340), and an interposer interconnection structure(222) which is electrically coupled to the component conductive pattern(332/132/334/134), the interposer conductive pattern and the one or more conductive vias(280); and wherein the interposer conductive pattern is electrically coupled to the one or more base vias.
Lin discloses a substrate(substrate of 124) comprising a substrate interconnection structure(132); a base semiconductor component(124) mounted on the substrate and electrically coupled to the substrate interconnection structure (by way of centermost404/132); wherein the encapsulant layer (364) comprises an interlayer connection region (region of 350); an interlayer connection array (array of 356) disposed within the interlayer connection region (region of 350),wherein the interlayer connection array (array of 356) comprises one or more conductive vias (left/right 356) each extending between the encapsulant bottom surface(bottom of 350) and the encapsulant top surface(top of 350);
and wherein the interposer layer (360/402/406) comprises an interposer conductive pattern (left/right408) on the interposer bottom surface, and an interposer interconnection structure (358b/left404/right404) which is electrically coupled to the interposer conductive pattern and the one or more conductive vias (left/right 356);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lin to the teachings of Do in order to have improvements in electrical interconnection and packaging materials [0008, Lin]. In doing so, and an interposer interconnection structure(358b/404 of Lin) which is electrically coupled to the component conductive pattern(332/132/334/134 of Do), and wherein the interposer conductive pattern(left/right408) is electrically coupled to the one or more base vias (left/right 280 of Do).
Re claim 7 Do and Lin disclose the electronic device of claim 6, further comprising one or more additional modular semiconductor devices stacked over the first modular semiconductor device(left/right 240/220), wherein the one or more additional modular semiconductor devices have a structure substantially the same as that of the first modular semiconductor device(left/right 240/220), and wherein the first modular semiconductor device(left/right 240/220) and the one or more additional modular semiconductor devices are electrically coupled together through their respective conductive vias(280) and interposer layer(210/340)s.
Re claim 8 Do and Lin disclose the electronic device of claim 6, wherein the base semiconductor component does not fully overlap with the first modular semiconductor device(left/right 240/220).
Re claim 9 Do and Lin disclose the electronic device of claim 6, wherein the one or more base vias(114 of Lin) has a thickness equal to that of the base semiconductor component.
Re claim 10 Do and Lin disclose the electronic device of claim 6, wherein the semiconductor component(324/124) of the first modular semiconductor device(left/right 240/220) comprises a semiconductor die or a semiconductor package.
Re claim 11 Do and Lin disclose the electronic device of claim 6, wherein the conductive vias(280) comprises conductive posts, conductive pillars or solder balls.
Re claim 12 Do and Lin disclose the electronic device of claim 6, wherein the encapsulant layer(240) has a thickness equal to that of the semiconductor component(324/124).
Re claim 13 Do and Lin disclose the electronic device of claim 6, wherein the modular semiconductor device(372/348 of Do) is formed as a single piece.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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