DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Applicant
This Office Action is in response to Applicant’s reply filed on 20 August 2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claim(s) 1-8 is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Tada et al. (U.S. Pub. 2001/0048122).
Claim 1: Tada et al. discloses a semiconductor device, in Fig. 2 and in paragraphs 81 and 82, comprising:
a substrate (1);
a first doped region (3 and 6) disposed in the substrate (1) and doped with a first doping polarity (n-type);
a second doped region (2) disposed in the substrate (1) and horizontally outside the first doped region (3 and 6), the second doped region (2) being doped with a second doping polarity (p-type) opposite to the first doping polarity (n-type);
a third doped region (4 on the left) disposed completely within (completely within 3) the first doped region (3 and 6), the third doped region (4 on the left) being doped with the second doping polarity (p-type);
a first isolation structure (8 on the right) disposed over the first doped region (3 and 6) and spaced apart from the second doped region (2) and the third doped region (4 on the left);
a second isolation structure (7) disposed over the first doped region (3 and 6) and the third doped region (4 on the left); and
a resistor (10) disposed over the first isolation structure (8 on the right),
wherein a bottommost surface (a bottommost surface of 8 on the right that is in contact with 6) of the first isolation structure (8 on the right) is on a surface (upper surface of 6) of the first doped region (3 and 6).
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Claim 2: Tada et al. discloses the semiconductor device of claim 1, and in Fig. 2, further discloses wherein the first doped region (3 and/or 6) and the second doped region (2) form a first P/N junction (junction where elements 2 and 3 meet), and
the first doped region (3 and/or 6) and the third doped region (4 on the left) form a second P/N junction (junction where elements 3 and 4 on the left meet).
Claim 3: Tada et al. discloses the semiconductor device of claim 2, and in Fig. 2, further discloses wherein the third doped region (4 on the left) is spaced apart from the second isolation structure (7).
Claim 4: Tada et al. discloses the semiconductor device of claim 1, and in Fig. 2, further discloses wherein the resistor (10) is electrically coupled to the first doped region (3 and/or 6).
Claim 5: Tada et al. discloses the semiconductor device of claim 1, and in Fig. 2 and in paragraph 81, further discloses comprising a field plate (13) disposed over a portion of the second doped region (2) and electrically coupled to the second doped region (2).
Claim 6: Tada et al. discloses the semiconductor device of claim 1, and in Fig. 2 and in paragraph 81, further discloses wherein the first doped region (3 and/or 6) includes a drift region (3) and a doped well (6) in the drift region (3), wherein the drift region (3) has a lower doping concentration level than the doped well (6)
Since regions 3 and 6 of Tada et al. are regions within the substrate 1, Tada et al. would disclose the doped well (4) extends to the substrate (1).
Claim 7: Tada et al. discloses the semiconductor device of claim 6, and in Fig. 2, further discloses wherein the third doped region (4) is embedded in the drift region (3) and adjacent to the doped well (6).
Claim 8: Tada et al. discloses the semiconductor device of claim 1, and in Fig. 2 and in paragraph 81, further discloses comprising a first heavily doped region (6) disposed in the first doped region (3) and a second heavily doped region (5) disposed in the second doped region,
wherein the first heavily doped region (6) is disposed between the first isolation structure (8 on the right) and the second isolation structure (7).
Claim(s) 21, 22 and 26 is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Kim et al. (U.S. Pub. 2008/0135970).
Claim 21: Kim et al. discloses a semiconductor device, in Fig. 3A and in paragraphs 34-38, comprising:
a substrate (100);
a first doped region (102 and 104) disposed in the substrate (100);
a second doped region (region of 100 to the left of 102) disposed adjacent to the first doped region (102 and 104) and being doped oppositely from the first doped region (102 and 104), wherein the first doped region (102 and 104) and the second doped region (region of 100 to the left of 102) form a P/N junction (junction where 102 and the region of 100 to the left of 102 meet);
a first isolation structure (118 on the left) disposed directly over the first doped region (102 and 104);
a second isolation structure (108 on the right) disposed over the first doped region (102 and 104) and adjacent to the second doped region (region of 100 to the left of 102),
a first heavily doped region (114 on the right) disposed in the first doped region (102 and 104) and between the first isolation structure (118 on the left) and the second isolation structure (108 on the right),
a second heavily doped region (110 on the left) disposed in the second doped region (region of 100 to the left of 102),
wherein the second heavily doped region (110 on the left) is electrically grounded,
wherein a portion (104 on the right) of the first doped region (102 and 104) is laterally sandwiched by the second doped region (region of 100 to the left of 102) and the second isolation structure (108 on the right).
Claim 22: Kim et al. discloses the semiconductor device of claim 21, and in Fig. 3A, further discloses comprising a resistor (122) disposed over the first isolation structure (118 on the left) and electrically connected (through elements of the device) to the first doped region (102).
Claim 26: Kim et al. discloses the semiconductor device of claim 21, and in Fig. 3A and in paragraph 35, further discloses comprising a field plate (112 on the left) disposed over the second heavily doped region (110 on the left) and electrically grounded.
Response to Arguments
Applicant's arguments filed 20 August 2025 have been fully considered but they are not persuasive.
Applicant contends Tada et al. does not disclose “a bottommost surface of the first isolation structure is on a surface of the first doped region” as recited in claim 1.
Examiner notes Tada et al. in Fig. 2 discloses a bottommost surface (bottom surface of 8 on the right) of the first isolation structure (8 on the right) is on a surface (upper surface of 6) of the first doped region (3 and/or 6).
Applicant contends insulating layer 118 of Kim et al. contacts only one of cathode contact region 114 on the left and cathode contact region 114 on the right, and does not extend from cathode contact region 114 on the left to cathode contact region 114 on the right, and therefore would not disclose “the first isolation structure extends continuously from the first heavily doped region to the second heavily doped region” as recited in claim 16.
Examiner notes that the claim does not require the first isolation structure to contact and extend from the first and second heavily doped regions. To extend continuously is broad and can be interpreted as a monolithic element that does not have to touch the two elements that is extends from. Therefore, Kim et al. in Fig. 3A discloses the first isolation structure (118 on the left) extends continuously from the first heavily doped region (114 on the left) and the second heavily doped region (114 on the right).
Applicant contends Kim et al. does not disclose “a portion of the first doped region is laterally sandwiched by the second doped region and the second isolation structure” as recited in claim 21.
Examiner notes Kim et al. in Fig 3A discloses a portion (104 on the right) of the first doped region (102 and 104) is laterally sandwiched by the second doped region (region of 100 to the left of 102) and the second isolation structure (108 on the right).
Allowable Subject Matter
Claims 16-20 are allowable over the prior art of record.
The following is an examiner’s statement of reasons for indicating allowable subject matter. The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, the first isolation structure extends continuously from the first heavily doped region and the second heavily doped region, as required by claim 16.
Claims 17-20 depend either directly or indirectly from claim 16 and are allowable for the same reason.
Claims 23-25 and 27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, wherein a non-distal portion of the resistor is electrically connected to the first doped region, and
wherein a first distal portion of the resistor is connected to a voltage of greater than 100 volts and a second distal portion of the resistor is electrically grounded, as required by claim 23.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, a third doped region embedded in the first doped region and below the second isolation structure,
wherein the third doped region is doped oppositely from the first doped region, as required by claims 24 and 25.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, a field plate disposed on top surfaces of the second isolation structure and the second doped region,
wherein the field plate is electrically grounded, as required by claim 27.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN LIN whose telephone number is (571)270-1274. The examiner can normally be reached Monday-Friday 10am-6pm EST.
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/J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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