DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Response to Applicant
This Office Action is in response to Applicant’s reply filed on 12 February 2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claim(s) 1-4, 6, 7 and 16 is/are rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Banerjee et al. (U.S. Pub. 2011/0042726).
Claim 1: Banerjee et al. discloses a semiconductor device, in Fig. 3, comprising:
a substrate (31; paragraph 28);
a first doped region (33 and/or 36; paragraphs 28 and 30) disposed in the substrate (31) and doped with a first doping polarity (n-type);
a second doped region (region of 31 to the right of 33) disposed in the substrate (31) and horizontally outside the first doped region (33 and/or 36), the second doped region (region of 31 to the right of 33) being doped with a second doping polarity (p-type) opposite to the first doping polarity (n-type);
a third doped region (34; paragraph 28) disposed completely within the first doped region (33 and 36), the third doped region (34) being doped with the second doping polarity (p-type);
a first isolation structure (left 38; paragraph 28) disposed over the first doped region (33 and 36) and spaced apart from the second doped region (region of 31 to the right of 33) and the third doped region (34) (paragraph 35);
a second isolation structure (middle 38; paragraph 28) disposed over the first doped region (33 and 36) and the third doped region (34); and
a resistor (39; paragraph 28) disposed over the first isolation structure (left 38),
wherein a bottommost surface (a bottommost surface of left 38) of the first isolation structure (left 38) is on a top surface (top surface of 33 and 36) of the first doped region (33 and/or 36),
wherein a sidewall (right sidewall of left 38) of the first isolation structure (left 38) interfaces with a sidewall (left sidewall of 36) of the first doped region (33 and/or 36).
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Claim 2: Banerjee et al. discloses the semiconductor device of claim 1, and in Fig. 3, further discloses wherein the first doped region (33 and/or 36) and the second doped region (region of 31 to the right of 33) form a first P/N junction (junction where elements 33 and 31 meet), and
the first doped region (33 and 36) and the third doped region (34) form a second P/N junction (junction where elements 33 and 34 meet).
Claim 3: Banerjee et al. discloses the semiconductor device of claim 2, and in Fig. 3, further discloses wherein the third doped region (34) is spaced apart from the second isolation structure (middle 38).
Claim 4: Banerjee et al. discloses the semiconductor device of claim 1, and in Fig. 3, further discloses wherein the resistor (39) is electrically coupled to the first doped region (33 and/or 36).
Claim 6: Banerjee et al. discloses the semiconductor device of claim 1, and in Fig. 3, further discloses wherein the first doped region (33 and/or 36) includes a drift region (33) and a doped well (36) in the drift region (33), wherein the drift region (33) has a lower doping concentration level than the doped well (36)
Claim 7: Banerjee et al. discloses the semiconductor device of claim 6, and in Fig. 3, further discloses wherein the third doped region (34) is embedded in the drift region (33) and adjacent to the doped well (36).
Claim 16: Banerjee et al. discloses a semiconductor device, in Fig. 3, comprising:
a first doped region (33; paragraph 28) disposed surrounded by a second doped region (31; paragraph 28), wherein the first doped region (33) is doped with a first doping polarity (n-type), and wherein the second doped region (31) is doped with a second doping polarity (p-type) opposite to the first doping polarity;
a first isolation structure (middle 38; paragraph 28) disposed directly over the first doped region (33);
a first heavily doped region (36; paragraph 30) and a second heavily doped region (37; paragraph 30) disposed completely in the first doped region (33), wherein the first isolation structure (middle 38) extends continuously from the first heavily doped region (36) to the second heavily doped region (37);
a second isolation structure (left 38; paragraph 30) and a third isolation structure (right 38; paragraph 30) disposed adjacent to the first heavily doped region (36) and the second heavily doped region (37), respectively;
a first field plate (42; paragraph 29) disposed over the second isolation structure (left 38), wherein a portion of the first field plate (41) is over the second doped region (31); and
a second field plate (43; paragraph 29) disposed over the third isolation structure (right 38), wherein a portion of the second field plate (43) is over the second doped region (31).
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Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 8 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Banerjee et al. as applied to claim 1 above, and further in view of Kim et al. (U.S. Pub. 2008/0135970).
Claim 5: Banerjee et al. discloses the semiconductor device of claim 1.
Banerjee et al. appears not to explicitly disclose a field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.
Kim et al., however, in Fig. 3A, discloses a field plate (112 on the left; paragraph 35) disposed over a portion of the second doped region (region of 100 to the left of 102; paragraph 34) and electrically coupled to the second doped region (region of 100 to the left of 102; paragraph 34).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Banerjee et al. with the disclosure of Kim et al. to have made a field plate disposed over a portion of the second doped region and electrically coupled to the second doped region in order to reduce noise by having a ground connection to the substrate.
Claim 8: Banerjee et al. discloses the semiconductor device of claim 1, and in Fig. 3, further discloses comprising a first heavily doped region (36; paragraph 30) disposed in the first doped region (33 and/or 36),
wherein the first heavily doped region (36) is disposed between the first isolation structure (left 38) and the second isolation structure (middle 38).
Banerjee et al. appears not to explicitly disclose a second heavily doped region disposed in the second doped region.
Kim et al., however, in Fig. 3A, discloses a second heavily doped region (110 on the left; paragraph 35) disposed in the second doped region (region of 100 to the left of 102; paragraph 34).
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Banerjee et al. with the disclosure of Kim et al. to have made a second heavily doped region disposed in the second doped region in order to reduce noise by having a ground connection to the substrate.
Claims 21, 22 and 24-26 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Banerjee et al. (U.S. Pub. 2011/0042726) in view of Kim et al. (U.S. Pub. 2008/0135970).
Claim 21: Banerjee et al. discloses a semiconductor device, in Fig. 3, comprising:
a substrate (31; paragraph 28);
a first doped region (33; paragraph 28) disposed in the substrate (31);
a second doped region (region of 31 to the right of 33; paragraph 28) disposed adjacent to the first doped region (33) and being doped oppositely from the first doped region (33), wherein the first doped region (33) and the second doped region (region of 31 to the right of 33) form a P/N junction (junction where 33 and region of 31 to the right of 33 meet);
a first isolation structure (left 38; paragraph 28) disposed directly over the first doped region (33);
a second isolation structure (middle 38; paragraph 28) disposed over the first doped region (33) and adjacent to the second doped region (region of 31 to the right of 33),
a first heavily doped region (36; paragraph 30) disposed in the first doped region (33) and between the first isolation structure (left 38) and the second isolation structure (middle 38),
wherein a first portion (portion of 33 to the left of middle 38) of the first doped region (33) is laterally sandwiched by the second doped region (region of 31 to the right of 33) and the second isolation structure (middle 38),
wherein the second isolation structure (middle 38) has a first sidewall (left sidewall) interfacing with the first portion (portion of 33 to the left of middle 38) of the first doped region (33) and a second sidewall (right sidewall) interfacing with a second portion (portion of 33 to the right of middle 38) of the first doped region (33).
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Banerjee et al. appears not to explicitly disclose a second heavily doped region disposed in the second doped region,
wherein the second heavily doped region is electrically grounded.
Kim et al., however, in Fig. 3A, discloses a second heavily doped region (110 on the left; paragraph 35) disposed in the second doped region (region of 100 to the left of 102; paragraph 34),
wherein the second heavily doped region (110 on the left) is electrically grounded.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Banerjee et al. with the disclosure of Kim et al. to have made a second heavily doped region disposed in the second doped region,
wherein the second heavily doped region is electrically grounded in order to reduce noise by having a ground connection to the substrate.
Claim 22: Banerjee et al. in view of Kim et al. discloses the semiconductor device of claim 21, and Banerjee et al. in Fig. 3A, further discloses comprising a resistor (39; paragraph 28) disposed over the first isolation structure (left 38) and electrically connected to the first doped region (33).
Claim 24: Banerjee et al. in view of Kim et al. discloses the first semiconductor device of claim 21, and Banerjee et al. in Fig. 3A, further discloses comprising a third doped region (35; paragraph 28) embedded in the first doped region (33) and below the second isolation structure (middle 38),
wherein the third doped region (35) is doped oppositely from the first doped region (33).
Claim 25: Banerjee et al. in view of Kim et al. discloses the first semiconductor device of claim 24, and Banerjee et al. in Fig. 3A, further discloses wherein the third doped region (35) is spaced apart from the second isolation structure (middle 38) (paragraph 35).
Claim 26: Banerjee et al. in view of Kim et al. discloses the semiconductor device of claim 21.
Banerjee et al. in view of Kim et al., as applied to claim 21, appears not to explicitly disclose a field plate disposed over the second heavily doped region and electrically grounded.
Kim et al., however, in Fig 3A, further discloses a field plate (112 on the left; paragraph 35) disposed over the second heavily doped region (110 on the left; paragraph 35) and electrically grounded.
It would have been obvious to one of ordinary skill in the art before the time of effective filing of the invention to modify Banerjee et al. in view of Kim et al., as applied to claim 21, with the further disclosure of Kim et al. to have made a field plate disposed over the second heavily doped region and electrically grounded in order to be able to apply ground to the device.
Allowable Subject Matter
Claims 17-20, 23 and 27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, a resistor disposed directly over the first isolation structure and electrically coupled to the first heavily doped region, as required by claim 17.
Claim 18 depends from claim 17 and is allowable for the same reason.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, a third heavily doped region and a fourth heavily doped region disposed in the second doped region; and
a third field plate over the third heavily doped region and a fourth field plate over the fourth heavily doped region,
wherein the first field plate is on a top surface of the second isolation structure, and the second filed plate is on a top surface of the third isolation structure, as required by claim 19.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, wherein the first doped region includes a doped well inside a drift region,
wherein the drift region has a lower doping concentration level than the doped well, and
wherein the first heavily doped region, the second heavily doped region, and a portion of the first isolation structure are disposed in the doped well, as required by claim 20.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, wherein a non-distal portion of the resistor is electrically connected to the first doped region, and
wherein a first distal portion of the resistor is connected to a voltage of greater than 100 volts and a second distal portion of the resistor is electrically grounded, as required by claim 23.
The prior art of record, either singularly or in combination, does not suggest, in combination with the other claim limitations, a field plate disposed on top surfaces of the second isolation structure and the second doped region,
wherein the field plate is electrically grounded, as required by claim 27.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8, 16, 21, 22 and 24-26 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/J.L/ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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