Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species IV in the reply filed on 2/11/2026 is acknowledged.
Claims 4,10-14,18-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected Species I-III, V-VI claims (claims 4,10,18-19 due to third via and claims 11-14 due to second semiconductor device), there being no allowable generic or linking claim. Election was made without traverse in the reply filed.
Claim Objections
Claim 17 is objected to because of the following informalities: “a pair source/drain structures” in line 2. For the purpose of examination, it is being considered as “a pair of source/drain structures”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
1. Claim(s) 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200388571 A1 (Huang) in view of US 20210391318 A1 (Peng).
Regarding claim 1, Huang shows (Fig. 1) a semiconductor structure, comprising:
a substrate (10, para 17) having a first surface (top) and a second surface (bottom) opposite the first surface;
a semiconductor device (1, para 17) disposed on the first surface;
a first conductive via (24, para 17) and a second conductive via (23, para 17) coupled in parallel to one another, the first conductive via and the second conductive via; and
an electrical fuse (110, para 17) disposed over the semiconductor device.
Huang does not show a metallization layer disposed on the second surface;
the first conductive via and the second conductive via extending from the second surface toward the first surface;
electrical fuse coupled to the first and second conductive vias.
Peng shows (Fig. 2A) a metallization layer (210A, para 42) disposed on the second surface;
conductive via (250A, 260A para 42) extending from the second surface (bottom of 200A) toward the first surface (top of 200A).
Hung in combination with Peng teaches that electrical fuse can similarly be coupled to the first and second conductive vias extending from the second surface toward the first surface.
It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Peng, with backside metallization, to the invention of Huang.
The motivation to do so is that the combination results in higher gate density (para 40).
Regarding claim 2, Huang as previously modified with Peng shows wherein the semiconductor device includes a gate structure (Peng, 220B, para 45) interposed between a pair of source/drain structures (Peng 262A, 262B, para 45) and wherein the first conductive via (Peng 250A) is coupled to a bottom surface of one of the source/drain structures from the second surface.
Allowable Subject Matter
Claims 3,5-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the second conductive via extends through at least the substrate to couple the first metallization layer to the second metallization layer”.
Regarding claim 5, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “wherein the electrical fuse is disposed in a third metallization layer over the second metallization layer”.
Regarding claim 6, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “the second conductive via has a second cross-sectional area that is greater than the first cross-sectional area”.
Claims 7-9,15-17,20 are allowed.
Regarding claim 7, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “second via coupled to the first via in parallel and extending through at least the substrate to couple the second metallization layer to the first metallization layer” when taken in combination with all the remaining limitations of the independent claim.
Regarding claim 16, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “forming a second via extending from the backside to the first metallization layer, the second via being coupled to the first via in parallel” when taken in combination with all the remaining limitations of the independent claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m..
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/WASIUL HAIDER/Primary Examiner, Art Unit 2812