DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/15/2026 has been entered.
Response to Arguments
Applicant’s response has been fully considered.
Applicant’s amendments and the accompanying arguments with respect to the first and fifth transistors being of a first conductivity type and the second transistor being of a second conductivity type opposite the first conductivity type, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Nii (US 2003/0185044).
Claim Objections
Claim 1 is objected to because of the following informalities: the word “conductive” at the end of line 11 should be changed to “conductivity.” Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 8 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Nii (US 2003/0185044).
In reference to claim 1, Nii (US 2003/0185044), hereafter “Nii,” discloses a semiconductor device, with reference to Figure 15, comprising:
first, second, third, fourth, and fifth active regions, (annotated 1-5 in Figure 15 reproduced below), each extending lengthwise along a first direction, vertical, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors, N2, P2, N7, N3, respectively, and the fifth active region comprises channel regions and S/D regions of fifth, N6, and sixth, N5, transistors; and
first, second, third, fourth, fifth, and sixth gates, PL2, PL3, PL4 each extending lengthwise along a second direction, horizontal, perpendicular to the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively,
wherein: the first, N2, and fifth, N6, transistors are of a first conductivity type, (n-type),
the second transistor P2 is of a second conductivity type opposite the first conductivity type, (p-type) paragraphs 58, 141, and 142,
the first, second, and fifth gates are electrically connected, (by PL2) paragraph 143, and
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[AltContent: textbox (2nd )][AltContent: textbox (5th )][AltContent: textbox (3rd )][AltContent: textbox (4th )] the fifth active region is disposed between the second and third active regions.
In reference to claim 8, Nii discloses a non-functional gate, PL1, configured to engage an end portion of the second active region, wherein the non-functional gate and the sixth gate, PL1 of N5, are aligned on a straight line, Figure 15.
Allowable Subject Matter
Claims 2-7, 9, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein the first, second, and fifth gates are aligned on a straight line with the second gate between the first and fifth gates; in combination with the other recited limitations in the base claim.
Claim 3 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein the third, fourth, and sixth gates are aligned on a straight line with the third gate between the fourth and sixth gates; in combination with the other recited limitations in the base claim.
Claim 4 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, the third gate, and the fourth gate are electrically connected; in combination with the other recited limitations in the base claim.
Claim 5 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate are electrically connected; in combination with the other recited limitations in the base claim.
Claim 6 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein the first active region comprises a channel region and S/D regions of a seventh transistor, and the fourth active region comprises a channel region and S/D regions of an eighth transistor; in combination with the other recited limitations in the base claim.
Claim 7 depends on claim 6 and would allowable in combination with the other recited limitation in the respective base claims.
Claim 9 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein a conductive feature extending lengthwise along the second direction and electrically connected to one of the S/D regions of the second transistor, wherein the conductive feature extends across the fifth active region; in combination with the other recited limitations in the base claim.
Claim 10 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein the first, fourth, fifth, and sixth transistors are of a first conductivity type, and the second and third transistors are of a second conductivity type opposite the first conductive type; in combination with the other recited limitations in the base claim.
Claims 11-20 are allowed.
In reference to claim 11, the prior art of record to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding the gate stacks of the first, second, and fifth transistors, one of the S/D regions of the third transistor, and one of the S/D regions of the fourth transistor are electrically connected; in combination with the other recited limitations. Claims 12-16 depend on claim 11.
In reference to claim 17, the prior art of record to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding a first write port portion; a second write port portion; and a read port portion disposed between the first write port portion and the second write port portion; in combination with the other recited limitations. Claims 18-20 depend on claim 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R JUNGE/Primary Examiner, Art Unit 2897