Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10, 13-18 and 35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Prechtl et al. (Pub. No.: US 2013/0299842 A1).
Regarding Claim 1, Prechtl et al. discloses a semiconductor device, comprising: a Group III-nitride semiconductor structure, the Group III-nitride semiconductor structure comprising a channel layer and a barrier layer on the channel layer (Par.0026-0028; Fig. 3 – channel layer 104 (buffer region 104); barrier layer 106);
PNG
media_image1.png
566
682
media_image1.png
Greyscale
an implanted region extending into the channel layer, the implanted region comprising a distribution of implanted dopants wherein a peak dopant concentration of the distribution of implanted dopants in the implanted region is in the channel layer (Par.0028-0031; Fig. 3 – implanted region 124; this prior art teaches that the implanted region 124 is a degenerately doped region; it further states that the implanted region 124 is doped such that current travels laterally from the channel layer 104 to the contact structure 120 through implanted region portion that is within the channel region 104; if the portion of the implanted region 124 that is within the barrier region 106 is also highly doped (degenerately doped) then current would flow not only laterally but would also flow through the portion of the implanted region 124 that is in the barrier layer 106); and a recess in the implanted region, the recess extending through the barrier layer into the channel layer (Par.0029-0031 & 0043; Figs. 3 & 11A – recess 170); and an ohmic contact within the recess (Par.0005, 0028-0032; Fig. 3 – ohmic contact 122).
Regarding Claim 10, Prechtl et al., as applied to claim 1, discloses the semiconductor device, wherein the implanted dopants comprise silicon (Par. 0029).
Regarding Claim 14, Prechtl et al., as applied to claim 1, discloses the semiconductor device, wherein a peak dopant concentration of the distribution of implanted dopants comprises about 1 x 1018 dopants/cm3 (Par. 0028-0029; Fig. 3 – this prior art teaches that the doped region is a degenerated region which in the case of GaN is known to need a dopant concentration of 1 x 1018 dopants/cm3 or more).
Regarding Claim 15, Prechtl et al., as applied to claim 1, discloses the semiconductor device, wherein the ohmic contact is a source contact or a drain contact (Par. 0049).
Regarding Claim 16, Prechtl et al., as applied to claim 1, discloses the semiconductor device, wherein the channel layer comprises AlxGa1-xN, wherein x is about 0.1 or less (Par. 0026 – channel layer GaN, x=0.0).
Regarding Claim 17, Prechtl et al., as applied to claim 1, discloses the semiconductor device, wherein the Group III-nitride semiconductor structure is on a silicon carbide substrate (Par. 0026).
Regarding Claim 18, Prechtl et al., as applied to claim 1, discloses the semiconductor device, wherein the semiconductor device comprises a high electron mobility transistor (Par. 0002-0004).
Regarding Claim 35, Prechtl et al. discloses a method of forming a semiconductor device, comprising: forming a Group III-nitride semiconductor structure on a substrate, the Group III-nitride
PNG
media_image2.png
554
638
media_image2.png
Greyscale
semiconductor structure comprising a channel layer and a barrier layer on the channel layer (Par.0026-0028; Figs. 3 & 11A-11C – channel layer 104 (buffer region 1044); barrier layer 106); implanting dopants in the Group III-nitride semiconductor structure to form an implanted region in the Group III-nitride semiconductor structure, the implanted region having a distribution of implanted dopants extending into the channel layer wherein a peak dopant concentration of the distribution of implanted dopants in the implanted region is in the channel layer (Par.0028-0031; Figs. 3 & 11A-11C – implanted region 124; this prior art teaches that the implanted region 124 is a degenerately doped region; it further states that the implanted region 124 is doped such that current travels laterally from the channel layer 104 to the contact structure 120 through implanted region portion that is within the channel region 104; if the portion of the implanted region 124 that is within the barrier region 106 is also highly doped (degenerately doped) then current would flow not only laterally but would also flow through the portion of the implanted region 124 that is in the barrier layer 106); forming a recess in the implanted region, the recess extending through the barrier layer into the channel layer (Par.0029-0031 & 0043, Figs. 3 & 11A-11C – recess 170); and forming an ohmic contact in the recess (Par.0005, 0028-0032; Fig. 3 – ohmic contact 122).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-7, 9, 11 & 19-20 are rejected under 35 U.S.C. 103 as obvious over Prechtl et al. (Pub. No.: US 2013/0299842 A1), as applied to claim 1.
Regarding Claim 2, Prechtl et al., as applied to claim 1, does not explicitly disclose the semiconductor device, wherein a contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is about 0.15 ohm-mm or less. However, Prechtl et al. teachesthe semiconductor device, wherein a specific contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is about 0.5E-5 ohm-mm2 or less (Par. 0032). This prior art is silent regarding the length of the contact; therefore, it is difficult to translate the specific contact resistance reported by Prechtl et al. into the contact resistance recited in the instant claim. If one is to assume that the length of the contact of this prior art is similar to the length of the contact given in this application, the contact resistance comes out to be very similar to the contact resistance claimed here. Also, since the method applied by this prior art to reduce the contact resistance is very similar to the method applied by the instant claim, there is no reason to think that these two references would have widely different contact resistances. Even, assuming arguendo that the contact resistance of Prechtl et al. is not quite as low as claimed in the instant claim, the factors that affect the contact resistance is well-known in the art, such as the concentration of the impurity in the implanted region, the depth of the recess, the metals used in the ohmic contact etc., it would have been obvious to one having ordinary skill in the art at the time the invention was filed to tweak the involved parameters to attain the semiconductor device, wherein a contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is about 0.15 ohm-mm or less, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 3, Prechtl et al., as applied to claim 1, does not explicitly disclose the semiconductor device, wherein a contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is about 0.10 ohm-mm or less. However, Prechtl et al. teachesthe semiconductor device, wherein a specific contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is about 0.5E-5 ohm-mm2 or less (Par. 0032). This prior art is silent regarding the length of the contact; therefore, it is difficult to translate the specific contact resistance reported by Prechtl et al. into the contact resistance recited in the instant claim. If one is to assume that the length of the contact of this prior art is similar to the length of the contact given in this application, the contact resistance comes out to be very similar to the contact resistance claimed here. Also, since the method applied by this prior art to reduce the contact resistance is very similar to the method applied by the instant claim, there is no reason to think that these two references would have widely different contact resistances. Even, assuming arguendo that the contact resistance of Prechtl et al. is not quite as low as claimed in the instant claim, the factors that affect the contact resistance is well-known in the art, such as the concentration of the impurity in the implanted region, the depth of the recess, the metals used in the ohmic contact etc., it would have been obvious to one having ordinary skill in the art at the time the invention was filed to tweak the involved parameters to attain the semiconductor device, wherein a contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is about 0.10 ohm-mm or less, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 4, Prechtl et al., as applied to claim 1, does not explicitly disclose the semiconductor device, wherein a contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is in a range of about 0.05 to about 0.15 ohm-mm. However, Prechtl et al. teachesthe semiconductor device, wherein a specific contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is about 0.5E-5 ohm-mm2 or less (Par. 0032). This prior art is silent regarding the length of the contact; therefore, it is difficult to translate the specific contact resistance reported by Prechtl et al. into the contact resistance recited in the instant claim. If one is to assume that the length of the contact of this prior art is similar to the length of the contact given in this application, the contact resistance comes out to be very similar to the contact resistance claimed here. Also, since the method applied by this prior art to reduce the contact resistance is very similar to the method applied by the instant claim, there is no reason to think that these two references would have widely different contact resistances. Even, assuming arguendo that the contact resistance of Prechtl et al. is not quite as low as claimed in the instant claim, the factors that affect the contact resistance is well-known in the art, such as the concentration of the impurity in the implanted region, the depth of the recess, the metals used in the ohmic contact etc., it would have been obvious to one having ordinary skill in the art at the time the invention was filed to tweak the involved parameters to attain the semiconductor device, wherein a contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is in a range of about 0.05 to about 0.15 ohm-mm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 5, Prechtl et al., as applied to claim 1, does not explicitly disclose the semiconductor device, wherein the barrier layer comprises AlyGa1-yN, wherein y is in a range of about 0.25 to about 0.4, wherein the barrier layer has a thickness of less than about 130 Angstroms. However, the Examiner takes OFFICIAL NOTICE that the semiconductor device, wherein the barrier layer comprises AlyGa1-yN, wherein y is in a range of about 0.25 to about 0.4, wherein the barrier layer has a thickness of less than about 130 Angstroms is well known in the art (creating enough band discontinuity in one hand and still keeping the lattice mismatch in check on the other hand; ; see for example, Higashiwaki et al. “30-nm-Gate AlGaN/GaN Heterostructure Field-Effect Transistors with a Current-Gain Cutoff Frequency of 181GHz” Japanese Journal of Applied Physics Vol. 45, No. 42, 2006, pp. L1111–L1113). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, wherein the barrier layer of Prechtl comprises AlyGa1-yN, wherein y is in a range of about 0.25 to about 0.4, wherein the barrier layer has a thickness of less than about 130 Angstroms in order to fabricate a high-performance HEMT device .
Regarding Claim 6, modified Prechtl et al., as applied to claim 5, discloses the semiconductor device, wherein y is in a range of 0.35 to about 0.4 (please see the rejection of claim 5 above).
Regarding Claim 7, modified Prechtl et al., as applied to claim 5, discloses the semiconductor device, wherein the barrier layer has a thickness in a range of about 70 Angstroms to about 100 Angstroms (please see the rejection of claim 5 above).
Regarding Claim 9, Prechtl et al., as applied to claim 1, discloses the semiconductor device, wherein the semiconductor device comprises a gate contact (Fig. 13). Prechtl et al. does not explicitly disclose the semiconductor device, wherein the semiconductor device comprises a gate contact and the gate contact has a gate length in a range of about 60 nm to about 100 nm. However, the Examiner takes OFFICIAL NOTICE that the semiconductor device, wherein the gate contact has a gate length in a range of about 60 nm to about 100 nm is well known in the art (depends on performance goals, manufacturing capabilities and physical limits; shorter gate generally improves speed, decreases power consumption, and improves packing density). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, wherein the gate contact of Prechtl has a gate length in a range of about 60 nm to about 100 nm in order to fabricate a high-performance HEMT device.
Regarding Claim 11, Prechtl et al., as applied to claim 1, discloses the semiconductor device, wherein the implanted dopants comprise silicon (Par. 0029) Prechtl et al. does not explicitly disclose the semiconductor device, wherein the implanted dopants comprise germanium. However, the Examiner takes OFFICIAL NOTICE that the semiconductor device, wherein the implanted dopants comprise germanium is well-known in the art (use of both silicon and germanium are known in the art). Prechtl et al. discloses the claimed invention except for the semiconductor device, wherein the implanted dopants comprise germanium. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to adapt the semiconductor device, wherein the implanted dopants comprise germanium, since it has been held that the simple substitution of one known element for another to obtain predictable results is obvious
Regarding Claim 12, Prechtl et al., as applied to claim 1, does not explicitly disclose the semiconductor device, wherein the implanted region extends to a depth of about 200 Angstroms to about 300 Angstroms beneath a surface of the Group III- nitride semiconductor structure. However, Prechtl et al. teachesthe semiconductor device, wherein the implanted region extends past the barrier layer into the channel layer. Unfortunately, this prior art does not explicitly teach the thicknesses of the barrier layer and the channel layer. However, the thicknesses adapted by the instant application for the various layers are widely used in the art. So, the thicknesses of the barrier layer and channel layer adapted by this prior art could be very similar to the thicknesses used by the instant application. Now, how deep into the channel layer the implanted region should extend into could be very easily found out by a person of ordinary skill in the art by routine experimentation. Prechtl et al. discloses the claimed invention except for the semiconductor device, wherein the implanted region extends to a depth of about 200 Angstroms to about 300 Angstroms beneath a surface of the Group III- nitride semiconductor structure. It would have been obvious to one having ordinary skill in the art at the time the invention was filed to adapt the semiconductor device, wherein the implanted region extends to a depth of about 200 Angstroms to about 300 Angstroms beneath a surface of the Group III- nitride semiconductor structure, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding Claim 19, Prechtl et al., as applied to claim 1, does not explicitly disclose the semiconductor device, wherein the semiconductor device is associated with an operating frequency of greater than about 8 GHz. However, the Examiner takes OFFICIAL NOTICE that the semiconductor device, wherein the semiconductor device is associated with an operating frequency of greater than about 8 GHz is well-known in the art (for example, please see Inoue et al. (Pub. No.: US 2009/0045438 A1). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, wherein the semiconductor device of Prechtl is associated with an operating frequency of greater than about 8 GHz in order to be able to use it in high frequency operation.
Regarding Claim 20, Prechtl et al. discloses a transistor device, comprising: a Group III-nitride semiconductor structure, the Group III-nitride semiconductor structure comprising a channel layer and a barrier layer on the channel layer (Par.0032-0036; Figs. 8A-8F – channel layer 3 (GaN channel layer); barrier layer 5 (InAlN electron supply layer));
PNG
media_image1.png
566
682
media_image1.png
Greyscale
a gate contact on the barrier layer, (Par.0037-0040; Figs. 8A-8F – gate contact 9); an implanted region in the Group III-nitride semiconductor structure, the implanted region comprising a distribution of implanted dopants (Par.0038-0040; Figs. 8A-8F – implanted region 10); an ohmic contact on the implanted region (Par.0084-0086; Figs. 8A-8F – ohmic contact 7/8). Prechtl et al. does not explicitly disclose the gate contact having a gate length of less than about 100 nm; and wherein a contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is about 0.15 ohm-mm or less. However, the Examiner takes OFFICIAL NOTICE that the semiconductor device, the gate contact having a gate length of less than about 100 nm is well known in the art (depends on performance goals, manufacturing capabilities and physical limits; shorter gate generally improves speed, decreases power consumption, and improves packing density; see for example, 1) Higashiwaki et al. “30-nm-Gate AlGaN/GaN Heterostructure Field-Effect Transistors with a Current-Gain Cutoff Frequency of 181GHz” Japanese Journal of Applied Physics Vol. 45, No. 42, 2006, pp. L1111–L1113). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use the teachings well-known in the industry to adapt the semiconductor device, wherein the gate contact of Prechtl having a gate length of less than about 100 nm in order to fabricate a high-performance HEMT device. Also, although Prechtl et al. does not explicitly disclose wherein a contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is about 0.15 ohm-mm or less, it teaches the semiconductor device, wherein a specific contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is about 0.5E-5 ohm-mm2 or less (Par. 0032). This prior art is silent regarding the length of the contact; so, it is hard to translate the specific contact resistance of Prechtl et al. to the contact resistance given in the instant claim. If one is to assume that the length of the contact of this prior art is similar to the length of the contact given in this application, the contact resistance comes out to be very similar to the contact resistance claimed here. Also, since the method applied by this prior art to reduce the contact resistance is very similar to the method applied by the instant claim, there is no reason to think that these two references would have widely different contact resistances. Even, assuming arguendo that the contact resistance of Prechtl et al. is not quite as low as claimed in the instant claim, the factors that affect the contact resistance is well-known in the art, such as the concentration of the impurity in the implanted region, the depth of the recess, the metals used in the ohmic contact etc., it would have been obvious to one having ordinary skill in the art at the time the invention was filed to tweak the involved parameters to attain the semiconductor device, wherein a contact resistance of the ohmic contact with the Group III-nitride semiconductor structure is about 0.15 ohm-mm or less, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Response to Arguments
Applicants’ arguments filed on 12/26/2025 have been fully considered but they are not found to be persuasive.
The Applicant argues regarding independent claims 1 & 35 “The pending application discloses a variety of methods for reducing the contact resistance, which can be utilized alone or in combination. One method disclosed is the precise control over the distribution of implanted dopants, so that the peak dopant concentration is strategically located within the channel layer. In this way, the pending application can provide a "low resistive path" between the ohmic contact and the channel layer. The Office Action (page 4) argues that paragraphs [0028]-[0029] of Prechtl discloses the subject matter of previously pending claim 13 (incorporated into independent claim 1 herein). However, these paragraphs only describe forming a generic "doped region" and do not disclose the specific depth profile or peak concentration location. For at least these reasons, independent claim 1 patentably defines over the cited art and is allowable. Independent claim 35 also recites the same or similar subject matter as independent claim 1, and patentably defines over the cited art for at least the same reasons. Therefore, Applicant submits that independent claims 1 and 35 patentably defines over the materials cited in the Office Action for at least the same reasons, and requests that the rejections under § 102 & 103 be withdrawn” (emphasis added). The Examiner’s Rebuttal – The Examiner respectfully disagrees. Although Prechtl does not explicitly disclose “a peak dopant concentration of the distribution of implanted dopants in the implanted region is in the channel layer”, the limitation has been implicitly taught. This prior art teaches (Par.0028-0029; Fig. 3) that the implanted region 124 is a degenerately doped region. It further states that the implanted region 124 is doped such that current travels laterally from the channel layer 104 to the contact structure 120 through implanted region portion that is within the channel region 104. If the portion of the implanted region 124 that is within the barrier region 106 is also highly doped (degenerately doped) then current would flow not only laterally but would also flow vertically through the portion of the implanted region 124 that is in the barrier layer 106.
The Applicant further argues regarding independent claim 20 “The Office Action (page 15) takes official notice that gate lengths <100 nm are "well known in the art." Applicant respectfully disagrees. First, the Examiner's reliance on official notice is unsupported by documentary evidence showing that sub-100 nm gate lengths are well known in the art. "The Examiner must provide specific factual findings predicated on sound technical and scientific reasoning to support the conclusion of common knowledge." See Soli, 317 E 2d at 946, 37 USPQ at 801; Chevenard, 139 RE2d at 713, 60 USPQ at 241”.
The Examiner’s Rebuttal – The Examiner respectfully disagrees. Although the Examiner took official notice that the gate lengths <100 nm are well-known in the art, he backed it up with documentary evidence. For example, the office cited the prior art of “Higashiwaki et al. “30-nm-Gate AlGaN/GaN Heterostructure Field-Effect Transistors with a Current-Gain Cutoff Frequency of 181GHz” Japanese Journal of Applied Physics Vol. 45, No. 42, 2006, pp. L1111–L1113)” as a proof of its statement which shows a gate length of as low as 30 nm for a nitride-based transistor.
The Applicant also argues regarding dependent claims 5 and 7 “The Office Action (pages 10 & 11) takes official notice that the barrier layer composition and thickness is "well known in the art." Applicant respectfully disagrees. First, the Examiner's reliance on official notice is unsupported by documentary evidence showing that the barrier layer composition and thickness is well known in the art. "The Examiner must provide specific factual findings predicated on sound technical and scientific reasoning to support the conclusion of common knowledge." See Soli, 317 E2d at 946, 37 USPQ at 801; Chevenard, 139 E2d at 713, 60 USPQ at 241”.
The Examiner’s Rebuttal – The Examiner respectfully disagrees. Although the Examiner took official notice that “the barrier layer comprising AlyGa1-yN, wherein y is in a range of about 0.25 to about 0.4, wherein the barrier layer has a thickness of less than about 130 Angstroms”. is well known in the art, he backed it up with documentary evidence. For example, the office cited the prior art of “Higashiwaki et al. “30-nm-Gate AlGaN/GaN Heterostructure Field-Effect Transistors with a Current-Gain Cutoff Frequency of 181GHz” Japanese Journal of Applied Physics Vol. 45, No. 42, 2006, pp. L1111–L1113)” as a proof of its statement which shows a barrier composition wherein y=0.4 and thickness is 80 Angstroms.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
02/17/2026
/SYED I GHEYAS/Primary Examiner, Art Unit 2893