DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 12/15/2025.
Claims 1-13, and 21-27 are pending in this application.
Applicant made a provisional election to prosecute the invention of Group I, claims 1-13, and new claims 21-27, is acknowledged.
Claims 14-20 have been cancelled.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 06/13/2023. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The specification is objected to for the following reason:
The drawings show Fig. 4A, Fig. 4B, and the brief description of the drawings at paragraph [0003] combinedly recites Figures 1 through 14.
MPEP 608.01(f) requires a brief description of Figure 4A, and Figure 4B (for example, Figs. 1 – 3, Figs. 4A – 4B, Figs. 5-14) be provided.
Appropriate correction is required.
4. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1, 8, 10, 13, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (US 2021/0066452)
Regarding claim 1, Liaw discloses a semiconductor device, comprising:
semiconductor nanosheets 1001 (see fig. 11) vertically stacked upon one another, disposed above a semiconductor substrate 101, and serving as channel regions, wherein a topmost semiconductor nanosheet 1001 (having thickness Th6) most distanced from the semiconductor substrate 101 is thinner than an underlying semiconductor nanosheet 1001 (having thickness Th4 or Th2; Para. 0020: Th2>Th4>Th6) between the topmost semiconductor nanosheet 1001 and the semiconductor substrate 101;
a gate structure (fig. 11, para. 0082) surrounding each of the semiconductor nanosheets 1001; and
source/drain (S/D) regions 603 disposed over the semiconductor substrate 101 and laterally abutting the semiconductor nanosheets 1001.
Regarding claim 8, Liaw discloses the semiconductor device of claim 1, further comprising:
a bottom isolation structure 135 (see fig. 10B, fig. 12C) disposed on the semiconductor substrate 101 to (partially) isolate the S/D regions 603 from the semiconductor substrate 101.
Regarding claim 10, Liaw discloses a semiconductor device, comprising:
a semiconductor substrate 101 (see fig. 11); and
a device layer 203 disposed on the semiconductor substrate 101, the device layer comprising:
channel regions 1001 vertically stacked upon one another, wherein a thickness of a topmost channel region (having thickness Th6) is less than that of a bottommost channel region (having thickness Th4 or Th2; Para. 0020: Th2>Th4>Th6);
a gate structure (fig. 11, para. 0082) surrounding each of the channel regions 1001; and
S/D regions 603 laterally coupled to the channel regions 1001 and laterally separated from the gate structure.
Regarding claim 13, Liaw discloses the semiconductor device of claim 10, further comprising:
inner spacers 503 (fig. 7B, fig. 11) laterally interposed between the gate structure and the S/D regions 603; and
a bottom isolation structure 135 (fig. 10B, fig. 12B) disposed on the semiconductor substrate 101 and laterally adjoining a bottommost one of the inner spacers.
Regarding claim 21, Liaw discloses a semiconductor device, comprising:
a first channel layer 1001 (having thickness Th2; see fig. 11) and a second channel layer 1001 (having thickness Th4 or Th6) disposed over the first channel layer, wherein a first dimension of the first channel layer 1001 and a second dimension of the second channel layer 1001 that are measured along a first direction (vertical direction) are different (Para. 0020: Th2>Th4>Th6);
a S/D region 603 adjoining the first channel layer 1001 and the second channel layer 1001 in a second direction (lateral direction) that is different from the first direction; and
a gate structure (fig. 11, para. 0082) spaced apart from the S/D region 603 in the second direction, the gate structure comprising a first gate segment adjoining the first channel layer 1001 in the first direction and a second gate segment adjoining the second channel layer 1001 in the first direction.
Claim Rejections - 35 U.S.C. § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 3, 4, 7, 22, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2021/0066452) in view of Jeong et al. (US 2022/0238723).
Regarding claim 3, Liaw discloses the semiconductor device of claim 1, comprising all claimed limitations, as discussed above, except for wherein a top segment of the gate structure directly under the topmost semiconductor nanosheet comprises a gate length less than a gate length of a bottom segment of the gate structure directly under a bottommost semiconductor nanosheet.
Jeong discloses a semiconductor device, shown in fig. 2A, wherein a top segment of a gate structure 180c directly under a topmost semiconductor nanosheet 120c-1 comprises a gate length less than a gate length of a bottom segment 180a of the gate structure directly under a bottommost semiconductor nanosheet 120a-1.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Liaw to have a gate structure as that taught by Jeong to provide a nanosheet transistor in which short channel effects are reduced or alleviated. See para. 0004 of Jeong.
Regarding claim 4, Liaw discloses the semiconductor device of claim 1, comprising all claimed limitations, as discussed above, including wherein top portions of adjacent two of the S/D regions 603 are disposed at opposing sides of the topmost semiconductor nanosheet 1001, bottom portions of the adjacent two of the S/D regions 603 are disposed at opposing sides of a bottommost semiconductor nanosheet.
Liaw fails to discloses wherein a lateral distance between the top portions of the adjacent two of the S/D regions is less than a lateral distance between the bottom portions of the adjacent two of the S/D regions.
Jeong discloses a semiconductor device, as shown in fig. 2A, wherein top portions of adjacent two of the S/D regions SD1-1/SD2-2 are disposed at opposing sides of the topmost semiconductor nanosheet 120c-1,
bottom portions of the adjacent two of the S/D regions SD1-1/SD2-2 are disposed at opposing sides of a bottommost semiconductor nanosheet 120a-1, and
a lateral distance between the top portions of the adjacent two of the S/D regions SD1-1/SD2-2 is less than a lateral distance between the bottom portions of the adjacent two of the S/D regions.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Liaw to have a source/drain S/D regions having lateral distances as that/those taught by Jeong to provide a nanosheet transistor in which short channel effects are reduced or alleviated. See para. 0004 of Jeong.
Regarding claim 7, Liaw discloses the semiconductor device of claim 1, comprising all claimed limitations, as discussed above, except for wherein the topmost semiconductor nanosheet comprises a first thickness in a central region and a second thickness in a peripheral region, and the first thickness is less than the second thickness.
Jeong discloses a semiconductor device wherein the topmost semiconductor nanosheet 120c-1 comprises a first thickness in a central region and a second thickness in a peripheral region (proximate to inner spacers 161c, 162c), and the first thickness is less than the second thickness.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Liaw to have nanosheet having thicknesses as that/those taught by Jeong in order to provide a nanosheet transistor in which short channel effects are reduced or alleviated. See para. 0004 of Jeong.
Regarding claim 22, Liaw discloses the semiconductor device of claim 21, comprising all claimed limitations, as discussed above, except for wherein a third dimension of the first gate segment and a fourth dimension of the second gate segment that are measured along the second direction are different.
Jeong discloses a semiconductor device comprising a gate structure wherein a third dimension of a first gate segment 180a of the gate structure and a fourth dimension of a second gate segment 180b or 180c that are measured along the second direction are different. See figs. 1F, 2A.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Liaw to have a gate structure as that taught by Jeong to provide a nanosheet transistor in which short channel effects are reduced or alleviated. See para. 0004 of Jeong.
Regarding claim 23, Liaw/Jeong discloses the semiconductor device of claim 22, wherein the first dimension of the first channel layer 120a/120b is greater than the second dimension of the second channel layer 120c, and the third dimension of the first gate segment 180a/180b is greater than the fourth dimension of the second gate segment 180c. See fig. 2A of Jeong.
9. Claims 5, 6, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 2021/0066452) in view of Xie et al. (US 2023/0093025)
Regarding claim 5, Liaw discloses the semiconductor device of claim 1, comprising all claimed limitations, as discussed above, except for wherein a top surface of the topmost semiconductor nanosheet comprises a substantially V-shaped cross-sectional profile or a substantially U-shaped cross-sectional profile.
Xie discloses a semiconductor device wherein a top surface of a topmost semiconductor nanosheet 18NS comprises a substantially V-shaped cross-sectional profile or a substantially U-shaped cross-sectional profile. See fig. 15.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Liaw to have semiconductor nanosheet(s) having cross-sectional profile, as that taught by Xie, in order to increase the gate and/or channel length, thereby to mitigate short-channel effects such as leakage current, to enhance gate control, etc. See paras. 0001-0003 of Xie.
Regarding claim 6, Liaw diclsoes the semiconductor device of claim 1, comprising all claimed limitations, except for wherein a top surface of the topmost semiconductor nanosheet comprises an asymmetric profile in a cross-sectional view.
Xie discloses a semiconductor device wherein a top surface of a topmost semiconductor nanosheet 18NS comprises an asymmetric profile in a cross-sectional view. See fig. 15.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Liaw to have semiconductor nanosheet(s) having cross-sectional profile, as that taught by Xie, in order to increase the gate and/or channel length, thereby to mitigate short-channel effects such as leakage current, to enhance gate control, etc. See paras. 0001-0003 of Xie.
Regarding claim 24, Liaw discloses the semiconductor device of claim 21, comprising all claimed limitations, as discussed above, except for wherein the second channel layer comprises a first side facing the first channel layer and a second side opposite to the first side, and the second side comprises a concave portion recessed toward the first channel layer.
Xie discloses a semiconductor device wherein a second channel layer (topmost layer) 18NS comprises a first side facing the first channel layer (lower layer(s)) 18NS and a second side opposite to the first side, and the second side comprises a concave portion recessed toward the first channel layer. See fig. 15.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Liaw to have channel layer(s) as that/those taught by Xie, in order to increase the channel length, thereby to mitigate short-channel effects such as leakage current, to enhance gate control, etc. See paras. 0001-0003 of Xie.
Allowable Subject Matter
10. Claims 2, 9, 11, 12, and 25-27 allowable.
Claims 2, 9, 11, 12, and 25-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, since the prior art of record and considered pertinent to the applicant’s disclosure does not teach or suggest the claimed semiconductor device (in addition to the other limitations in the claim) comprising:
Claim 2:
wherein each of the S/D regions comprises:
a first region laterally adjacent to the topmost semiconductor nanosheet; and
a second region below the first region, wherein a doping concentration in the first region is higher than a doping concentration in the second region.
Claim 9:
an undoped epitaxial structure directly disposed on the semiconductor substrate; and
a bottom isolation structure overlying the undoped epitaxial structure, wherein the S/D regions are directly on the bottom isolation structure.
Claim 11:
wherein the semiconductor substrate comprising a p-type region and an n-type region, and the thickness of the topmost channel region corresponding to the p-type region is different from the thickness of the topmost channel region corresponding to the n-type region.
Claim 12:
wherein each of the S/D regions comprises:
a first region laterally adjacent to the topmost channel regions; and
a second region other than the first region, wherein a doping concentration in the first region is higher than a doping concentration in the second region.
Claim 25:
wherein the second channel layer comprises a sidewall interfaced with the S/D region, and a dimension of the sidewall measured along the first direction is greater than a minimum distance between the first side and the second side measured along the first direction.
Claims 26-27:
wherein the first gate segment comprises a first side adjoining the first channel layer and a second side opposite to the first side, a fifth dimension of the first side and a sixth dimension of the second side that are measured along the second direction are different.
Conclusion
11. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 February 7, 2026