Attorney Docket Number: 106222.022140
Filing Date: 06/14/2023
Claimed Priority Date: none
Inventors: Mu et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 11/18/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 11/18/2025 in reply to the previous Office action mailed on 08/18/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-25 and 39-40.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because the following reference characters have been used to designate different parts:
“420” has been used to designate both a semiconductor device and a metallization layer in figure 4
“200” has been used to designate both an exemplary process flow in figure 5 and an integrated passive device in figures 1-2
“212” has been used to designate both a portion of a first metal layer in figure 7 and a second metal layer deposited on a first metal layer in figure 2
“400” has been used to designate both an exemplary process flow in figure 13 and a semiconductor device in figures 1 and 3
“412” has been used to designate both a portion of a first metal layer in figure 15 and a second metal layer deposited on a first metal layer in figure 3
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections
Initially, and with respect to claim 12, note that a “product by process” claim is directed to the product per se, no matter how actually made. See In re Thorpe, 227 USPQ 964 (CAFC, 1985) and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe,
even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935).
Note that the applicants have the burden of proof in such cases, as the above case law makes clear.
As to the grounds of rejection under section 103, see MPEP § 2113, which discusses the handling of “product by process” claims and recommends the alternative (§ 102/ § 103) grounds of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 11, 13-18, and 39-40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chinnusamy (US 9,875,988).
Regarding claim 1, Chinnusamy (see, e.g., figs. 6a-6b) shows all aspects of the instant invention, including a packaged device 154 comprising:
at least one integrated passive device 104 (see, e.g., col.4/ll.36-37) comprising at least one bond pad 112;
at least one semiconductor device 140 (see, e.g., col.6/ll.67 through col.7/ll.2) comprising at least one bond pad 144; and
at least one connection structure 122 arranged on the at least one integrated passive device
wherein:
the at least one connection structure 122 comprises a solder portion 120 (see, e.g., col.5/ll.31-32) configured to form a solder connection to the at least one bond pad 144 of the at least one semiconductor device 140
Regarding claim 39, Chinnusamy (see, e.g., figs. 1b-1f and 5a-5f) shows a process of implementing a packaged device comprising:
configuring at least one integrated passive device 104 with at least one bond pad 112;
configuring at least one semiconductor device 140 with at least one bond pad 144;
arranging at least one connection structure 118 on the at least one integrated passive device;
arranging a solder portion 120 on the at least one connection structure; and
connecting the at least one connection structure to the at least one bond pad 144 of the at least one semiconductor device 140 with the solder portion
Regarding claim 2, Chinnusamy (see, e.g., figs. 6a-6b) shows that the at least one integrated passive device 104 comprises one or more under bump metals (see, e.g., par.0036/ll.6-8), that the at least one connection structure 122 is on the one or more under bump metals (see, e.g., par.0036/ll.6-8), and that the solder portion 120 is arranged on an end of the at least one connection structure 122 closer to the at least one bond pad 144 of the semiconductor device 140 than the at least one bond pad 112 of the at least one integrated passive device 104.
Regarding claim 3, Chinnusamy (see, e.g., figs. 6a-6b) shows wherein that:
the at least one integrated passive device 104 comprises one or more under bump metals (see, e.g., par.0036/ll.6-8);
the at least one connection structure 122 is on the one or more under bump metals (see, e.g., par.0036/ll.6-8)
solder portion 120 is arranged on an end of the at least one connection structure 122 closer to the at least one semiconductor device 140 than the at least one bond pad 112 of the at least one integrated passive device 104; and
the at least one connection structure comprises a pillar portion 118 that comprises an electroplated copper structure and/or electroless plated copper structure (see, e.g., col.5/ll.17-25)
Regarding claim 4, Chinnusamy (see, e.g., figs. 6a-6b) shows that the solder portion 120 is arranged on an end of the at least one connection structure 122 distal from the at least one integrated passive device 104, and wherein the solder portion 120 is arranged on an end of the at least one connection structure 122 proximal to the at least one semiconductor device 140.
Regarding claim 5, Chinnusamy (see, e.g., figs. 6a-6b) shows that the solder portion 120 is arranged on an end of the at least one connection structure 122 distal from the at least one bond pad 112 of the at least one integrated passive device 104, and that the solder portion 120 is arranged on an end of the at least one connection structure 122 proximal to the at least one bond pad 144 of the at least one semiconductor device 140.
Regarding claim 6, Chinnusamy (see, e.g., figs. 6a-6b) shows that the solder portion 120 is arranged on an end of the least one connection structure 122 opposing the at least one semiconductor device 140.
Regarding claim 7, Chinnusamy (see, e.g., figs. 6a-6b) shows that the solder portion 120 is arranged on an end of the at least one connection structure 122 opposing the at least one bond pad 144 of the at least one semiconductor device 140.
Regarding claim 8, Chinnusamy (see, e.g., figs. 6a-6b and col.7/ll.34-36) shows that the solder portion 120 is arranged on an end of the at least one connection structure 122, and that solder portion comprises reflowed solder.
Regarding claim 9, Chinnusamy (see, e.g., figs. 1e-1f) shows that the at least one connection structure 122 is attached to the at least one integrated passive device 104 while the at least one integrated passive device is arranged in a wafer 100 together with a plurality of the at least one integrated passive device prior to singulation of the at least one integrated passive device from the wafer.
Regarding claim 11, Chinnusamy (see, e.g., figs. 1e-1f) shows that the at least one connection structure 122 is arranged on the at least one bond pad 112 of the at least one integrated passive device 104 that is arranged in a wafer.
Regarding claim 13, Chinnusamy (see, e.g., figs. 5c-5d) shows that the at least one connection structure 122 is arranged on the at least one bond pad 112 of the integrated passive device 104 prior to being connected to the at least one bond pad 144 of the at least one semiconductor device 140.
Regarding claim 14, Chinnusamy (see, e.g., figs. 6a-6b) shows that the at least one connection structure 122 is configured to extend vertically below the at least one integrated passive device 104 and connect to the at least one bond pad 144 of the at least one semiconductor device 140.
Regarding claim 15, Chinnusamy (see, e.g., figs. 2 and 5b-5d) shows that:
at least one bond pad 112 of the at least one integrated passive device 104 is arranged on a first surface of the at least one integrated passive device 104; and
the at least one integrated passive device is configured as a flip chip such that the first surface is located adjacent the at least one semiconductor device 140
Regarding claim 16, Chinnusamy (see, e.g., figs. 6a-6b) shows that the at least one connection structure 122 comprises a pillar portion 118 and a solder portion 120.
Regarding claim 17, Chinnusamy (see, e.g., figs. 6a-6b and col.5/ll.17-25) shows the pillar portion 118 that comprises an electroplated metallic structure and/or an electroless plated metallic structure.
Regarding claim 18, Chinnusamy (see, e.g., figs. 6a-6b and col.5/ll.17-25) shows the pillar portion 118 that comprises an electroplated copper structure and/or an electroless plated copper structure.
Regarding claim 40, Chinnusamy (see, e.g., figs. 1d and 5c-5f) shows arranging the solder portion 120 on an end of the at least one connection structure 118 closer to the at least one bond pad 144 of the at least one semiconductor device 140 than the at least one bond pad 112 of the at least one integrated passive device 104, wherein the solder portion 120 is arranged on an end of the at least one connection structure 122 distal from the at least one integrated passive device 104, and wherein the solder portion 120 is arranged on an end of the at least one connection structure proximal to the at least one semiconductor device 140.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by, or in the alternative, under 35 U.S.C. 103 as obvious over Chinnusamy.
Regarding claim 12, Chinnusamy (see, e.g., figs. 5e-5f and 6a-6b) shows that the at least one semiconductor device 140 is connected to the at least one connection structure 122 of the integrated passive device 104.
Accordingly, it is noted that that Chinnusamy shows all structural aspects of the packaged device according to the claimed invention (see also paragraph 10 above), and that the method steps of having the above arrangement during wafer processing of the at least one integrated passive device are intermediate steps that do not affect the structure of the final device.
Claims 1 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2020/0135677) in view of Meyer (US 2017/0309582) and Noori (US 2021/0313284).
Regarding claim 1 (as necessitated by Applicant’s amendments to dependent claims 10 and 11, such as by removing “product by process” limitations from claim 10 such that the limitation “while the at least one integrated passive device is arranged in a wafer together with a plurality of the at least one integrated passive device” is amended to be a new structural, rather than process, limitation [see “Applicant Arguments/Remarks Made in an Amendment”, page 10, lines 22-23 and 26-27], thereby changing the scope), Chang (see, e.g., fig. 23) shows most aspects of the instant invention, including a packaged device comprising:
at least one component 71 comprising a passive device (see, e.g., pars.0040/ll.3-9 and 0041/ll.1-3) comprising at least one bond pad 96 (see, e.g., par.0043/ll.17);
at least one semiconductor device 22 comprising at least one bond pad 54B; and
at least one connection structure 106/112 arranged on the at least one die/packaged component 71 comprising a passive device
wherein:
the at least one connection structure 106/112 comprises a solder portion 112 configured to form a solder connection to the at least one bond pad 54B of the at least one semiconductor device 2222
Chang shows most aspects of the instant invention. Chang further teaches that Chang’s packaged device includes at least one component 71 comprising a passive device, and that device dies and logic dies are suitable for use as Chang’s component 71 (see, e.g., pars.0040/ll.3-9 and 0041/ll.1-7). Chang, however, fails to explicitly specify that Chang’s component is an integrated passive device. Meyer, in the same field of endeavor, teaches integrated passive devices to function equivalently to various other device dies, including logic dies, in packaged devices (see, e.g., Meyer: par.0016/ll.1-8). Furthermore, Noori, in the same field of endeavor, teaches that a variety of functional blocks can be realized through the use of integrated passive devices, specifically (see, e.g., Noori: par.0009/ll.1-4).
Meyer is evidence showing that one of ordinary skill in the art would appreciate that having an integrated passive device would be equivalent to having a logic or other device in Chang’s packaged device, and that such differences would result in no unexpected changes in the performance of the packaged device of Chang. That is, the device components of both Meyer and Chang would yield the predictable result of providing a suitable electronic component capable of hosting applicable circuitry and communicating with other electronic components.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have as Chang’s component be either an integrated passive device, as taught by Meyer, or another type of device, as taught by Chang, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable electronic component capable of hosting applicable circuitry and communicating with other electronic components. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Moreover, Noori is evidence that it would have been obvious at the time of filing the invention that one of ordinary skill in the art would find particular incentive to have Chang’s components 71 be integrated passive devices, so as to realize a variety of functional blocks in Chang’s device, as taught by Noori, thereby expanding the applications of Chang’s device.
Regarding claim 10’s amendment, Chang (see, e.g., fig. 21) shows that the at least one semiconductor device 22 is arranged on the at least one connection structure 106/112 of the at least one integrated passive device 71 (see the comments stated above in paragraphs 33-37 regarding the integrated passive device, which are considered to be repeated here) while the at least one integrated passive device is arranged in a wafer 70 together with a plurality of the at least one integrated passive device.
Regarding claim 11’s amendment, Chang (see, e.g., fig. 21) shows that the at least one connection structure 106/112 is arranged on the at least on the at least one bond pad 96 of the at least one integrated passive device 71 (see the comments stated above in paragraphs 33-37 regarding the integrated passive device, which are considered to be repeated here) that is arranged in a wafer 70.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chinnusamy in view of Yu (US 2013/0277830).
Regarding claim 19, Chinnusamy teaches most aspects of the instant invention (see paragraphs 10 and 24 above). Chinnusamy (see, e.g., col.5/ll.30-31) further shows that the conductive solder portion 120 comprises printed solder. Additionally, Chinnusamy (see, e.g., col.4/ll.7-8 and col.5/ll.49-50) further teaches Chinnusamy’s electrical connections may use conductive paste. Therefore, Chinnusamy shows that the solder portion comprises a printed solder paste.
Furthermore, Yu, in a similar device to Chinnusamy, teaches solder and solder paste to be equivalent for their use in a solder portion connecting a copper pillar 122 to a bond pad 116 in a connection structure 122/124 (see, e.g., Yu: fig. 1 and par.0021/ll.5-7).
Therefore, it would have been further obvious at the time of filing the invention to one of ordinary skill in the art to use either solder or solder paste in Chinnusamy’s solder portion because these were recognized in the semiconductor art as equivalents for their use as solder portion materials, and selecting among known equivalents would be within the level of ordinary skill in the art. International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 20, Chinnusamy teaches most aspects of the instant invention (see paragraphs 10 and 24 above). Chinnusamy (see, e.g., figs. 6a-6b, col.5/ll.17-25, and col.5/ll.30-31) further shows that:
the pillar portion 118 that comprises an electroplated copper structure and/or an electroless plated copper structure; and
the conductive solder portion 120 comprises printed solder
Additionally, Chinnusamy (see, e.g., col.4/ll.7-8 and col.5/ll.49-50) further teaches Chinnusamy’s electrical connections may use conductive paste. Therefore, Chinnusamy shows that the solder portion comprises a printed solder paste.
Furthermore, Yu, in a similar device to Chinnusamy, teaches solder and solder paste to be equivalent for their use in a solder portion connecting a copper pillar 122 to a bond pad 116 in a connection structure 122/124 (see, e.g., Yu: fig. 1 and par.0021/ll.5-7).
Therefore, it would have been further obvious at the time of filing the invention to one of ordinary skill in the art to use either solder or solder paste in Chinnusamy’s solder portion because these were recognized in the semiconductor art as equivalents for their use as solder portion materials, and selecting among known equivalents would be within the level of ordinary skill in the art. International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chinnusamy in view of Lo (US 2011/0084381).
Regarding claim 21, Chinnusamy teaches most aspects of the instant invention (see paragraphs 10 and 24 above). Furthermore, Chinnusamy (see, e.g., figs. 6a-6b and col.5/ll.17-25) shows that Chinnusamy’s pillar portion 118 comprises an electroplated copper structure and/or an electroless plated copper structure. However, Chinnusamy fails to specify that the pillar portion further comprises a nickel (Ni) barrier layer portion arranged between Chinnusamy’s solder 120 and pillar portion.
Lo, in the same field of endeavor and in a similar device to Chinnusamy, shows having a Ni barrier layer portion 31 between a solder portion 27 and copper pillar portion 26 of a connection structure 28 (see, e.g., Lo: fig. 17). Lo teaches that having a Ni barrier portion between the solder portion and the copper pillar portion of a connection structure prevents solder from penetrating the copper pillar portion and subsequently improves the reliability of the connection structure (see, e.g., Lo: par.0025/ll.10-16).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a Ni barrier layer portion between Chinnusamy’s solder portion and pillar portion, as taught by Lo, so as to prevent solder from penetrating Chinnusamy’s copper pillar to subsequently improve the reliability of Chinnusamy’s connection structure.
Regarding claim 22, Chinnusamy teaches most aspects of the instant invention (see paragraphs 10 and 24 above). Chinnusamy, however, fails to specify that the pillar portion further comprises a layer portion arranged between Chinnusamy’s solder 120 and pillar portion.
Lo, in the same field of endeavor and in a similar device to Chinnusamy, shows having a layer portion 31 between a solder portion 27 and copper pillar portion 26 of a connection structure 28 (see, e.g., Lo: fig. 17). Lo teaches that having such a layer portion between the solder portion and copper pillar portion of a connection structure can allow the layer to act as a barrier between the portions, preventing solder from penetrating the copper pillar portion to subsequently improve the reliability of the connection structure (see, e.g., Lo: par.0025/ll.10-16).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a layer portion between Chinnusamy’s solder portion and pillar portion, as taught by Lo, so as to allow the layer portion to act as a barrier, preventing solder from penetrating Chinnusamy’s copper pillar portion and to subsequently improve the reliability of Chinnusamy’s connection structure.
Claims 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chinnusamy in view of Pankove (US 5,930,666).
Regarding claim 23, Chinnusamy shows most aspects of the instant invention (see paragraph 10 above). Furthermore, Chinnusamy (see, e.g., col.6/ll.67 through col.7/ll.2) teaches that the at least one semiconductor device 140 may comprise a transistor. However, Chinnusamy fails to specify that Chinnusamy’s transistor comprises gallium nitride (GaN) silicon carbide (SiC). Pankove, in the same field of endeavor, teaches that GaNSiC transistors are suitable for packaging in packaged devices, and further teaches that transistors of this composition are suitable for withstanding high operating temperatures (see, e.g., Pankove: fig.1, col.1/ll.10-19, and col.4/ll.59-61).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chinnusamy’s transistor comprise GaN/SiC, as taught by Pankove, so as to expand the operability of Chinnusamy’s semiconductor device at high temperatures.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chinnusamy in view of Gowda (US 2018/0082981).
Regarding claim 24, Chinnusamy (see, e.g., figs. 1e-1f, col.4/ll.14-17, and col.4/ll.36-37) shows that the at least one integrated passive device comprises a silicon carbide (SiC) integrated passive device (IPD).
Furthermore, Gowda, in the same field of endeavor and in a similar device to Chinnusamy, teaches that integrated passive devices can be formed from any material that enables appropriate connection, including but not limited to SiC (see, e.g., Gowda: pars.0044/ll.7-12 and 0044/ll.23-25).
Therefore, it would further have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chinnusamy’s integrated passive device comprise an SiC integrated passive device, or to comprise any other suitable material, because these were recognized in the semiconductor art as equivalents for their use as integrated passive device materials, and selecting among known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Chinnusamy in view of Lai (US 2020/0212018).
Regarding claim 25, Chinnusamy shows most aspects of the instant invention (see paragraph 10 above). Furthermore, although Chinnusamy teaches that at least one bond pad 144 Chinnusamy’s at least one semiconductor device 140 can allow connection to a printed circuit board (PCB) (see, e.g., figs. 6a-6b and col.7/ll.20-22), Chinnusamy fails to specify that Chinnusamy’s at least one integrated passive device comprises a PCB. Lai, in a similar device to Chinnusamy, teaches integrated package devices and PCBs to be equivalent to each other (see, e.g., Lai: fig. 17B and par.0064/ll.3-9). Lai further teaches that having a PCB can allow the inclusion of discrete integrated circuits and passive devices (see, e.g., Lai: par.0064/ll.9-11).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a PCB as the integrated passive device of Chinnusamy, as taught by Lai, so as to expand the applications of Chinnusamy’s device by allowing the inclusion of discrete circuits and passive devices, and because general integrated passive devices and PCBs were recognized in the semiconductor art as equivalents, and selecting among known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Response to Arguments
With respect to the drawings, the applicant argues:
Applicant has provided a Replacement Sheet of Drawings to address one of the informalities noted by the examiner. Regarding the remaining objections, as supported by the specification, the reference numeral 200 and associated arrow in Figure 5 is referencing the at least one integrated passive device 200 in the exemplary process flow 300. Furthermore, as supported by the specification, the reference numeral 212 illustrated in Figure 7 is referencing the second layer 212 that is part of the seed metal disposition configuration 302. Additionally, as supported in the specification, the reference numeral 400 and associated arrow is referencing the at least one semiconductor device 400 in the exemplary process flow 310. Finally, as supported by the specification, the reference numeral 412 relates to “the second seed layer 412” in both figures 3 and 15. Accordingly, Applicant requests withdrawal of the objections to the drawings.
The examiner responds:
Although the applicant has stated on page 9 of the “Applicant Arguments/Remarks made in an Amendment” document that replacement drawings have been filed, it does not appear to the examiner that “Replacement Sheets” regarding the drawings and specification have been attached. Accordingly, the corresponding objections to the drawings from the previous Office action have been maintained.
Regarding reference numeral 200 and its corresponding drawing objection, figure 5 of the applicant’s drawings shows an arrow corresponding to reference numeral 200 vaguely gesturing to the entirety of the page whereas figures 1-2 of the applicant’s drawings appear to have reference numeral 200 referring to a specific element. Accordingly, it is unclear from the figures alone which specific element to which reference numeral 200 is meant to refer.
Regarding reference numeral 212 and its corresponding drawing objection, figure 7 depicts reference numeral 212 as being part of a first seed metal disposition in direct contact with reference numeral 224 whereas figure 2 depicts reference numeral 212 as being part of a second seed metal disposition directly in contact with reference numeral 211 and not in direct contact with reference numeral 224. Accordingly, it is unclear from the figures alone which specific element of figures 2 and 7 to which element 212 is meant to refer.
Regarding reference numeral 400 and its corresponding drawing objection, figures 3 and 13 of the applicant’s drawings have an arrow corresponding to reference numeral 400 vaguely gesturing to the entirety of the page whereas figure 1 cites reference numeral 400 as referring to a specific element. Furthermore, reference numeral 400 appears twice in figure 3, appearing to indicate to distinct and separate features in the figure. Accordingly, it is unclear from the figures alone which specific element of figures 1, 3, and 13 to which reference numeral 400 is meant to refer.
Regarding reference numeral 412 and its corresponding drawing objection, figure 15 depicts reference numeral 412 as being part of a first seed metal disposition in direct contact with reference numeral 424 whereas figure 3 depicts reference numeral 412 as being part of a second seed metal disposition directly in contact with reference numeral 411 and not in direct contact with reference numeral 424. Accordingly, it is unclear from the figures alone which specific element of figures 3 and 15 to which element 412 is meant to refer.
An objection to drawings under 37 CFR 1.84(p)(4) is not a dispositive finding that the features lack written support; rather it identifies that the figures contain discrepancies that prevent a clear and unambiguous visual understanding of the application’s structures from the features alone. Whether or not the written description may contain support for the feature is a separate inquiry.
For all the reasons listed above, the applicant’s request to withdraw the objections to the drawings is denied.
With regards to the claims, the applicant argues:
Applicant asserts that CHINNUSAMY teaches a non-fusible pillar 118 is fixed to contact pad 112 of semiconductor die 104, the non-fusible pillar 118 comprises the fusible layer 120 that includes solder (see column 5, lines 31 -32) that is brought into physical contact with the contact pad 144 of the substrate 140. See column 7, lines 32 – 48. CHINNUSAMY does not teach nor fairly disclose a “packaged device comprising: at least one integrated passive device comprising at least one bond pad; at least one semiconductor device comprising at least one bond pad; and at least one connection structure arranged on the at least one integrated passive device, wherein the at least one connection structure comprises a solder portion configured to form a solder connection to the at least one bond pad of the at least one semiconductor device” as recited by claim 1.
On the contrary, CHINNUSAMY teaches a non-fusible pillar 118 is fixed to contact pad 112 of semiconductor die 104, the non-fusible pillar 118 comprises the fusible layer 120 that includes solder (see column 5, lines 31 - 32) that is brought into physical contact with the contact pad 144 of the substrate 140. See column 7, lines 32 - 48.
In contrast, the disclosure specifically teaches the benefits of the solder portion 218 on the at least one connection structure 204 and the solder portion 218 being attached to the at least one bond pad 402 of the at least one semiconductor device 400; and the disclosure specifically teaches the limitations and drawbacks of any such structure on a semiconductor device as taught by CHINNUSAMY.
A claim may be properly rejected under 35 U.S.C. § 102 if, and only if, a single prior art reference discloses each and every feature of the invention as recited in the claim. If the rejected claim recites even one feature that is not disclosed by the prior art reference, the 35 U.S.C. § 102 rejection is improper and must be withdrawn. In this case, the rejection of claim 1 must be withdrawn because CHINNUSAMY fails to disclose at least one feature recited in independent claim 1.
The examiner responds:
Applicant argues that Chinnusamy does not teach or fairly disclose a “packaged device comprising: at least one integrated passive device comprising at least one bond pad; at least one semiconductor device comprising at least one bond pad; and at least one connection structure arranged on the at least one integrated passive device, wherein the at least one connection structure comprises a solder portion configured to form a solder connection to the at least one bond pad of the at least one semiconductor device” recited in claim 1. This is not found persuasive.
As put forth in paragraph 12 of the previous Office action mailed on 08/18/2025, Chinnusamy expressly teaches the disputed limitations of independent claim 1. See also paragraph 10 above where the specific claim elements are mapped to the corresponding features in Chinnusamy, demonstrating that each and every feature of claim 1 is present in the prior art. Furthermore, patentability is determined based on the structure that is disclosed in the prior art, not the particular terminology used to describe that structure. “The Patent and Trademark Office ("PTO") determines the scope of claims in patent applications not solely on the basis of the claim language, but upon giving claims their broadest reasonable construction” In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364[, 70 USPQ2d 1827, 1830] (Fed. Cir. 2004). See MPEP § 2111. When the prior art discloses the same structure as the claims, anticipation is not avoided merely because the reference uses different descriptive language. The dispositive inquiry is whether the prior art structure meets the claimed structural limitations, not whether it is labeled using the same terminology as the claims, as the determinative issue in an anticipation analysis is whether the prior art discloses the claimed structure, not whether the reference uses identical terminology or is characterized differently by the applicant.
Here, Chinnusamy (see, e.g., figs. 6a-6b) teaches the same packaged device 154 comprising at least one integrated passive device 104 (see, e.g., col.4/ll.36-37) comprising at least one bond pad 112, at least one semiconductor device 140 (see, e.g., col.6/ll.67 through col.7/ll.2) comprising at least one bond pad 144; and at least one connection structure 122 arranged on the at least one integrated passive device, wherein the at least one connection structure 122 comprises a solder portion 120 (see, e.g., col.5/ll.31-32) configured to form a solder connection to the at least one bond pad 144 of the at least one semiconductor device 140 as recited in claim 1 of the claimed invention. Accordingly, Chinnusamy teaches each and every aspect of the claim.
To the extent the applicant relies on statements in the specification regarding alleged advantages, distinctions, or drawbacks of structures such as those disclosed in Chinnusamy, such arguments are not relevant to the anticipation analysis. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Patentability is determined based on the structure recited in the claims and what is taught by the prior art, and the applicant’s characterizations of alleged benefits, purposes, or criticisms of prior approaches do not avoid anticipation when the prior art teaches the claimed structure. When the prior art discloses the same structural arrangement as that recited in the claims, anticipation is established regardless of any purported differences in stated purpose, advantage, or terminology. Accordingly, arguments directed to the perceived distinctions in alleged intended use, performance, or asserted improvements do not overcome the fact that Chinnusamy discloses the structure recited in the claim.
Moreover, beyond broadly stating that Chinnusamy allegedly fails to disclose the claimed limitations, Applicant has not identified any specific structural feature recited in claim 1 that is absent from Chinnusamy. Conclusory statements that a reference “does not teach” a limitation, without identifying a structural difference, are insufficient to rebut a prima facie case of anticipation where the Office has specifically mapped the claim elements to the reference. Accordingly, for at least the reasons set forth above and in the previous Office action, Chinnusamy teaches each and every limitation of independent claim 1, and the rejection is maintained.
Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new and/or maintained grounds of rejection.
Conclusion
Applicant’s response and amendment necessitated the new and/or maintained grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire three months from the mailing date of this action. In the event a first reply is filed within two months of the mailing date of this final action and the advisory action is not mailed until after the end of the three-month shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the mailing date of this final action.
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shamita Hanumasagar at (703) 756-1521 and between the hours of 7:00 AM to 5:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Shamita.Hanumasagar@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (in USA or Canada) or 571-272-1000.
/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814