Attorney Docket Number: 106222.022140
Filing Date: 06/14/2023
Claimed Priority Date: none
Inventors: Mu et al.
Examiner: Shamita S. Hanumasagar
DETAILED ACTION
This Office action responds to the amendment filed on 05/18/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 05/18/2026 in reply to the previous Office action mailed on 02/18/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-25 and 39-40.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because the following reference characters have been used to designate different parts:
“420” has been used to designate both a semiconductor device and a metallization layer in figure 4
“200” has been used to designate both an exemplary process flow in figure 5 and an integrated passive device in figures 1-2
“212” has been used to designate both a portion of a first metal layer in figure 7 and a second metal layer deposited on a first metal layer in figure 2
“400” has been used to designate both an exemplary process flow in figure 13 and a semiconductor device in figures 1 and 3
“412” has been used to designate both a portion of a first metal layer in figure 15 and a second metal layer deposited on a first metal layer in figure 3
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections
Initially, and with respect to claims 9 and 12-13, note that a “product by process” claim is directed to the product per se, no matter how actually made. See In re Thorpe, 227 USPQ 964 (CAFC, 1985) and the related case law cited therein which makes it clear that it is the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that, as here, an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. As stated in Thorpe,
even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 1348, 162 USPQ 145, 147 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26 USPQ 57, 61 (2d. Cir. 1935).
Note that the applicants have the burden of proof in such cases, as the above case law makes clear.
As to the grounds of rejection under section 103, see MPEP § 2113, which discusses the handling of “product by process” claims and recommends the alternative (§ 102/ § 103) grounds of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 11, 13-18, and 39-40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chinnusamy (US 9,875,988).
Regarding claim 1, Chinnusamy (see, e.g., figs. 6a-6b) shows all aspects of the instant invention, including a packaged device 154 comprising:
at least one integrated passive device 104 (see, e.g., col.4/ll.36-37) comprising at least one bond pad 112;
at least one semiconductor device 140 (see, e.g., col.6/ll.67 through col.7/ll.2) comprising at least one bond pad 144; and
at least one connection structure 122 arranged on the at least one integrated passive device
wherein:
the at least one connection structure 122 comprises a solder portion 120 (see, e.g., col.5/ll.31-32) configured to form a solder connection to the at least one bond pad 144 of the at least one semiconductor device 140
Regarding claim 4, Chinnusamy (see, e.g., figs. 6a-6b) shows all aspects of the instant invention, including a packaged device 154 comprising:
at least one integrated passive device 104 (see, e.g., col.4/ll.36-37) comprising at least one bond pad 112;
at least one semiconductor device 140 (see, e.g., col.6/ll.67 through col.7/ll.2) comprising at least one bond pad 144; and
at least one connection structure 122 arranged on the at least one integrated passive device;
wherein:
the at least one connection structure 122 comprises a solder portion 120 (see, e.g., col.5/ll.31-32) configured to form a solder connection to the at least one bond pad 144 of the at least one semiconductor device 140;
the solder portion 120 is arranged on an end of the at least one connection structure 122 distal from the at least one integrated passive device 104;
and the solder portion 120 is arranged on an end of the at least one connection structure 122 proximal to the at least one semiconductor device 140.
Regarding claim 39, Chinnusamy (see, e.g., figs. 1b-1f and 5a-5f) shows a process of implementing a packaged device comprising:
configuring at least one integrated passive device 104 with at least one bond pad 112;
configuring at least one semiconductor device 140 with at least one bond pad 144;
arranging at least one connection structure 118 on the at least one integrated passive device;
arranging a solder portion 120 on the at least one connection structure; and
connecting the at least one connection structure to the at least one bond pad 144 of the at least one semiconductor device 140 with the solder portion
Regarding claim 2, Chinnusamy (see, e.g., figs. 6a-6b) shows that the at least one integrated passive device 104 comprises one or more under bump metals (see, e.g., par.0036/ll.6-8), that the at least one connection structure 122 is on the one or more under bump metals (see, e.g., par.0036/ll.6-8), and that the solder portion 120 is arranged on an end of the at least one connection structure 122 closer to the at least one bond pad 144 of the semiconductor device 140 than the at least one bond pad 112 of the at least one integrated passive device 104.
Regarding claim 3, Chinnusamy (see, e.g., figs. 6a-6b) shows wherein that:
the at least one integrated passive device 104 comprises one or more under bump metals (see, e.g., par.0036/ll.6-8);
the at least one connection structure 122 is on the one or more under bump metals (see, e.g., par.0036/ll.6-8)
solder portion 120 is arranged on an end of the at least one connection structure 122 closer to the at least one semiconductor device 140 than the at least one bond pad 112 of the at least one integrated passive device 104; and
the at least one connection structure comprises a pillar portion 118 that comprises an electroplated copper structure and/or electroless plated copper structure (see, e.g., col.5/ll.17-25)
Regarding claim 5, Chinnusamy (see, e.g., figs. 6a-6b) shows that the solder portion 120 is arranged on an end of the at least one connection structure 122 distal from the at least one bond pad 112 of the at least one integrated passive device 104, and that the solder portion 120 is arranged on an end of the at least one connection structure 122 proximal to the at least one bond pad 144 of the at least one semiconductor device 140.
Regarding claim 6, Chinnusamy (see, e.g., figs. 6a-6b) shows that the solder portion 120 is arranged on an end of the least one connection structure 122 opposing the at least one semiconductor device 140.
Regarding claim 7, Chinnusamy (see, e.g., figs. 6a-6b) shows that the solder portion 120 is arranged on an end of the at least one connection structure 122 opposing the at least one bond pad 144 of the at least one semiconductor device 140.
Regarding claim 8, Chinnusamy (see, e.g., figs. 6a-6b and col.7/ll.34-36) shows that the solder portion 120 is arranged on an end of the at least one connection structure 122, and that solder portion comprises reflowed solder.
Regarding claim 9, Chinnusamy (see, e.g., figs. 1e-1f) shows that the at least one connection structure 122 is attached to the at least one integrated passive device 104 while the at least one integrated passive device is arranged in a wafer 100 together with a plurality of the at least one integrated passive device prior to singulation of the at least one integrated passive device from the wafer.
Regarding claim 11, Chinnusamy (see, e.g., figs. 1e-1f) shows that the at least one connection structure 122 is arranged on the at least one bond pad 112 of the at least one integrated passive device 104 that is arranged in a wafer.
Regarding claim 13, Chinnusamy (see, e.g., figs. 5c-5d) shows that the at least one connection structure 122 is arranged on the at least one bond pad 112 of the integrated passive device 104 prior to being connected to the at least one bond pad 144 of the at least one semiconductor device 140.
Regarding claim 14, Chinnusamy (see, e.g., figs. 6a-6b) shows that the at least one connection structure 122 is configured to extend vertically below the at least one integrated passive device 104 and connect to the at least one bond pad 144 of the at least one semiconductor device 140.
Regarding claim 15, Chinnusamy (see, e.g., figs. 2 and 5b-5d) shows that:
at least one bond pad 112 of the at least one integrated passive device 104 is arranged on a first surface of the at least one integrated passive device 104; and
the at least one integrated passive device is configured as a flip chip such that the first surface is located adjacent the at least one semiconductor device 140
Regarding claim 16, Chinnusamy (see, e.g., figs. 6a-6b) shows that the at least one connection structure 122 comprises a pillar portion 118 and a solder portion 120.
Regarding claim 17, Chinnusamy (see, e.g., figs. 6a-6b and col.5/ll.17-25) shows the pillar portion 118 that comprises an electroplated metallic structure and/or an electroless plated metallic structure.
Regarding claim 18, Chinnusamy (see, e.g., figs. 6a-6b and col.5/ll.17-25) shows the pillar portion 118 that comprises an electroplated copper structure and/or an electroless plated copper structure.
Regarding claim 40, Chinnusamy (see, e.g., figs. 1d and 5c-5f) shows arranging the solder portion 120 on an end of the at least one connection structure 118 closer to the at least one bond pad 144 of the at least one semiconductor device 140 than the at least one bond pad 112 of the at least one integrated passive device 104, wherein the solder portion 120 is arranged on an end of the at least one connection structure 122 distal from the at least one integrated passive device 104, and wherein the solder portion 120 is arranged on an end of the at least one connection structure proximal to the at least one semiconductor device 140.
Claims 1, 4-7, 14, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noori (US 2021/0313284).
Regarding claim 1, Noori (see, e.g., fig. 1A) shows all aspects of the instant invention, including a packaged device 100a comprising:
at least one integrated passive device 110 comprising at least one bond pad 110p;
at least one semiconductor device 105 comprising at least one bond pad 105p;
at least one connection structure 111 arranged on the at least one integrated passive device;
wherein:
the at least one connection structure 111 comprises a solder portion (see, e.g., par.00671/ll.10-13) configured to form a solder connection to the at least one bond pad 105p of the at least one semiconductor device 105
Regarding claim 23, Noori (see paragraph 29 above and, e.g., par.0063/ll.1-6) shows that the at least one semiconductor device 105 comprises a gallium nitride (GaN) silicon carbide (SiC) transistor.
Regarding claim 1, Noori (see, e.g., fig. 1A) shows all aspects of the instant invention, including a packaged device 100a comprising:
at least one integrated passive device 110 comprising at least one bond pad 110p;
at least one semiconductor device 104 comprising at least one bond pad 104p;
at least one connection structure 111 arranged on the at least one integrated passive device;
wherein:
the at least one connection structure 111 comprises a solder portion (see, e.g., par.00671/ll.10-13) configured to form a solder connection to the at least one bond pad 104p of the at least one semiconductor device 104
Regarding claim 1, Noori (see, e.g., fig. 1A) shows all aspects of the instant invention, including a packaged device 100a comprising:
at least one integrated passive device 110 comprising at least one bond pad 110p;
at least one semiconductor device 106 comprising at least one bond pad 106p;
at least one connection structure 111 arranged on the at least one integrated passive device;
wherein:
the at least one connection structure 111 comprises a solder portion (see, e.g., par.00671/ll.10-13) configured to form a solder connection to the at least one bond pad 106p of the at least one semiconductor device 106
Regarding claim 1, Noori (see, e.g., fig. 1A) shows all aspects of the instant invention, including a packaged device 100a comprising:
at least one integrated passive device 110 comprising at least one bond pad 110p;
at least one semiconductor device 105 comprising at least one bond pad 105p;
at least one connection structure 111 arranged on the at least one integrated passive device;
wherein:
the at least one connection structure 111 comprises a solder portion (see, e.g., par.00671/ll.10-13) configured to form a solder connection to the at least one bond pad 105p of the at least one semiconductor device 105
Regarding claim 4, Noori (see, e.g., fig. 1A) shows all aspects of the instant invention, including a packaged device 100a comprising:
at least one integrated passive device 110 comprising at least one bond pad 110p;
at least one semiconductor device 105 comprising at least one bond pad 105p;
at least one connection structure 110p/111 arranged on the at least one integrated passive device;
wherein:
the at least one connection structure 110p/111 comprises a solder portion 111 (see, e.g., par.00671/ll.10-13) configured to form a solder connection to the at least one bond pad 105p of the at least one semiconductor device 105;
the solder portion is arranged on an end of the at least one connection structure distal from the at least integrated passive device 110; and
the solder portion is arranged on an end of the at least one connection structure proximal to the at least one semiconductor device 105
Regarding claim 4, Noori (see, e.g., fig. 1A) shows all aspects of the instant invention, including a packaged device 100a comprising:
at least one integrated passive device 110 comprising at least one bond pad 110p;
at least one semiconductor device 104 comprising at least one bond pad 104p;
at least one connection structure 110p/111 arranged on the at least one integrated passive device;
wherein:
the at least one connection structure 110p/111 comprises a solder portion 111 (see, e.g., par.00671/ll.10-13) configured to form a solder connection to the at least one bond pad 104p of the at least one semiconductor device 104;
the solder portion is arranged on an end of the at least one connection structure distal from the at least integrated passive device 110; and
the solder portion is arranged on an end of the at least one connection structure proximal to the at least one semiconductor device 104
Regarding claim 4, Noori (see, e.g., fig. 1A) shows all aspects of the instant invention, including a packaged device 100a comprising:
at least one integrated passive device 110 comprising at least one bond pad 110p;
at least one semiconductor device 106 comprising at least one bond pad 106p;
at least one connection structure 110p/111 arranged on the at least one integrated passive device;
wherein:
the at least one connection structure 110p/111 comprises a solder portion 111 (see, e.g., par.00671/ll.10-13) configured to form a solder connection to the at least one bond pad 106p of the at least one semiconductor device 106;
the solder portion is arranged on an end of the at least one connection structure distal from the at least integrated passive device 110; and
the solder portion is arranged on an end of the at least one connection structure proximal to the at least one semiconductor device 106
Regarding claim 39, Noori (see, e.g., fig. 1A and pars.0062-0069) shows all aspects of the instant invention, including a process of implementing a packaged device 100a comprising:
configuring at least one integrated passive device 110 comprising at least one bond pad 110p;
configuring at least one semiconductor device 105 comprising at least one bond pad 105p;
arranging at least one connection structure 110p on the at least one integrated passive device;
arranging a solder portion 111 on the at least one connection structure (see, e.g., par.00671/ll.10-13); and
connecting the at least one connection structure to the at least one bond pad of the at least one semiconductor device with the solder portion (see, e.g., par.00671/ll.10-13)
Regarding claim 39, Noori (see, e.g., fig. 1A and pars.0062-0069) shows all aspects of the instant invention, including a process of implementing a packaged device 100a comprising:
configuring at least one integrated passive device 110 comprising at least one bond pad 110p;
configuring at least one semiconductor device 104 comprising at least one bond pad 104p;
arranging at least one connection structure 110p on the at least one integrated passive device;
arranging a solder portion 111 on the at least one connection structure (see, e.g., par.00671/ll.10-13); and
connecting the at least one connection structure to the at least one bond pad of the at least one semiconductor device with the solder portion (see, e.g., par.00671/ll.10-13)
Regarding claim 39, Noori (see, e.g., fig. 1A and pars.0062-0069) shows all aspects of the instant invention, including a process of implementing a packaged device 100a comprising:
configuring at least one integrated passive device 110 comprising at least one bond pad 110p;
configuring at least one semiconductor device 106 comprising at least one bond pad 106p;
arranging at least one connection structure 110p on the at least one integrated passive device;
arranging a solder portion 111 on the at least one connection structure (see, e.g., par.00671/ll.10-13); and
connecting the at least one connection structure to the at least one bond pad of the at least one semiconductor device with the solder portion (see, e.g., par.00671/ll.10-13)
Regarding claim 1, Noori (see, e.g., fig. 1A) shows all aspects of the instant invention, including a packaged device 100a comprising:
at least one integrated passive device 110 comprising at least one bond pad 110p;
at least one semiconductor device 105 comprising at least one bond pad 105p;
at least one connection structure 110p/111 arranged on the at least one integrated passive device;
wherein:
the at least one connection structure 110p/111 comprises a solder portion 111 (see, e.g., par.00671/ll.10-13) configured to form a solder connection to the at least one bond pad 105p of the at least one semiconductor device 105
Regarding claim 5, Noori (see paragraph 40 above and, e.g., fig. 1) shows that the solder portion 111 is arranged on an end of the at least one connection structure 110p/111 distal from the at least one bond pad 110p of the at least one integrated passive device, and that the solder portion is arranged on an end of the at least one connection structure proximal to the at least one bond pad 105p of the at least one semiconductor device 105.
Regarding claim 6, Noori (see paragraph 40 above and, e.g., fig. 1) shows that the solder portion 111 is arranged on an end of the at least one connection structure 110p/111 opposing the at least one semiconductor 105.
Regarding claim 7, Noori (see paragraph 40 above and, e.g., fig. 1) shows that the solder portion 111 is arranged on an end of the at least one connection structure 110p/111 opposing the at least one bond pad 105p of the at least one semiconductor 105.
Regarding claim 14, Noori (see paragraph 40 above and, e.g., fig. 1) shows that the at least one connection structure 110p/111 is configured to extend vertically below the at least one integrated passive device 110 and connected to the at least one bond pad 105p of the at least one semiconductor device 105.
Regarding claim 23, Noori (see paragraph 40 above and, e.g., par.0063/ll.1-6) shows that the at least one semiconductor device 105 comprises a gallium nitride (GaN) silicon carbide (SiC) transistor.
Regarding claim 1, Noori (see, e.g., fig. 1A) shows all aspects of the instant invention, including a packaged device 100a comprising:
at least one integrated passive device 110 comprising at least one bond pad 110p;
at least one semiconductor device 104 comprising at least one bond pad 104p;
at least one connection structure 110p/111 arranged on the at least one integrated passive device;
wherein:
the at least one connection structure 110p/111 comprises a solder portion 111 (see, e.g., par.00671/ll.10-13) configured to form a solder connection to the at least one bond pad 104p of the at least one semiconductor device 104
Regarding claim 5, Noori (see paragraph 46 above and, e.g., fig. 1) shows that the solder portion 111 is arranged on an end of the at least one connection structure 110p/111 distal from the at least one bond pad 110p of the at least one integrated passive device, and that the solder portion is arranged on an end of the at least one connection structure proximal to the at least one bond pad 104p of the at least one semiconductor device 104.
Regarding claim 6, Noori (see paragraph 4640 above and, e.g., fig. 1) shows that the solder portion 111 is arranged on an end of the at least one connection structure 110p/111 opposing the at least one semiconductor 104.
Regarding claim 7, Noori (see paragraph 46 above and, e.g., fig. 1) shows that the solder portion 111 is arranged on an end of the at least one connection structure 110p/111 opposing the at least one bond pad 104p of the at least one semiconductor 104.
Regarding claim 14, Noori (see paragraph 46 above and, e.g., fig. 1) shows that the at least one connection structure 110p/111 is configured to extend vertically below the at least one integrated passive device 110 and connected to the at least one bond pad 104p of the at least one semiconductor device 104.
Regarding claim 1, Noori (see, e.g., fig. 1A) shows all aspects of the instant invention, including a packaged device 100a comprising:
at least one integrated passive device 110 comprising at least one bond pad 110p;
at least one semiconductor device 106 comprising at least one bond pad 106p;
at least one connection structure 110p/111 arranged on the at least one integrated passive device;
wherein:
the at least one connection structure 110p/111 comprises a solder portion 111 (see, e.g., par.00671/ll.10-13) configured to form a solder connection to the at least one bond pad 106p of the at least one semiconductor device 106
Regarding claim 5, Noori (see paragraph 51 above and, e.g., fig. 1) shows that the solder portion 111 is arranged on an end of the at least one connection structure 110p/111 distal from the at least one bond pad 110p of the at least one integrated passive device, and that the solder portion is arranged on an end of the at least one connection structure proximal to the at least one bond pad 106p of the at least one semiconductor device 106.
Regarding claim 6, Noori (see paragraph 514640 above and, e.g., fig. 1) shows that the solder portion 111 is arranged on an end of the at least one connection structure 110p/111 opposing the at least one semiconductor 106.
Regarding claim 7, Noori (see paragraph 51 above and, e.g., fig. 1) shows that the solder portion 111 is arranged on an end of the at least one connection structure 110p/111 opposing the at least one bond pad 106p of the at least one semiconductor 106.
Regarding claim 14, Noori (see paragraph 51 above and, e.g., fig. 1) shows that the at least one connection structure 110p/111 is configured to extend vertically below the at least one integrated passive device 110 and connected to the at least one bond pad 106p of the at least one semiconductor device 106.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by, or in the alternative, under 35 U.S.C. 103 as obvious over Chinnusamy.
Regarding claim 9, Chinnusamy (see, e.g., figs. 1e-1f) shows that the at least one connection structure 122 is attached to the at least one integrated passive device 104 while the at least one integrated passive device is arranged in a wafer 100 together with a plurality of the at least one integrated passive device prior to singulation of the at least one integrated passive device from the wafer.
Nevertheless, it is noted that that Chinnusamy shows all structural aspects of the packaged device according to the claimed invention (see also paragraph 10 above), and that the wafer-related method steps of having the above arrangement “arranged in a wafer together with a plurality of the at least one integrated passive device prior to singulation of the at least one integrated passive device from the wafer” are intermediate steps that do not affect the structure of the final device.
Regarding claim 12, Chinnusamy (see, e.g., figs. 5e-5f and 6a-6b) shows that the at least one semiconductor device 140 is connected to the at least one connection structure 122 of the integrated passive device 104.
Accordingly, it is noted that that Chinnusamy shows all structural aspects of the packaged device according to the claimed invention (see also paragraph 10 above), and that the method steps of having the above arrangement during wafer processing of the at least one integrated passive device are intermediate steps that do not affect the structure of the final device.
Regarding claim 13, Chinnusamy (see, e.g., figs. 5c-5d) shows that the at least one connection structure 122 is arranged on the at least one bond pad 112 of the integrated passive device 104 prior to being connected to the at least one bond pad 144 of the at least one semiconductor device 140.
Nevertheless, it is noted that that Chinnusamy shows all structural aspects of the packaged device according to the claimed invention (see also paragraph 10 above), and that the method steps of having the above arrangement “prior to being connected to the at least one bond pad of the at least one semiconductor device” are intermediate steps that do not affect the structure of the final device.
Claims 9 and 12 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by, or in the alternative, under 35 U.S.C. 103 as obvious over Noori.
Regarding claim 9, Noori (see paragraphs 40, 46, and 51 above and, e.g., fig. 1a) shows that the at least one connection structure 110p/111 is attached to the at least one integrated passive device 110.
Accordingly, is noted that that Noori shows all structural aspects of the packaged device according to the claimed invention (see also paragraph 40 above), and that the wafer-related method steps of having the above arrangement “arranged in a wafer together with a plurality of the at least one integrated passive device prior to singulation of the at least one integrated passive device from the wafer” are intermediate steps that do not affect the structure of the final device.
Regarding claim 12, Noori (see paragraph 40 above and, e.g., fig. 1a) shows that the at least one semiconductor device 105 is connected to the at least one connection structure 110p/111 of the integrated passive device 105.
Accordingly, it is noted that that Noori shows all structural aspects of the packaged device according to the claimed invention (see also paragraph 40 above), and that the method steps of having the above arrangement during wafer processing of the at least one integrated passive device are intermediate steps that do not affect the structure of the final device.
Regarding claim 12, Noori (see paragraph 46 above and, e.g., fig. 1a) shows that the at least one semiconductor device 104 is connected to the at least one connection structure 110p/111 of the integrated passive device 104.
Accordingly, it is noted that that Noori shows all structural aspects of the packaged device according to the claimed invention (see also paragraph 46 above), and that the method steps of having the above arrangement during wafer processing of the at least one integrated passive device are intermediate steps that do not affect the structure of the final device.
Regarding claim 12, Noori (see paragraph 51 above and, e.g., fig. 1a) shows that the at least one semiconductor device 106 is connected to the at least one connection structure 110p/111 of the integrated passive device 106.
Accordingly, it is noted that that Noori shows all structural aspects of the packaged device according to the claimed invention (see also paragraph 51 above), and that the method steps of having the above arrangement during wafer processing of the at least one integrated passive device are intermediate steps that do not affect the structure of the final device.
Claims 1 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2020/0135677) in view of Meyer (US 2017/0309582) and Noori.
Regarding claim 1, Chang (see, e.g., fig. 23) shows most aspects of the instant invention, including a packaged device comprising:
at least one component 71 comprising a passive device (see, e.g., pars.0040/ll.3-9 and 0041/ll.1-3) comprising at least one bond pad 96 (see, e.g., par.0043/ll.17);
at least one semiconductor device 22 comprising at least one bond pad 54B; and
at least one connection structure 106/112 arranged on the at least one die/packaged component 71 comprising a passive device
wherein:
the at least one connection structure 106/112 comprises a solder portion 112 configured to form a solder connection to the at least one bond pad 54B of the at least one semiconductor device 2222
Chang shows most aspects of the instant invention. Chang further teaches that Chang’s packaged device includes at least one component 71 comprising a passive device, and that device dies and logic dies are suitable for use as Chang’s component 71 (see, e.g., pars.0040/ll.3-9 and 0041/ll.1-7). Chang, however, fails to explicitly specify that Chang’s component is an integrated passive device. Meyer, in the same field of endeavor, teaches integrated passive devices to function equivalently to various other device dies, including logic dies, in packaged devices (see, e.g., Meyer: par.0016/ll.1-8). Furthermore, Noori, in the same field of endeavor, specifically teaches that a variety of functional blocks can be realized through the use of integrated passive devices (see, e.g., Noori: par.0009/ll.1-4).
Meyer is evidence showing that one of ordinary skill in the art would appreciate that having an integrated passive device would be equivalent to having a logic or other device in Chang’s packaged device, and that such differences would result in no unexpected changes in the performance of the packaged device of Chang. That is, the device components of both Meyer and Chang would yield the predictable result of providing a suitable electronic component capable of hosting applicable circuitry and communicating with other electronic components.
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have as Chang’s component be either an integrated passive device, as taught by Meyer, or another type of device, as taught by Chang, because these were recognized as equivalents in the semiconductor art and would yield the predictable result of providing a suitable electronic component capable of hosting applicable circuitry and communicating with other electronic components. KSR International Co. v. Teleflex Inc., 550 U.S.-- ,82 USPQ2d 1385 (2007).
Moreover, Noori is evidence that it would have been obvious at the time of filing the invention that one of ordinary skill in the art would find particular incentive to have Chang’s components 71 be integrated passive devices, so as to realize a variety of functional blocks in Chang’s device, as taught by Noori, thereby expanding the applications of Chang’s device.
Regarding claim 10, Chang (see, e.g., fig. 21) shows that the at least one semiconductor device 22 is arranged on the at least one connection structure 106/112 of the at least one integrated passive device 71 (see the comments stated above in paragraphs 74-78 regarding the integrated passive device, which are considered to be repeated here) while the at least one integrated passive device is arranged in a wafer 70 together with a plurality of the at least one integrated passive device.
Regarding claim 11, Chang (see, e.g., fig. 21) shows that the at least one connection structure 106/112 is arranged on the at least on the at least one bond pad 96 of the at least one integrated passive device 71 (see the comments stated above in paragraphs 74-78 regarding the integrated passive device, which are considered to be repeated here) that is arranged in a wafer 70.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chinnusamy in view of Yu (US 2013/0277830).
Regarding claim 19, Chinnusamy teaches most aspects of the instant invention (see paragraphs 10 and 24 above). Chinnusamy (see, e.g., col.5/ll.30-31) further shows that the conductive solder portion 120 comprises printed solder. Additionally, Chinnusamy (see, e.g., col.4/ll.7-8 and col.5/ll.49-50) further teaches Chinnusamy’s electrical connections may use conductive paste. Therefore, Chinnusamy shows that the solder portion comprises a printed solder paste.
Furthermore, Yu, in a similar device to Chinnusamy, teaches solder and solder paste to be equivalent for their use in a solder portion connecting a copper pillar 122 to a bond pad 116 in a connection structure 122/124 (see, e.g., Yu: fig. 1 and par.0021/ll.5-7).
Therefore, it would have been further obvious at the time of filing the invention to one of ordinary skill in the art to use either solder or solder paste in Chinnusamy’s solder portion because these were recognized in the semiconductor art as equivalents for their use as solder portion materials, and selecting among known equivalents would be within the level of ordinary skill in the art. International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 20, Chinnusamy teaches most aspects of the instant invention (see paragraphs 10 and 24 above). Chinnusamy (see, e.g., figs. 6a-6b, col.5/ll.17-25, and col.5/ll.30-31) further shows that:
the pillar portion 118 that comprises an electroplated copper structure and/or an electroless plated copper structure; and
the conductive solder portion 120 comprises printed solder
Additionally, Chinnusamy (see, e.g., col.4/ll.7-8 and col.5/ll.49-50) further teaches Chinnusamy’s electrical connections may use conductive paste. Therefore, Chinnusamy shows that the solder portion comprises a printed solder paste.
Furthermore, Yu, in a similar device to Chinnusamy, teaches solder and solder paste to be equivalent for their use in a solder portion connecting a copper pillar 122 to a bond pad 116 in a connection structure 122/124 (see, e.g., Yu: fig. 1 and par.0021/ll.5-7).
Therefore, it would have been further obvious at the time of filing the invention to one of ordinary skill in the art to use either solder or solder paste in Chinnusamy’s solder portion because these were recognized in the semiconductor art as equivalents for their use as solder portion materials, and selecting among known equivalents would be within the level of ordinary skill in the art. International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chinnusamy in view of Lo (US 2011/0084381).
Regarding claim 21, Chinnusamy teaches most aspects of the instant invention (see paragraphs 10 and 24 above). Furthermore, Chinnusamy (see, e.g., figs. 6a-6b and col.5/ll.17-25) shows that Chinnusamy’s pillar portion 118 comprises an electroplated copper structure and/or an electroless plated copper structure. However, Chinnusamy fails to specify that the pillar portion further comprises a nickel (Ni) barrier layer portion arranged between Chinnusamy’s solder 120 and pillar portion.
Lo, in the same field of endeavor and in a similar device to Chinnusamy, shows having a Ni barrier layer portion 31 between a solder portion 27 and copper pillar portion 26 of a connection structure 28 (see, e.g., Lo: fig. 17). Lo teaches that having a Ni barrier portion between the solder portion and the copper pillar portion of a connection structure prevents solder from penetrating the copper pillar portion and subsequently improves the reliability of the connection structure (see, e.g., Lo: par.0025/ll.10-16).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a Ni barrier layer portion between Chinnusamy’s solder portion and pillar portion, as taught by Lo, so as to prevent solder from penetrating Chinnusamy’s copper pillar to subsequently improve the reliability of Chinnusamy’s connection structure.
Regarding claim 22, Chinnusamy teaches most aspects of the instant invention (see paragraphs 10 and 24 above). Chinnusamy, however, fails to specify that the pillar portion further comprises a layer portion arranged between Chinnusamy’s solder 120 and pillar portion.
Lo, in the same field of endeavor and in a similar device to Chinnusamy, shows having a layer portion 31 between a solder portion 27 and copper pillar portion 26 of a connection structure 28 (see, e.g., Lo: fig. 17). Lo teaches that having such a layer portion between the solder portion and copper pillar portion of a connection structure can allow the layer to act as a barrier between the portions, preventing solder from penetrating the copper pillar portion to subsequently improve the reliability of the connection structure (see, e.g., Lo: par.0025/ll.10-16).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a layer portion between Chinnusamy’s solder portion and pillar portion, as taught by Lo, so as to allow the layer portion to act as a barrier, preventing solder from penetrating Chinnusamy’s copper pillar portion and to subsequently improve the reliability of Chinnusamy’s connection structure.
Claims 23 is rejected under 35 U.S.C. 103 as being unpatentable over Chinnusamy in view of Pankove (US 5,930,666).
Regarding claim 23, Chinnusamy shows most aspects of the instant invention (see paragraph 10 above). Furthermore, Chinnusamy (see, e.g., col.6/ll.67 through col.7/ll.2) teaches that the at least one semiconductor device 140 may comprise a transistor. However, Chinnusamy fails to specify that Chinnusamy’s transistor comprises gallium nitride (GaN) silicon carbide (SiC). Pankove, in the same field of endeavor, teaches that GaNSiC transistors are suitable for packaging in packaged devices, and further teaches that transistors of this composition are suitable for withstanding high operating temperatures (see, e.g., Pankove: fig.1, col.1/ll.10-19, and col.4/ll.59-61).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chinnusamy’s transistor comprise GaN/SiC, as taught by Pankove, so as to expand the operability of Chinnusamy’s semiconductor device at high temperatures.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Chinnusamy in view of Gowda (US 2018/0082981).
Regarding claim 24, Chinnusamy (see, e.g., figs. 1e-1f, col.4/ll.14-17, and col.4/ll.36-37) shows that the at least one integrated passive device comprises a silicon carbide (SiC) integrated passive device (IPD).
Furthermore, Gowda, in the same field of endeavor and in a similar device to Chinnusamy, teaches that integrated passive devices can be formed from any material that enables appropriate connection, including but not limited to SiC (see, e.g., Gowda: pars.0044/ll.7-12 and 0044/ll.23-25).
Therefore, it would further have been obvious at the time of filing the invention to one of ordinary skill in the art to have Chinnusamy’s integrated passive device comprise an SiC integrated passive device, or to comprise any other suitable material, because these were recognized in the semiconductor art as equivalents for their use as integrated passive device materials, and selecting among known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Chinnusamy in view of Lai (US 2020/0212018).
Regarding claim 25, Chinnusamy shows most aspects of the instant invention (see paragraph 10 above). Furthermore, although Chinnusamy teaches that at least one bond pad 144 Chinnusamy’s at least one semiconductor device 140 can allow connection to a printed circuit board (PCB) (see, e.g., figs. 6a-6b and col.7/ll.20-22), Chinnusamy fails to specify that Chinnusamy’s at least one integrated passive device comprises a PCB. Lai, in a similar device to Chinnusamy, teaches integrated package devices and PCBs to be equivalent to each other (see, e.g., Lai: fig. 17B and par.0064/ll.3-9). Lai further teaches that having a PCB can allow the inclusion of discrete integrated circuits and passive devices (see, e.g., Lai: par.0064/ll.9-11).
Therefore, it would have been obvious at the time of filing the invention to one of ordinary skill in the art to include a PCB as the integrated passive device of Chinnusamy, as taught by Lai, so as to expand the applications of Chinnusamy’s device by allowing the inclusion of discrete circuits and passive devices, and because general integrated passive devices and PCBs were recognized in the semiconductor art as equivalents, and selecting among known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Response to Arguments
With respect to the drawings, the applicant argues:
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4). Office Action, at 3. The objection is respectfully traversed. In this regard, Applicant has provided Replacement Sheets of Drawings to address one of the informalities noted by the Examiner. Accordingly, Applicant asserts that the drawing objections have been overcome.
The examiner responds:
Although the applicant has asserted on page 10 of the “Applicant Arguments/Remarks made in an Amendment” document that replacement drawings have been filed, it does not appear to the Examiner that “Replacement Sheets” regarding the drawings and/or specification have been attached. Moreover, Applicant’s arguments as filed on 05/18/2026 have only provided a general conclusory statement that the objections to the drawings have been traversed and have not provided any specific or detailed explanation of any alleged errors in Examiner’s previously noted drawing objections. Accordingly, the corresponding objections to the drawings from the previous Office actions mailed on 08/18/2025 and 02/18/2026 are been maintained.
With regards to the claims, the applicant additionally argues:
Applicant acknowledges the Examiner's comments in Section 5, page 4 of the Office Action. The Examiner states that "method steps... during wafer processing are intermediate steps that do not affect the structure of the final device." Applicant respectfully disagrees because the "during wafer processing of the [IPD]" limitation, when read in view of the application, is not merely a temporal step; it is tied to an architecture in which the connection structure is formed on and remains on the IPD wafer and is used to attach the semiconductor die to the IPD at wafer level. The present application repeatedly describes wafer level processing where the connection structure is structured/arranged on the IPD while the IPD is still in wafer form and the semiconductor die is attached during wafer level processing. Because CHINNUSAMY instead teaches formation of the micro pillar connection structures on the semiconductor die (not on an IPD wafer) and direct attach to a substrate, the claimed product-defined by where the connection structure resides in the final assembled stack-is structurally distinct.
The Examiner responds:
Applicant’s arguments have been considered but are not persuasive. The disputed limitation of claim 12, dependent on independent claim 1, recites that “at least one semiconductor device is connected to the at least one connection structure of the at least one integrated passive device during wafer processing of the at least one integrated passive device”. The language of “during wafer processing of the at least one integrated passive device” merely specifies when or under what manufacturing conditions the recited actions are performed. The limitation does not positively recite any structural characteristic of the claimed final device resulting from the wafer-processing environment, nor does it require a structure that would be distinguishable from an otherwise identical device produced by a different process.
Product claims are distinguished based on the structure of the claimed product, not on the manner in which the product is made, absent a demonstrated structural difference. Applicant asserts that the limitation is tied to an architecture in which the connection structure is formed on and remains on the IPD wafer and is used to attach the semiconductor die at the wafer level. However, the features upon which applicant relies (i.e., a “connection structure formed on and remain[ing] on [an] IPD wafer and is used to attach the semiconductor die to the IPD at wafer level”) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The structural claim language at issue merely requires that “at least one semiconductor device is connected to the at least one connection structure of the at least one integrated passive device”. The phrase “during wafer processing of the IPD” subsequently does not impose any structural limitation on the final assembled device beyond the recited components and their relationships, which Chinnusamy already shows (see paragraphs 10 and 58-61 above). Even in an exemplary case that a prior art forms a structure using a different manufacturing sequence, a product claim is not patentable merely because it is made be a different process. The determinative inquiry is whether the claimed product is structurally distinct from the prior art product. Applicant has not showed that performing the arrangement “during wafer processing of the IPD” results in a structurally different final device. Therefore, the limitation is not sufficient to distinguish over the applied art.
Applicant has not identified, and the claims do not recite, any structural feature of the final device that necessarily results from performing the arrangement during wafer processing rather than at another stage of manufacture. Accordingly, the limitation is interpreted as a process limitation that does not distinguish the claimed product from the prior art product, and the recited timing of manufacture does not impart patentable weight to the claimed final product.
With regards to the claims, the applicant additionally argues:
The disclosure specifically teaches the benefits of the solder portion 218 on the at least one connection structure 204 and the solder portion 218 being attached to the at least one bond pad 402 of the at least one semiconductor device 400; and the disclosure specifically teaches the limitations and drawbacks of any such structure on a semiconductor device.
CHINNUSAMY does not disclose (and therefore cannot anticipate) an arrangement in which the connection structure is on an IPD that is then stacked with a semiconductor device as claimed; rather, CHINNUSAMY's composite interconnect structures are formed over the semiconductor die and are used for direct die-to-substrate attachment. Accordingly, at least the limitations requiring (i) an integrated passive device and (ii) the connection structure arranged on the integrated passive device are not disclosed in CHINNUSAMY, and the §102 rejection is improper.
CHINNUSAMY is anchored in a DCALGA die-to-substrate paradigm in which the die is mounted to a substrate and the non-fusible pillar establishes standoff while only the solder layer reflows. In contrast, Applicant's disclosure addresses different constraints and objectives: enabling wafer level stacking of a semiconductor die onto an IPD wafer (including processing bumps/pillars on the IPD wafer, and providing semiconductor die bond pad metallurgy compatible with solder reflow). Nothing in CHINNUSAMY suggests introducing an IPD as the mounting base for the connection structures or re-architecting the assembly so that the connection structures reside on an IPD wafer for wafer level die attach; CHINNUSAMY instead teaches forming and using the composite interconnect structures on the semiconductor die for direct attachment to a substrate. Moreover, CHINNUSAMY emphasizes advantages tied to its own process sequencing-specifically, performing reflow after mounting the semiconductor die to the substrate and highlighting elimination of wafer level reflow operations in that context. Applicant's disclosure, in contrast, explicitly relies on wafer level processing of the IPD wafer and wafer level attachment/singulation flows to achieve wafer level packaging of the stacked assembly.
The claims recite a specific structural arrangement (connection structure on an IPD used to connect to a semiconductor device) and a wafer level integration approach that are not taught or suggested by CHINNUSAMY's die side micro pillar, direct attach DCALGA framework.
For anticipation, the reference must disclose each and every limitation as in the claim. The Examiner asserts that CHINNUSAMY teaches claim 1 by labeling the semiconductor die 104 as an "integrated passive device" and the substrate/PCB 140 as a "semiconductor device." But CHINNUSAMY expressly identifies 104 as a semiconductor die and 140 as a substrate/PCB, and discloses the connection structure on the die (not on an IPD). Accordingly, CHINNUSAMY does not disclose the claimed IPD based structural arrangement, and the §102 rejection of claim 1 should be withdrawn.
For at least the reasons above, the Office's anticipation position depends on relabeling CHINNUSAMY's semiconductor die 104 as an "integrated passive device" and relabeling the substrate/PCB 140 as a "semiconductor device," contrary to the express disclosures of CHINNUSAMY. When the reference is applied consistent with its own description, it does not disclose (i) an IPD as claimed, (ii) a connection structure arranged on the IPD, or (iii) solder connection from that IPD side structure to a semiconductor device bond pad as required by claim 1. Accordingly, the §102 rejections should be withdrawn
The examiner responds:
Applicant argues that Chinnusamy does not teach or fairly disclose a “packaged device comprising: at least one integrated passive device comprising at least one bond pad; at least one semiconductor device comprising at least one bond pad; and at least one connection structure arranged on the at least one integrated passive device, wherein the at least one connection structure comprises a solder portion configured to form a solder connection to the at least one bond pad of the at least one semiconductor device” recited in claim 1. This is not found persuasive.
As put forth in paragraph 12 of the previous Office action mailed on 08/18/2025 and in paragraph 10 of the previous Office action mailed on 02/18/2026, Chinnusamy expressly teaches the disputed limitations of independent claim 1. See also paragraph 10 above where the specific claim elements are mapped to the corresponding features in Chinnusamy, demonstrating that each and every feature of claim 1 is present in the prior art. For example, contrary to Applicant’s arguments that Chinnusamy does not (wherein it is noted that Applicant has not provided information on where in Chinnusamy support for Applicant’s assertion may be found), Chinnusamy’s disclosure does expressly teach at least one integrated passive device (“IPD”) 104 (see, e.g., col.4/ll.36-37) and a least one semiconductor device 140 (which is not limited to only a substrate/PCB as asserted by the Applicant) (see, e.g., col.6/ll.67 through col.7/ll.2). Furthermore, patentability is determined based on the structure that is disclosed in the prior art, not the particular terminology used to describe that structure. “The Patent and Trademark Office ("PTO") determines the scope of claims in patent applications not solely on the basis of the claim language, but upon giving claims their broadest reasonable construction” In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364[, 70 USPQ2d 1827, 1830] (Fed. Cir. 2004). See MPEP § 2111. When the prior art discloses the same structure as the claims, anticipation is not avoided merely because the reference uses different descriptive language or because. The dispositive inquiry is whether the prior art structure meets the claimed structural limitations, not whether it is labeled using the same terminology as the claims, as the determinative issue in an anticipation analysis is whether the prior art discloses the claimed structure, not whether the reference uses identical terminology or is characterized differently by the applicant.
Here, Chinnusamy (see, e.g., figs. 6a-6b) teaches the same packaged device 154 comprising at least one integrated passive device 104 (see, e.g., col.4/ll.36-37) comprising at least one bond pad 112, at least one semiconductor device 140 (see, e.g., col.6/ll.67 through col.7/ll.2) comprising at least one bond pad 144; and at least one connection structure 122 arranged on the at least one integrated passive device, wherein the at least one connection structure 122 comprises a solder portion 120 (see, e.g., col.5/ll.31-32) configured to form a solder connection to the at least one bond pad 144 of the at least one semiconductor device 140 as recited in claim 1 of the claimed invention. Accordingly, Chinnusamy teaches each and every aspect of the claim.
To the extent the applicant relies on statements in the specification regarding alleged advantages, distinctions, or drawbacks of structures such as those disclosed in Chinnusamy, such arguments are not relevant to the anticipation analysis. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Patentability is determined based on the structure recited in the claims and what is taught by the prior art, and the applicant’s characterizations of alleged benefits, purposes, or criticisms of prior approaches do not avoid anticipation when the prior art teaches the claimed structure. When the prior art discloses the same structural arrangement as that recited in the claims, anticipation is established regardless of any purported differences in stated purpose, advantage, or terminology. Accordingly, arguments directed to the perceived distinctions in alleged intended use, performance, or asserted improvements do not overcome the fact that Chinnusamy discloses the structure recited in the claim. Accordingly, Applicant’s assertions that Chinnusamy is directed to a different paradigm and intended use than that of the instant application does not preclude Chinnusamy from teaching the required product structure as claimed and such arguments are not found persuasive.
As stated above, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Consequently, Applicant’s assertion that Chinnusamy fails to disclose features such as “introducing an IPD as the mounting base for the connection structures or re-architecting the assembly so that the connection structures reside on an IPD wafer for wafer level die attach”, “a wafer level integration approach”, and “an arrangement in which the connection structure is on an IPD that is then stacked with a semiconductor device as claimed” are found unpersuasive as such features are absent from the claims. As recited from the claims and responsive to Applicant’s arguments, Chinnusamy (see, e.g., fig.s 6a-6b) does teach (i) an IPD 104 as claimed, (ii) a connection structure 122 arranged on the IPD, and (iii) a solder portion 120 configured to form a solder connection to a semiconductor device 140 bond pad 144. Accordingly, for at least the reasons set forth above and in the previous Office action(s), Chinnusamy teaches each and every limitation of independent claim 1, and the rejection is maintained. These arguments are considered to be similarly repeated for all 35 U.S.C. § 102 independent claim rejections reliant on Chinnusamy.
With regards to the claims, the applicant additionally argues:
Applicant asserts that the Application expressly distinguishes the IPD (200) from both the semiconductor device (400) and from downstream substrates/PCBs, assigning each a separate structural role, reference numeral, and function within the packaged device architecture (see paragraphs [0068]-[0071], [0081]-[0084]). Because the Application clearly defines "integrated passive device (IPD)" as a device distinct from the semiconductor device that integrates passive components and hosts the claimed connection structure, and this definition is consistent with what one of ordinary skill would understand is an IPD, this definition must govern claim interpretation. Further, Applicant can act as its own lexicographer, and this definition must likewise govern claim interpretation. When the claims are properly construed in accordance with the Application’s express definitions, the cited reference fails to disclose the required IPD-based structure, and the §102 rejection is improper.
The Examiner responds:
Chinnusamy’s disclosure expressly and separately teaches at least one integrated passive device (“IPD”) 104 (see, e.g., col.4/ll.36-37) and a least one semiconductor device 140 (which is not limited to only a substrate/PCB as asserted by the Applicant) (see, e.g., col.6/ll.67 through col.7/ll.2). Furthermore, Applicant’s assertion that the application “expressly distinguishes the IPD (200) from… downstream substrates/PCBs” is found unpersuasive and is contradicted by the specification and claims themselves. Specifically, paragraph 0069, cited by Applicant in support of this argument, expressly identifies a “printed circuit board (PCB) and/or the like” as an example of a valid “integrated passive device 200”. Furthermore, Applicant’s own original claim, claim 25, expressly claims that the “at least one integrated passive device comprises a printed circuit board (PCB). Thus, Applicant’s own specification and claims do not draw the distinction now asserted, but instead affirmatively encompasses printed circuit boards as within the scope of the disclosed integrated passive device. In view of this express disclosure, the Examiner finds no basis for excluding a PCB from the claimed integrated passive device, nor any basis for Applicant’s new contention that the claims require a distinction between the IPD and downstream substrates/PCBs. Applicant’s argument is therefore inconsistent with the plain language of the specification and claims and is not persuasive. Accordingly, it is unclear to the Examiner why a printed circuit board would be permitted as an integrated passive device in Applicant’s application, as directly stated by Applicant in paragraph 0069, but not in the prior art.
Additionally, Applicant’s contention that the specification acts as its own lexicographer regarding IPDs is not persuasive. To act as its own lexicographer, Applicant must clearly set forth a definition of the disputed term and clearly express an intent to redefine the term. The portions of the specification cited by Applicant merely describe particular embodiments and examples and do not contain a clear definitional statement specifying the exact constitutions of an IPD in all embodiments. Descriptions of exemplary embodiments do not, without more, constitute lexicography or mandate that corresponding limitations be imported into the claims.
Moreover, the specification lacks any language indicating that the term “integrated passive device” or “IPD” is being assigned a special definition that departs from its ordinary and customary meaning. In fact, even Applicant’s arguments assert that the definition for an IPD used in the instant application “is consistent with what one of ordinary skill would understand is an IPD”. The specification also does not state than an IPD must, in all instances, be distinct from a semiconductor device or must exclude structures such as printed circuit boards. Accordingly, the Examiner finds no basis to conclude that Applicant has clearly lexicographically redefined the term “IPD” for purposes of claim interpretation. To the contrary, paragraph 0069 and claim 25 even expressly identify “PCBs” as examples of suitable integrated passive devices. This disclosure is inconsistent with Applicant’s assertion that the specification unequivocally limits the claimed IPD in the manner now proposed. Where the original disclosure itself discloses broader examples falling within the scope of the term, the Examiner declines to adopt Applicant’s proposed narrow construction. Accordingly, Applicant has not demonstrated that the cited paragraphs constitute lexicography, and the Examiner maintains the interpretation applied in the rejection as within the broadest reasonable interpretation and consistent with Applicant’s specification. Accordingly, as also recited above, Chinnusamy teaches the claimed aspects of the instant invention. These arguments are considered to be similarly repeated for all 35 U.S.C. § 102 independent claim rejections reliant on Chinnusamy.
With regards to the claims, the applicant additionally argues:
CHANG is directed to metal bump sidewall protection techniques intended to prevent solder migration and improve package reliability. CHANG discloses forming dielectric protection layers along bump sidewalls using printing, coating, or lithographic processes. However, CHANG is entirely silent with respect to integrated passive devices, and further fails to disclose any functional electrical integration of passive circuit elements within a package. Importantly, CHANG does not disclose connection structures formed at wafer level that electrically interconnect a semiconductor device and an integrated passive device. The dielectric layers of CHANG serve a protective, non functional role and do not operate as electrical interconnects between distinct devices. Moreover, CHANG does not disclose a packaged device architecture in which a passive device is embedded as a constituent component of the package for circuit functionality.
MEYER fails to disclose, either expressly or inherently, the claimed packaged semiconductor device including an integrated passive device electrically connected to a semiconductor device by wafer level formed connection structures. MEYER is directed to semiconductor dies having on chip antennas and the formation of recesses or exposed epitaxial layers on an opposite surface of the die to improve RF radiation characteristics. While MEYER describes RF related structures and wafer level thinning
or etching techniques, MEYER does not disclose an integrated passive device forming part of a package, nor does MEYER disclose electrical connection structures formed at wafer level that interconnect bond pads of a semiconductor device to bond pads of an integrated passive device. NOORI discloses stacked RF packages employing integrated passive devices for impedance matching in RF amplifier applications. While NOORI generally describes stacking active dies and passive devices, NOORI does not disclose the claimed wafer level formed connection structures that electrically interconnect a semiconductor device and an integrated passive device as part of a package level fabrication process. NOORI does not disclose forming the electrical connection structures at wafer level as part of the packaged device itself, prior to singulation, nor embedding an integrated passive device using wafer level fabrication techniques as claimed.
Applicant further asserts that combination of CHANG, MEYER, and NOORI would not properly teach or suggest the claimed invention. MEYER addresses die level antenna performance through material removal, CHANG addresses bump reliability through protective coatings, and NOORI addresses RF circuit topology using stacked components. None of these references teaches or suggests forming electrical connection structures between a semiconductor device and an integrated passive device at wafer level, nor embedding an integrated passive device as a functional part of the package using wafer level fabrication.
In response to applicant's arguments against Chang, Meyer, and Noori, one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The applicant’s argument addresses Chang, Meyer, and Noori as individual references and does not rebut the combination of Chang in view of Meyer and Noori. All features recited in the claim, sparing the integrated passive device, are already taught by Chang (see paragraph 74-78 above). This includes features such as “package level interconnects”, which the Applicant recites Meyer fails to teach. Furthermore, features upon which applicant relies to argue Chang and Noori (e.g., “connection structures formed at wafer level that electrically interconnect a semiconductor device and an integrated passive device”, “wafer level formation of inter device connection structures”, “the electrical connection structures at wafer level as part of the packaged device itself, prior to singulation, “embedding an integrated passive device using wafer level fabrication techniques”) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). All limitations of claim 1, including interconnection structures 106/112 but sparing the integrated passive device limitation are met by Chang (see, e.g., fig. 18). The rejection for Chang in view of Meyer and Noori does not rely upon Chang, Meyer, or Noori individually disclosing every claimed feature. Rather, the rejection relies on the collective teachings of the references and the knowledge of one of ordinary skill in the art at the time of filing the invention, which Applicant fails to adequately rebut.
The fact that the references discuss different applications or particular design objectives does not preclude their combination. The relevant inquiry under 35 U.S.C. § 103 is not whether the references are directed to an identical problem addressed by Applicant, but whether their teachings would have suggested the claimed subject matter to one of ordinary skill in the art. Chang, Meyer, and Noori are all directed to semiconductor packaging and integration technologies involving semiconductor devices, package structures, and electrical interconnections. Accordingly, the references are reasonably pertinent to the same field of endeavor. In fact, Noori teaches each and every aspect of independent claim 1 by itself (see paragraphs 29, 31-33, 40, 46, and 51 above), further evincing the analogous nature of the references.
Furthermore, the rejection does not propose incorporating the specific antenna functionality of Meyer into Chang, nor does it propose incorporating the particular RF circuit implementation disclosed by Noori into Chang. Rather, Meyer is relied upon solely for its teaching that integrated passive devices may be implemented as semiconductor device suitable for incorporation within semiconductor package environments, whereas Noori is relied upon to further evidence motivation and incentive for the specific use of integrated passive devices in such environments, so as to realize various functional blocks within the package and expand the external applications of an overall device. These teachings are not limited to the particular end-use applications discussed in the individual references and would have been recognized by one of ordinary skill in the art as generally applicable to semiconductor packaging concepts.
One of ordinary skill in the art would have understood that the suitably of an integrated passive device for incorporation into a semiconductor package does not depend on whether the package is ultimately used for antenna applications, RF circuitry, or another electronic function. Rather, integrated passive devices were known package-level components capable of providing circuit functionality within semiconductor packages. Consequently, a skilled artisan would have recognized that the integrated passive device teaches of Meyer and Noori could be applied within the package architecture taught by Chang without changing the fundamentals of Chang’s package.
Applicant’s assertion that the references address different subject matter fails to account for the rationale set forth in the rejection. As explained in the rejection mailed on 02/18/2026, Meyer evidences that integrated passive devices were known equivalents to other device dies utilized in semiconductor packages, and Noori evidences that integrated passive devices could be employed in semiconductor packages to advantageously realize various functional blocks. In view of these teachings, one of ordinary skill in the art would have found it obvious to implement Chang’s packaged device using an integrated passive device because such substitution would have represented the predictable use of known prior-art elements according to their established functions and would have yielded the expected result of providing a suitable electronic component capable of hosting applicable circuitry and communicating with other electronic components. Furthermore, in view of these teachings, one of ordinary skill in the art would have had particular incentive employ an integrated passive device in the packaged device of Chang, so as to advantageously realize various functional blocks in the overall packaged device.
Applicant’s argument regarding electrical connection structures formed at wafer level is likewise unpersuasive. As discussed above, the “wafer level” arguments cited by Applicant are not recited in the claims, and features from the specification are not read into the claims. Furthermore, the rejection does not rely upon Meyer or Noori for teaching the package interconnection architecture or the claimed connection structures. Rather, Chang is relied upon for teaching the semiconductor package structure, including the connection structures and the arrangement of components within the package as recited in claim 1. Meyer and Noori are relied upon only for the additional teaching that integrated passive devices were known, suitable, and even desired package components capable of providing circuit functionality within semiconductor package environments. The proposed modification therefore substitutes a known integrated passive device into the package architecture already taught by Chang, while retaining Chang’s disclosed connection structure arrangement. Because the rejection relies upon Chang, not Meyer or Noori, for the claimed connection structure limitations, and because features the Applicant relies upon are not recited in the claims, Applicant’s criticism that Meyer and Noori do not disclose wafer-level interconnects is not persuasive.
The applicant’s focus solely on Chang, Meyer, and Noori as individual references constitutes an improper piecemeal analysis because it fails to address the combination and rationale Chang/Meyer/Noori actually relied upon in the rejection. In fact, Applicant has not provided any evidence or argument to address Examiner’s specific rationale regarding IPD incorporation for the rejection as cited in paragraphs 33-37 of the previous Office action mailed on 02/18/2026. Accordingly, the argument is unpersuasive.
Applicant’s other arguments with respect to the claims have been considered but are moot in view of the new and/or clarified grounds of rejection.
Conclusion
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/Shamita S. Hanumasagar/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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