Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments and Arguments
Applicant's arguments in “Applicant Arguments/Remarks Made in an Amendment” on 10/31/2025, regarding the Claim Objections of Claims 7, 8, and 11, and the 35 U.S.C. § 112(b) rejections of claims 1, 10, 13, 15, and 17 have been fully considered and are persuasive. The objections and rejections for the above have been withdrawn.
Claim objections for claim 7 and 8 was resolved by adding in the missing transitional phrase “wherein,” and claim 11’s issue of “includes has a” has been resolved by canceling the “has” portion.
By amending that “separated” is “separated by a predetermined distance,” the indefiniteness issue that claims 1, 10, and 15 had, because the connected portion and the mounting portion were not separated in ways such as electrically, the new language clears up the indefiniteness. Examiner also does see that there is support for this change in the originally filed disclosure in at least the figures.
Regarding Claim 13, the amendment does solve the antecedent issue that was presented in the previous Office Action, however, there still problems as to what the scope of what the members other than the crosslink member is. However, it is difficult to say that this rises to another issue of indefiniteness, and instead it is more reasonable, under broadest reasonable interpretation (BRI), that the only limitations that are explicitly claimed is that the crosslink member is covered by the sealing resin and that something/anything else is also covered by the sealing resin, so long as it can be called a "member." Currently, under the language of the claim, it is not reasonable to limit “plurality of members” to anything other than a least two things that can be called “member” where one of those “plurality of members” is the crosslink member.
Regarding the indefiniteness rejection of claim 17, the amendment adds and deletes various things from the claim to make the claim clear.
Applicant’s arguments with respect to claims 1 and 15, and their dependent claims with respect to the 35 U.S.C. § 103 have been considered but are moot because the new ground of rejection by Xue in view of new reference Otremba et al. (US 20180301398 A1; Otremba). Xue was used as a single reference obviousness rejection for claims 1 and 15, because at least in part, while Xue didn’t explicitly disclose covering two corners with the crosslink member, Xue does talk about altering the area in which the crosslink member covers the semiconductor elements in order to increase heat dissipation. Applicant argues on pages 17-21 in “Applicant Arguments/Remarks Made in an Amendment” dated 10/31/2025, that inter alia., the reason why it is important to specifically cover at least 2 adjacent corners of the semiconductor element, then at least one full side of the semiconductor element would be covered. Applicant points to the Specification where it says “Having the entire side of a semiconductor device 1A, 1B and at least portions of adjacent sides of the semiconductor device 1A, 1B may provide an advantage in heat diffusion.” This raises multiple possible problems if as the language of the claim does not require the crosslink member to be strictly rectangular in shape. Meaning that it possible to have a shape of the crosslink member that is wider than each of the semiconductor elements and covering two adjacent corners of the semiconductor element, while at the same time not covering any full side of the semiconductor element. An example shape would be a smaller square where each of the corners extend in an almost X shape. An example for illustrative purposes only would see the cross shape that the AM4 Mounting bracket is below.
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Figure 1: Example of a shape of the crosslink member.
The above example is only to show an example shape and not one that is being used to reject the art. This example shape is used to prove a point that by having the corners covered, there is not necessarily a guarantee that a full side of the semiconductor element will need to be covered even if two adjacent corners are covered. Furthermore, applicant makes an assertion that having a full side covered may improve heat dissipation. While examiner agrees that having more coverage of the semiconductor element should improve heat dissipation, there is nothing in the context of the claim requiring this larger than normal coverage and/or full side coverage.
However, without forgoing the original single reference obviousness rejection based on Xue, Examiner will instead use a new ground of rejection by Xue in view of Otremba in order to more clearly make the obviousness of having the corners of the semiconductor element covered by the crosslink member from the prior art.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 21 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The Phrase “the plurality of semiconductor elements are adapted to the plurality of mounting portions” is indefinite because it is unclear whether the plurality of semiconductor elements muse be specially designed (structural limitation) to fit the mounting portions, or if any reasonable similar semiconductor element is capable of being mounted to the mounting portions. If the prior art shows a semiconductor element that is able to be mounted to generic mounting portions, it is unclear if the claim covers the prior art. “Adapted to” can mean “made to,” “designed to,” or “capable of,” Making it vague if not supported by the specification, which Examiner has failed to find said support. This is the reason for the 35 U.S.C. 112(b) rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-13, 20, and 23 are rejected under 35 U.S.C. 103 as being unpatentable as obvious by United States Patent Application Publication by Xue et al (US 20140361419 A1; Xue) in view of United States Patent Application Publication by Otremba et al. (US 20180301398 A1; Otremba).
Regarding Claim 1, Xue discloses a semiconductor package (10) comprising:
a plurality of semiconductor elements (11/12/101/102);
a lead frame (Abstract “A power semiconductor device comprises a lead frame unit”) having
a mounting portion (110/110-1/110-2) to which a first surface of at least one of the pluralities of semiconductor elements is connected (Fig. 2b, where the bottom [first surface] of the semiconductor elements 101 and 102 are mounted to the mounting portion 110), and
a connected portion (111/112) separated from the mounting portion (Figs. 3C, 4B, 5B, 6, 7, where the connection portions 111 and 112 are separated by a predetermined distance from mounting portions 110, 110-1, and 110-2);
a crosslinked member (211, 212, 2110, 2120, 250) connected to a second surface of the at least one of the plurality of semiconductor elements and the connected portion (Fig. 2E, where clip 212/211 are connected to the top [second surface] of the semiconductor elements 101/102 and connecting portions 111/112 respectively), such that the crosslinked member electrically connects the at least one of the plurality of semiconductor elements and the connected portion, the second surface located on a side opposite to the first surface (Para. 26, “The first metal clip 211 and the second metal clip 212 are bridge-type clips able to attach on the dies and the pins located on the planes with different heights.”); and
a sealing resin being electrically insulated, the sealing resin covering a portion of the lead frame, the plurality of semiconductor elements, and the crosslinked member (Para. 27, where sealing resin covers the above but is not shown in figures), wherein
at least one of the plurality of semiconductor elements is different from another one of the plurality of semiconductor elements in element size or power consumption during drive of the semiconductor package (In all figures, they appear to be different size, Furthermore in Para. 23 “As shown in FIG. 2C, the first die 101 is a high-side P-type channel MOSFET, the second die 102 is a low-side N-type channel MOSFET”),
each of the plurality of semiconductor elements is a rectangular plate (all figures show the semiconductor elements to be rectangular in plain view and plate like in side view), and
the crosslinked member has a larger width than each of the plurality of semiconductor elements (In all of the figures, the crosslinked members 211, 212, 2110, 2120, 250, are wider [up down] then their respective die’s they are disposed over).
Xue teaches all aspects of claim; however, Xue is silent with respect to the limitation of the crosslinked member covering at least two adjacent corner portions of at least one of the plurality of semiconductor elements.
In a similar field of endeavor, Otremba discloses semiconductor device including a lead frame (21), A semiconductor element (1) that is rectangle in shape, and a crosslinked member (23 - clip) over at least two adjacent corner portions of the plurality of semiconductor elements.
In view of the disclosure of Otremba, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Otremba to Xue at the time the instant application was filed to incorporate having the crosslink member cover at least two adjacent corner portions of the semiconductor element. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages having the crosslink member extend over the edge (including at least wo adjacent corners) of the semiconductor element have in regard to increased heat dissipation. (Otremba: Heat dissipation in Para. 57, Embodiment/layout in Para 48, and Figs 1, 3, and 5)
Regarding Claim 2, Xue and Otremba discloses the semiconductor package according to Claim 1, and further wherein the plurality of semiconductor elements are electrically connected through at least one of the mounting portion (Xue: Para. 22-26, Figs. 2-6, where the plurality of semiconductor elements 101 and 102 are connected to mounting portion 110) or the crosslinked member (Xue: Para. 39 “The second parts 250c and 250e of the metal clip 250 which are mounted on the first electrode 101a of the first die 101 and the first electrode 102a of the second die 102”, Figs. 7- 11)
Regarding Claim 3, Xue and Otremba discloses the semiconductor package according to Claim 1, wherein
the at least one of the plurality of semiconductor elements includes two of the plurality of semiconductor elements (Xue: All packages include at least two of semiconductor elements (11/12/13/101/102/103),
the sealing resin covers the two of the plurality of semiconductor elements (Xue: Para. 27, “plastic package materials, such as epoxy resin and the like, is deposited to form a plastic package body 225 for encapsulating the lead frame unit, the first die 101 and the second die 102”),
the two of the plurality of semiconductor elements are transistors (Xue: Para. 23, “As shown in FIG. 2C, the first die 101 is a high-side P-type channel MOSFET, the second die 102 is a low-side N-type channel MOSFET”, further semiconductor elements in alternate embodiments are also MOSFET dies, found in Para. 36, 44, and 50. [MOSFET’s are a type of transistor]), and
the two of the plurality of semiconductor elements are included in a half-bridge circuit in which the two of the plurality of semiconductor elements are connected in series through the mounting portion (Xue: Para. 22-26, Figs. 2-6, where the plurality of semiconductor elements 101 and 102 are connected to mounting portion 110) or the crosslinked member (Xue: Para. 39” which are mounted on the first electrode 101a of the first die 101 and the first electrode 102a of the second die 102”, Figs. 7- 11) (because the semiconductor elements are connected in series and use a DC-DC power supply. It can be considered a half bridge circuit.)
Regarding Claim 4, Xue and Otremba discloses the semiconductor package according to Claim 3, and further wherein
the mounting portion of the lead frame includes two mounting portions separated from each other (Xue: Para. 37, Fig. 7B/7C, where the lead-frame mounting portions 110-1 and 110-2 are physically separated from each other),
the two of the plurality of semiconductor elements respectively mount on the two mounting portions (Xue: Para. 38, “The first die 101 is attached on the top surface of the first die paddle 110-1 and the second die 102 is attached on the top surface of the second die paddle 110-2”),
each of the two of the plurality of semiconductor elements has a drain electrode at the first surface, and has a source electrode and a gate electrode at the second surface (Xue: Para. 44, lines 4-12), and
one of the two of the plurality of semiconductor elements is a high-side n-channel transistor, and another one of the two of the plurality of semiconductor elements is a low-side n-channel transistor (Xue: Para. 23, “As shown in FIG. 2C, the first die 101 is a high-side P-type channel MOSFET, the second die 102 is a low-side N-type channel MOSFET”, and same is true for other embodiments with semiconductor elements 101 and 102).
Regarding Claim 5, Xue and Otremba discloses the semiconductor package according to Claim 3, wherein
the mounting portion is a single mounting portion on which the two of the plurality of semiconductor elements mount (Xue: Para. 22-26, Figs. 2-6, where the plurality of semiconductor elements 101 and 102 are connected to a single mounting portion 110), and
each of the two of the plurality of semiconductor elements has a drain electrode at the first surface, and has a source electrode and a gate electrode at the second surface (Xue: Para. 23), and
one of the two of the plurality of semiconductor elements is a high-side p-channel transistor, and another one of the two of the plurality of semiconductor elements is a low-side n-channel transistor (Xue: Para. 23, “As shown in FIG. 2C, the first die 101 is a high-side P-type channel MOSFET, the second die 102 is a low-side N-type channel MOSFET”, and same is true for other embodiments with semiconductor elements 101 and 102).
Regarding Claim 6, Xue and Otremba discloses the semiconductor package according to Claim 3, wherein
the mounting portion of the lead frame includes two mounting portions separated from each other (Xue: Para. 37, Fig. 7B/7C, where the lead-frame mounting portions 110-1 and 110-2 are physically separated from each other),
the two of the plurality of semiconductor elements respectively mount on the two mounting portions (Xue: Para. 38, “The first die 101 is attached on the top surface of the first die paddle 110-1 and the second die 102 is attached on the top surface of the second die paddle 110-2”), while the crosslinked member as a common member is connected to the two of the plurality of semiconductor elements (Xue: Para. 39 “The second parts 250c and 250e of the metal clip 250 which are mounted on the first electrode 101a of the first die 101 and the first electrode 102a of the second die 102”, Figs. 7- 11),
each of the two of the plurality of semiconductor elements has a drain electrode at the first surface, and has a source electrode and a gate electrode at the second surface (Xue: Para. 44, lines 4-12), and
one of the two of the plurality of semiconductor elements is a high-side n-channel transistor, and another one of the two of the plurality of semiconductor elements is a low-side p-channel transistor (Xue: Para. 23, “As shown in FIG. 2C, the first die 101 is a high-side P-type channel MOSFET, the second die 102 is a low-side N-type channel MOSFET”, and same is true for other embodiments with semiconductor elements 101 and 102).
Regarding Claim 7, Xue and Otremba discloses the semiconductor package according to Claim 3, and further wherein
the mounting portion of the lead frame includes two mounting portions separated from each other (Xue: Para. 37, Fig. 7B/7C, where the lead-frame mounting portions 110-1 and 110-2 are physically separated from each other),
the two of the plurality of semiconductor elements respectively mount on the two mounting portions (Xue: Para. 38, “The first die 101 is attached on the top surface of the first die paddle 110-1 and the second die 102 is attached on the top surface of the second die paddle 110-2”),
each of the two of the plurality of semiconductor elements has a source electrode and a gate electrode at the first surface, and has a drain electrode at the second surface (Xue: Para. 44, lines 4-12), and
one of the two of the plurality of semiconductor elements is a high-side n-channel transistor, and another one of the two of the plurality of semiconductor elements is a low-side n-channel transistor (Xue: Para. 23, “As shown in FIG. 2C, the first die 101 is a high-side P-type channel MOSFET, the second die 102 is a low-side N-type channel MOSFET”, and same is true for other embodiments with semiconductor elements 101 and 102).
Regarding Claim 8, Xue and Otremba discloses the semiconductor package according to Claim 3, and further wherein
the mounting portion of the lead frame includes two mounting portions separated from each other (Xue: Para. 37, Fig. 7B/7C, where the lead-frame mounting portions 110-1 and 110-2 are physically separated from each other),
the two of the plurality of semiconductor elements respectively mount on the two mounting portions (Xue: Para. 38, “The first die 101 is attached on the top surface of the first die paddle 110-1 and the second die 102 is attached on the top surface of the second die paddle 110-2”), while the crosslinked member as a common member is connected to the two of the plurality of semiconductor elements (Xue: Para. 39 “The second parts 250c and 250e of the metal clip 250 which are mounted on the first electrode 101a of the first die 101 and the first electrode 102a of the second die 102”, Figs. 7- 11),
each of the two of the plurality of semiconductor elements has a source electrode and a gate electrode at the first surface, and has a drain electrode at the second surface (Xue: Para. 44, lines 4-12), and
one of the two of the plurality of semiconductor elements is a high-side p-channel transistor, and another one of the two of the plurality of semiconductor elements is a low-side n-channel transistor (Xue: Para. 23, “As shown in FIG. 2C, the first die 101 is a high-side P-type channel MOSFET, the second die 102 is a low-side N-type channel MOSFET”, and same is true for other embodiments with semiconductor elements 101 and 102).
Regarding Claim 9, Xue and Otremba discloses the semiconductor package according to Claim 3, wherein
the mounting portion is a single mounting portion on which the two of the plurality of semiconductor elements mount (Xue: Para. 22-26, Figs. 2-6, where the plurality of semiconductor elements 101 and 102 are connected to a single mounting portion 110),
each of the two of the plurality of semiconductor elements has a source electrode and a gate electrode at the first surface, and has a drain electrode at the second surface (Xue: Para. 23), and
one of the two of the plurality of semiconductor elements is a high-side n-channel transistor, and another one of the two of the plurality of semiconductor elements is a low-side p-channel transistor (Xue: Para. 38, “The first die 101 is attached on the top surface of the first die paddle 110-1 and the second die 102 is attached on the top surface of the second die paddle 110-2”).
Regarding Claim 10, Xue discloses a semiconductor package (10) comprising:
a semiconductor element (101) having a first surface (Bottom of semiconductor element 101 in Fig. 2E) and a second surface located on a side opposite to the first surface (Top of semiconductor element 101 in Fig. 2E), the semiconductor element being a rectangular plate (Fig. 2B shows the semiconductor element 101 to be rectangular in plan view and Fig. 2E shows semiconductor element 101 to be plate shape);
a lead frame (Abstract “A power semiconductor device comprises a lead frame unit”) having
a mounting portion (110) on which the semiconductor element mounts, the mounting portion connected to the first surface of the semiconductor element (Fig. 2b, where the bottom [first surface] of the semiconductor elements 101 is mounted to the mounting portion 110), and
a connected portion (111) separated by a predetermined distance from the mounting portion (Figs. 2D and 2E, where the connection portion 111 is physically separated from mounting portions 110);
a crosslinked (211) member connected to the second surface of the semiconductor element and the connected portion to electrically connect the semiconductor element and the connected portion (Fig. 2E, where crosslink member 211 is connected to the top [second surface] of the semiconductor elements 101 and connecting portion 111 respectively); and
a sealing resin being electrically insulated, the sealing resin covering a portion of the lead frame, the semiconductor element, and the crosslinked member (Para. 27),
wherein the crosslinked member has a larger width than the semiconductor element (Fig. 2D, the crosslinked member 211 is wider [up down in figure] than the die it is disposed over).
Xue teaches all aspects of claim; however, Xue is silent with respect to the limitation of the crosslinked member covering at least two adjacent corner portions of at least one of the plurality of semiconductor elements.
In a similar field of endeavor, Otremba discloses semiconductor device including a lead frame (21), A semiconductor element (1) that is rectangle in shape, and a crosslinked member (23 - clip) over at least two adjacent corner portions of the plurality of semiconductor elements.
In view of the disclosure of Otremba, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Otremba to Xue at the time the instant application was filed to incorporate having the crosslink member cover at least two adjacent corner portions of the semiconductor element. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages having the crosslink member extend over the edge (including at least wo adjacent corners) of the semiconductor element have in regard to increased heat dissipation. (Otremba: Heat dissipation in Para. 57, Embodiment/layout in Para 48, and Figs 1, 3, and 5)
Regarding Claim 11, Xue and Otremba discloses the semiconductor package according to Claim 1, wherein
the sealing resin includes a side surface in a thickness direction of the mounting portion as one of a plurality of outer surfaces of the sealing resin (Xue: Para. 27, and Fig. 4C, where the resin top is shown to have thickness direction at least covering the semiconductor elements and parts of the crosslink member), and
a portion of the crosslinked member is exposed to outside of the sealing resin at the side surface of the sealing resin (Xue: Para. 30, “the first metal clip 211 (or the second metal clip 212) is often encapsulated by the plastic package body 225. In this embodiment, the top surfaces of the first part 2110b and the first part 2120b of the first and second metal clips 2110 and 2120 respectively are completely flat so they can be exposed from the top surface of the plastic package body 225 as shown in FIG. 4C that is a top view of the device package”).
Regarding Claim 12, Xue and Otremba discloses the semiconductor package according to Claim 1, but fails to explicitly disclose wherein the at least one of the plurality of semiconductor elements is connected to an external power supply having a voltage of 60 volts or lower, such that at least one of the plurality of semiconductor elements is driven by the voltage of 60 volts or lower through the external power supply.
However, integrating the semiconductor element and the power supply would merely be a matter of obvious engineering choice (In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965)).
Regarding Claim 13, Xue and Otremba discloses the semiconductor package according to Claim 1, and further wherein
a surface of the mounting portion on which at least one of the plurality of semiconductor elements mounts is defined as a mounting surface (Xue: top surface of 110),
the crosslinked member is one of a plurality of members,
the sealing resin covers the plurality of members (Xue: Para. 27, “the top surface of the first die 101, the second die 102, the control dies 103, the first metal clip 211, the second metal clip 212, and the metal bumps 201 are all completely encapsulated by the plastic package body 225”),
a distance from a top of each of the plurality of members to the mounting surface in a direction normal to the mounting surface is defined as a height of each of the plurality of members, and
the crosslinked member has a largest height among the plurality of members covered by the sealing resin (Fig. 2e, where the crosslink member has the greatest height overall in the device. Or fig 4C. where the crosslink member is higher than the resin).
Regarding Claim 20, Xue and Otremba discloses the semiconductor package according to Claim 1, and further wherein each of the plurality of semiconductor elements has a drain electrode on the first surface, and has a source electrode and a gate electrode on the second surface (Xue: Para. 44, lines 4-12),
the gate electrode is exposed from the crosslinked member (Xue, as the Gate electrode is on the side opposite the crosslink member, it would be reasonable to say that the gate electrode is at least physically exposed from the crosslink member.
Xue, does not explicitly disclose that the crosslinked member completely covers the source electrode 101a. However, the combination of reference of Otremba and Xue would result in the entirety of the semiconductor elements first side (source electrode side), with the crosslink member and thus the entirety of the source electrode of Xue would completely cover the source electrode.
Regarding Claim 23, Xue and Otremba discloses the semiconductor package according to Claim 1, and further wherein the at least one of the plurality of semiconductor elements includes at least first, second, and third sides, the second side being adjacent to the first side, and the third side being adjacent to the first side (Xue: Where the first side would be the side that is towards the elongated direction of the crosslink member),
the crosslinked member entirely covers the first side of the semiconductor element, and
the crosslinked member at least partially covers the second and third sides of the semiconductor element (Xue alone does not explicitly disclose that the crosslinked member entirely covers the first side of the semiconductor element and partially over the second and third sides. However, the combination of reference of Otremba and Xue would result in the entirety of the first side of the semiconductor elements being completely covered as well with at least partially covering the second and third sides of the semiconductor element).
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable as obvious by Xue in view of Otremba and further in view of Internation Application publication by Huang et al. (WO 2016082138 A1)
Regarding Claim 14, Xue and Otremba disclose the semiconductor package according to Claim 1, and further wherein the sealing resin has a surface layer portion covering at least the crosslinked member (Xue: Para. 27), but fails to explicitly disclose where thermal conductivity of the surface layer portion is equal to 2.2 watts per meter-kelvin or larger.
Huang teaches of sealing resins with high thermal conductivity and electrically insulating (Xue: Para. 41 “The cured polymer material has high thermal conductivity as well as good insulative properties. The in-plane thermal conductivity of the cured thermoset is 8 ‘watts per meter-kelvin’ or more, preferably 10 ‘watts per meter-kelvin’ more”)
Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a known high thermally conductive and still insulating sealing resin, as shown by Huang, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose high thermally conductive and still insulating sealing resin over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer.
Claims 15-18, and 22 are rejected under 35 U.S.C. 103 as being unpatentable as obvious by Xue in view Otremba and further in view of United States Patent Application Publication by Yoshioka et al. (US 20200126896 A1; Yoshioka)
Regarding Claim 15, Xue discloses an electronic device comprising:
a semiconductor package (10) including
a plurality of semiconductor elements (11/12/13/101/102/103) being different in element size or power consumption during drive of the semiconductor package (In all figures, they appear to be different size, Furthermore in Para. 23 “As shown in FIG. 2C, the first die 101 is a high-side P-type channel MOSFET, the second die 102 is a low-side N-type channel MOSFET”),
a lead frame (Abstract “A power semiconductor device comprises a lead frame unit”) having,
a mounting portion (110/110-1/110-2) to which a first surface of at least one of the plurality of semiconductor elements is connected (Fig. 2b, where the bottom [first surface] of the semiconductor elements 101 and 102 are mounted to the mounting portion 110), and
a connected portion (111/112) separated by a predetermined distance from the mounting portion (Figs. 3C, 4B, 5B, 6, 7, where the connection portions 111 and 112 are separated from mounting portions 110, 110-1, and 110-2);
a crosslinked member (211, 212, 2110, 2120, 250) connected to a second surface of the at least one of the plurality of semiconductor elements and the connected portion (Fig. 2E, where clip 212/211 are connected to the top [second surface] of the semiconductor elements 101/102 and connecting portions 111/112 respectively), such that the crosslinked member electrically connects the at least one of the plurality of semiconductor elements and the connected portion, the second surface located on a side opposite to the first surface (Para. 26, “The first metal clip 211 and the second metal clip 212 are bridge-type clips able to attach on the dies and the pins located on the planes with different heights”); and
a sealing resin being electrically insulated, the sealing resin covering a portion of the lead frame, the plurality of semiconductor elements, and the crosslinked member (Para. 27, where sealing resin covers the above but is not shown in figures); wherein
each of the plurality of semiconductor elements is a rectangular plate (all figures show the semiconductor elements to be rectangular in plain view and plate like in side view), and
the crosslinked member has a larger width than each of the plurality of semiconductor elements (In all of the figures, the crosslinked members 211, 212, 2110, 2120, 250, are wider [up down] then their respective die’s they are disposed over).
Xue teaches the above aspects of claim; however, Xue is silent with respect to the limitation of the crosslinked member covering at least two adjacent corner portions of at least one of the plurality of semiconductor elements.
In a similar field of endeavor, Otremba discloses semiconductor device including a lead frame (21), A semiconductor element (1) that is rectangle in shape, and a crosslinked member (23 - clip) over at least two adjacent corner portions of the plurality of semiconductor elements.
In view of the disclosure of Otremba, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Otremba to Xue at the time the instant application was filed to incorporate having the crosslink member cover at least two adjacent corner portions of the semiconductor element. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages having the crosslink member extend over the edge (including at least wo adjacent corners) of the semiconductor element have in regard to increased heat dissipation. (Otremba: Heat dissipation in Para. 57, Embodiment/layout in Para 48, and Figs 1, 3, and 5)
Xue is also silent with respect to the circuit board, the heat radiation member, and the heat radiation layer.
In a similar field of endeavor Yoshioka discloses a multi-chip (semiconductor element) package that has a circuit board (Yoshioka: 12) on which the semiconductor package mounts;
a heat radiation member (Yoshioka: 13) disposed on a side opposite to the circuit board to sandwich the semiconductor package (Yoshioka: 1 or 101) between the heat radiation member and the circuit board (Yoshioka: Fig. 8, where the circuit board 12, is disposed on one side of the package 101 and the heat radiation member 13 is disposed on the other), such that the heat radiation member diffuses heat to outside; and
a heat radiation layer (Yoshioka: 19) disposed at a top surface of the sealing resin facing the heat radiation member, the top surface being a surface of the sealing resin on a side covering the crosslinked member, a gap between the semiconductor package and the heat radiation member being filled with the heat radiation layer (Yoshioka: Para. 93, Where heat radiation layer 19 is disposed between top of resin from the package and the bottom of the heat radiation member, and is for both electrical and thermal conductivity).
In view of the disclosure of Yoshioka, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Yoshioka to Xue at the time the instant application was filed to incorporate further adding a thermal cover, circuit board, and heat radiation layer to the package of Xue, further improving the package and/or using the package in devices. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that structures added to the package “enabling improvements in exhaust heat performance of the semiconductor package and the module to be achieved” (Yoshioka: Para. 20).
Regarding Claim 16, Xue, Otremba, and Yoshioka discloses the electronic device according to Claim 15, and further wherein
the semiconductor package includes a plurality of semiconductor packages, and
the heat radiation member covers the plurality of semiconductor packages (Yoshioka: Fig. 11, where multiple packages are on the single circuit board and under the same heat radiation member).
Regarding Claim 17, Xue, Otremba, and Yoshioka discloses the electronic device according to Claim 15, wherein
the semiconductor package and a plurality of electronic components mount on the circuit board (Yoshioka: Para. 6, “plurality of semiconductor packages that are each mounted to a module circuit board”),
a height of each of the plurality of electronic components is defined as a distance from a top of each of the plurality of electronic components to the circuit board,
a height of the semiconductor package is defined as a distance from a top of the semiconductor package to the circuit board (In Xue and Yoshioka, the sealing resin forms the shape of the package body from the top of the resin to the bottom, the whole package is within. In Yoshida: Para. 51, “The molded member 9 forms an external shape of the package main body 2. An upper surface 2a, a bottom surface 2b, and side surfaces 2c of the package main body 2 are thereby formed on the molded member 9”. In Xue: Para. 27 and Fig. 2H, where the resin is at the bottom of the device and the top), and
the height of the semiconductor package is larger than the height of each of the plurality of electronic components (Yoshioka: Fig. 11, Where the height of the package appears larger than the semiconductor components).
Regarding Claim 18, Xue, Otremba, and Yoshioka discloses the electronic device according to Claim 15, wherein
a bottom surface of the sealing resin on a side opposite to the top surface is joined to the circuit board in the semiconductor package (Yoshioka: Para. 59, “In addition, each of the semiconductor packages 1 is mounted to the module circuit board 12 in a state in which the die pad 3 is connected to the ground terminals 14 by means of the electrically conductive connecting members 17”, and Fig. 11, where it is the “bottom surface” of the package 1 mounted on the circuit board), and
the heat radiation member has larger thermal conductivity than the circuit board. It is well known that circuit boards have low thermal conductivity (Yoshioka: Para. 16) and one of the reasons that Yoshioka uses the heat radiation member, and the heat radiation layer is to overcome this bad thermal conductivity of the circuit board. Because of this Yoshioka makes sure to use a heat radiation member with comparatively good thermal conductivity to the circuit board (Para. 68-69)
Regarding Claim 22, Xue, Otremba, and Yoshioka electronic device according to Claim 15, and further wherein the heat radiation layer entirely covers the top surface of the sealing resin (Yoshioka: Para. 69, and Fig. 10, where the heat radiation layer 13 is disposed over the entire device including the sealing resin).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable as obvious by Xue in view Otremba and further in view of United States Patent Application Publication by Kobayashi et al. (US 20170301633 A1; Kobayashi)
Regarding Claim 19, Xue and Otremba disclose the semiconductor package according to Claim 1.
However, Xue fails to explicitly disclose wherein a distance between a top surface of the sealing resin and a top surface of the crosslinked member is 0.6 millimeter or shorter in a thickness direction of the sealing resin.
In a similar field of endeavor, Kobayashi discloses a semiconductor device, including a lead frame (331-335) and a semiconductor element (302a/b) and crosslink member (341 – substrate - heat dissipation surfaces, this can reasonably be considered a crosslink member as both provide the same function of providing electrical connections and structural support) and sealing resin (304) over the semiconductor elements and the crosslink member. Kobayashi further discloses that a distance between a top surface of the sealing resin and a top surface of the crosslinked member is 0.6 millimeter or shorter in a thickness direction of the sealing resin (Kobayashi: Para. 40, “A thickness 305 (see FIG. 3(a)) of the sealing resin covering the heat dissipation surfaces is preferably 0.5 [mm] or less, more preferably 0.3 [mm] or less from the viewpoint of heat dissipation property”)
In view of the disclosure of Kobayashi, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Kobayashi to Otremba and Xue at the time the instant application was filed to incorporate having relatively small distance from the top of the crosslink member to the top of the sealing resin. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages using the sealing resin to still secure components but not overly harm the heat dissipation properties of the rest of the structure by having too much resin (Kobayashi: Para. 40, “When the thickness 305 of the heat dissipation resin 304 is formed in the aforementioned manner, the insulation property can be secured without impairing the heat dissipation property”).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899