DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 04/27/2026, with respect to Rejections under 35 USC 103 have been fully considered and are persuasive, the amendments made overcome the prior art rejection previously made as written. The Rejections under 35 USC 103 has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made incorporating US 20160111539 A1 Nayak, US 20170062613 A1 Sung, US 20200035820 A1 Zhang et al hereafter “Zhang”, and US 5963824 A Krivokapic hereafter “Krivokapic”.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Applicant's Specific arguments filed 04/27/2026 have been fully considered but they are not persuasive. For claim 1 Applicant argues in part that Qi expressly teaches away from the newly claim germanium content and that Nayak does not resolve the deficiency. The examiner respectfully disagrees. A prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention, the prior art’s mere disclosure of more than one alternative does not constitute a teaching away from any of these alternatives because such disclosure does not criticize, discredit, or otherwise discourage the solution claimed [See MPEP 2141] and Nayak sufficiently discloses that a germanium content maybe adjusted or changed in a layer comprising Si or SiGe to improve the carrier mobility, Stress and/or Strain as shown below and illustrated in fig. 1. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
The applicant also in part argues that Ge is not a dopant in SiGe. This argument is moot as regardless of whether or not one considered Ge a dopant, SiGe (Silicon germanium) still comprises Silicon as claimed, and as shown in Nayak the relative germanium content maybe modified to achieve the desired stress/strain relationship. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
The applicant also argues in part that it is unclear how Potera’s p-type channel region is sandwiched between the source region and the drain region, The examiner does not rely on Potera to meet that limitation, the examiner expressly relies on Potera to achieve the wavy structure. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In addition, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, are rejected under 35 U.S.C. 103 as being unpatentable over US 20160104799 A1 Qi et al hereafter “Qi” in view of US 6218895 B1 De et al hereafter “De” and US 20160111539 A1 Nayak hereafter “Nayak”.
Claim 1 Qi teaches a semiconductor device, comprising:
a substrate (303 and/or 301 fig. 10);
a semiconductor fin structure (comprising at least 501, 505, 1001,1003, 805, 405, 411. 703 and/or 403 fig. 10) over the substrate and extending lengthwise along a direction (left to right of fig. 10), the semiconductor fin structure including a middle section (505, 1003, 411, and 805 fig. 10) adjacent to a first end section (501, 405, 1001, 703, and 403 fig. 10);
a gate structure (replacement metal gate RMG 1007 fig. 10) wrapping over a channel region (505/411 and 805 fig. 10) of the middle section; and
a first source/drain feature (left/right 1003 fig. 10) and a second source/drain feature (right/left 1003 fig. 10, respective to the first source/drain feature) sandwiching the channel region of the middle section along the direction [met under broadest reasonable interpretation 1003 sandwich a middle section of 505/411 and 805],
wherein the middle section comprises a first semiconductor material (compressive strained SiGe Paragraph 0028) and the first end section comprise a second semiconductor material (tensile strained Si Paragraph 0028) different from the first semiconductor material [the scope of the embodiment tensile strained Si and is different than the scope of the embodiment of compressively strained SiGe meets the limitation with sufficiently specificity See MPEP 2131.03].
Qi does not explicitly illustrate the fin structure including the middle section sandwiched between the first end section and a second end section along the direction, the second end section comprise a second semiconductor material different from the first semiconductor material, Nor a germanium content of the first semiconductor material is smaller than a germanium content of the second semiconductor material
De teaches a middle section (PMOS fig. 12) sandwiched between a first end section (left/right NMOS fig. 12) and a second end section (right/left NMOS fig. 12 respective to the first end section) along a direction (left to right of fig. 12) of a fin (comprising at least NMOS and PMOS and P-Substrate fig. 12) the second end section comprise a second semiconductor material (P-well semiconductor material fig. 12 sufficiently illustrated) different from a first semiconductor material (N-Well semiconductor material fig. 12 sufficiently illustrated); and three gates (G fig. 12) wrapped around a channel regions (sufficiently illustrated at the locations of B fig. 12) of the middle section, the first end section and the second end section.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the first end section of Qi in view of the device of De and/or combine the device of Qi with the device of De such that --the fin structure including the middle section sandwiched between the first end section and a second end section along the direction, the second end section comprise a second semiconductor material different from the first semiconductor material-- as duplication of parts is prima facie type obviousness [2144.04 VI B.] and/or substituting equivalents known for the same purpose is prima facie type obviousness [See 2144.06] in this case substituting the NMOS and PMOS transistors of De with the NMOS and PMOS transistors of Qi to form the device of De and/or to necessarily form a NFET-PFET Array comprising the device of Qi.
Nayak teaches a SiGe as an alternative material to Si (“channel Si or SiGe fig. 1). Nayak further teaches that the relative Ge concentration with the SiGe layers directly affects the stress and/or strain of the layer, wherein a relatively low Ge content forms a layer under Tensile stress/strain (130 Tensile fig. 1) and a relatively high Ge concentration forms a layer under Compressive stress/strain (230 Compressive fig. 2) [Sufficiently illustrated fig. 1 and 2 in “Y<X” “Tensile” and “Z>X” compressive when referring to the relative Ge content].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Qi in view of De in further view of Nayak such that “a germanium content of the first semiconductor material is smaller than a germanium content of the second semiconductor material”.
A person of ordinary skill in the art would have been motivated to make this modification as a part of routine optimization of the known resultant variables of relative stress and/or strain of the layers, and/or electron/hole mobility of the layers [See MPEP 2144.05II].
Claim 2 Qi in view of De and Nayak teaches as shown above the semiconductor device of claim 1, wherein the first end section and the second end section exert a compressive stress (Paragraph 0028 explicitly discloses 505 as “compressive strained SiGe fin”) on the middle section along the direction [Qi disclosed 501 as being a “tensile strained Si” Paragraph 0028 in view of MPEP 2112.01 Qi meets the limitation --the first end section exerts a compressive stress on the middle section along the direction-- under MPEP 2112.01 wherein the structure of a compressively strained/stressed middle section adjacent to a first end section the same as the disclosed and/or claimed structure and/or composition, and the presumed property [under MPEP 2112.01] is that the end section exerts the compressive stress/strain and/or Broadest reasonable interpretation, in view of modification in view of De as shown above --the second end section exert a compressive stress on the middle section along the direction-- is met as well for the same rational as the first end section].
Claim 3 Qi in view of De and Nayak teaches as shown above the semiconductor device of claim 2,
wherein the first semiconductor material comprises silicon (Si) [SiGe paragraph 0028, under broadest reasonable interpretation the first semiconductor material SiGe (Silicon Germanium) comprises Silicon]; wherein the second semiconductor material comprises silicon germanium (SiGe) [Met in view of the modification of Nayak to adjust a germanium content within a Si or SiGe layer as shown above].
Claim 4 Qi in view of De and Nayak teaches as shown above the semiconductor device of claim 3, where the second semiconductor material comprises a germanium content between about 40% and about 95% [met with sufficient specificity in view of Nayak wherein Nayak discloses with an embodiment wherein the germanium content is between 0%-50% to achieve a tensile strain/stress and/or 50%-100% to achieve compressive strain/stress which sufficiently overlaps with 40%-95%, Paragraph 0005 “x=0.5” in view of fig. 2 “y<x” and/or “z>y” [See MPEP 2131.03].
Claims 10 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over US Qi in further view of Di and US 20170062613 A1 Sung et al hereafter “Sung”.
Claim 10 Qi teaches A semiconductor structure, comprising:
a substrate (303 and 301 fig. 10) of a first semiconductor material (SiGe Paragraph 0027);
a fin structure over the substrate (comprising at least 501, 405, 1001, 703, 403, 505, 411, 1003, 605 fig. 10), the fin structure comprising:
a middle section (comprising 505, 411, 1003, and 605 fig. 10) formed of the first semiconductor material (SiGe sufficiently disclosed Paragraph 0028 “compressive strained SiGe Fins 505”), and
a first end section (comprising 501, 405, 1001, 803, and 403 fig. 10) adjacent the middle section along a direction (left to right of fig. 10) and formed of a second semiconductor material (“tensile strained Si fins 501” Paragraph 0028) different from the first semiconductor material [met with sufficiently specify the scope of the embodiment of tensile strained Silicon is different than the scope of the embodiment of SiGe];
a first gate structure (1007 fig. 10) wrapping over a channel region (comprising middle 411 and 805 fig. 10) of the middle section;
a second gate structure (1005 fig. 10) wrapping over the first end section; and
a first source/drain feature (comprising left/right 1003 and a corresponding left/right 411 fig. 10 met under broadest reasonable interpretation) and a second source/drain feature (comprising right/left 1003 and a corresponding right/left 411 fig. 10 respective to the first source/drain feature) sandwiching the channel region of the middle section along the direction [met under broadest reasonable interpretation it at least sandwiches a portion of the channel region comprising 411 and 805 fig. 10].
Qi does not teach a second end section; wherein the first end section and the second end section sandwiching the middle section along the direction and formed of a second semiconductor material different from the first semiconductor material; nor a third gate structure wrapping over the second end section; a semiconductor liner extending along sidewalls of the fin structure and a top surface of the substrate
De teaches a middle section (PMOS fig. 12) sandwiched between a first end section (left/right NMOS fig. 12) and a second end section (right/left NMOS fig. 12 respective to the first end section) along a direction (left to right of fig. 12) of a fin (comprising at least NMOS and PMOS and P-Substrate fig. 12) the second end section comprise a second semiconductor material (P-well semiconductor material fig. 12 sufficiently illustrated) different from a first semiconductor material (N-Well semiconductor material fig. 12 sufficiently illustrated); and three gates (G fig. 12) wrapped around a channel regions (sufficiently illustrated at the locations of B fig. 12) of the middle section, the first end section and the second end section.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the first end section of Qi in view of the device of De and/or combine the device of Qi with the device of De such that -- wherein the first end section and the second end section sandwiching the middle section along the direction and formed of a second semiconductor material different from the first semiconductor material; and a third gate structure wrapping over the second end section;-- as duplication of parts is prima facie type obviousness [2144.04 VI B.] and/or substituting equivalents known for the same purpose is prima facie type obviousness [See 2144.06] in this case substituting the NMOS and PMOS transistors of De with the NMOS and PMOS transistors of Qi to form the device of De and/or to necessarily form a NFET-PFET Array comprising the device of Qi.
Sung teaches a semiconductor liner (134 and/or 132 fig. 4) extending along sidewalls of a fin structure (F1 and/or F2 fig. 4) and a top surface of a substrate (110 fig. 4)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Qi in view of De in further view of Sung such that “a semiconductor liner extending along sidewalls of the fin structure and a top surface of the substrate”.
A person of ordinary skill in the art would have been motivated to make this modification to improve carrier mobility in the channel/active region [disclosed Paragraph for “stress liner” 0061 Sung] and/or to insulate the fin [disclosed “insulating liner” 0060 Sung].
Claim 14 Qi in view of De and Sung teach as shown above the semiconductor structure of claim 10
wherein the first source/drain feature is in contact with the first end section [illustrated fig. 10 met under broadest reasonable interpretation wherein the left source/drain comprising left 1003 and left 411 contacts the first end section comprising at least 501 fig. 10],
wherein the second source/drain feature is in contact with the second end section [met in view of De and under broadest reasonable interpretation wherein the right source/drain comprising right 1003 and right 411 contacts the first end section comprising at least 501 fig. 10].
Claim 15 Qi in view of De and Sung teach as shown above the semiconductor structure of claim 10, wherein the first end section and the second end section exert a compressive stress (Paragraph 0028 explicitly discloses 505 as “compressive strained SiGe fin”) on the middle section along the direction [Qi disclosed 501 as being a “tensile strained Si” Paragraph 0028 in view of MPEP 2112.01 Qi meets the limitation --the first end section exerts a compressive stress on the middle section along the direction-- under MPEP 2112.01 wherein the structure of a compressively strained/stressed middle section adjacent to a first end section the same as the disclosed and/or claimed structure and/or composition, and the presumed property [under MPEP 2112.01] is that the end section exerts the compressive stress/strain and/or Broadest reasonable interpretation, in view of modification in view of De as shown above --the second end section exert a compressive stress on the middle section along the direction-- is met as well for the same rational as the first end section].
Claims 10 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over US Qi in further view of Di and Sung, as shown in the claims above, and in further view of Nayak.
Claim 11 Qi in view of De and Sung teaches the semiconductor structure of claim 10,
wherein the first semiconductor material comprises silicon (Si) [met as shown in claim 10],
Qi in view of De does not teach wherein the second semiconductor material comprises silicon germanium (SiGe).
Nayak teaches an NMOS and/or NFET device (100 fig. 1) with a section (comprising 120 and 130 fig. 1) in tensile strained silicon germanium material (SiGe fig. 1), wherein the section comprises a buffer layer (120 fig. 1) and a channel layer (130 fig. 1) and that silicon germanium is an art recognized alternative to silicon (sufficiently illustrated fig. 1 “Channel Si or SiGe (tensile)”).
It would have been obvious one of ordinary skill in the art before the effective filing date of the claimed invention to select SiGe materials for the first and second end sections including the buffer layer and the channel layer of Qi in view of De in further view of Nayak such that “the second semiconductor material comprises silicon germanium (SiGe)” as selection of a known material based on its suitability for its intended use is prima facie type obviousness [See MPEP 2144.07] and/or Substituting equivalences known for the same purpose is prima facie type obviousness [in this case materials of NMOS device under tensile strain, See MPEP 2144.06] and/or to enhance the transport of electrons within the device and/or the current drive of the device [See Paragraph 0004 Nayak].
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Qi in view of De and Nayak as shown for the claims above and in further view of US 6607948 B1 Sugiyama et al hereafter “Sugiyama”.
Claim 5 Qi in view of De and Nayak teaches the semiconductor device of claim 1, further comprising: a gate spacer extending along a sidewall of the gate structure [sufficiently disclosed Paragraph 0032 “dummy gate and spacer (not shown for illustrative convenience) are formed by standard methods”].
Qi in view of De and Nayak does not teach a buffer semiconductor layer disposed on top surfaces of the channel region of the middle section, the first end section and the second end section; wherein the gate spacer is disposed on and interfaces a top surface of the buffer semiconductor layer
Sugiyama teaches a buffer semiconductor layer (115 fig. 3) on the top surface of a channel region (114 and 113 fig. 3), wherein the channel region comprises SiGe [Column 6 lines 5-10] and the buffer semiconductor layer comprises Si [ “Si cap layer” Column 6 lines 5-10].
It would have been obvious to one of ordinary skill in the art to modify Qi in view of De such that it includes “a buffer semiconductor layer disposed on top surfaces of the channel region of the middle section, the first end section and the second end section” in further view of Sugiyama to protect the underlying material from being oxidized in the process of manufacturing the transistor [sufficiently disclosed Column 7 lines 1-14 paragraph 30 Sugiyama].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Qi in view of De and Sugiyama such that “the gate spacer is disposed on and interfaces a top surface of the buffer semiconductor layer”.
A person of ordinary skill in the art would have been motivated to make this modification to protect the layers underlying the buffer semiconductor from oxidizing process performed on and/or near the gate spacer [reason for modification is sufficiently disclosed Column 7 lines 1-14 paragraph 30 Sugiyama].
Claim 6 Qi in view of De, Nayak and Sugiyama teach as shown above the semiconductor device of claim 5, wherein the buffer semiconductor layer comprises silicon (Si) [met in view of Sugiyama “Si Cap layer” Column 6 lines 5-10 as shown above].
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Qi in view of De, Nayak, and Sugiyama as shown for the claims above and in further view of Sung.
Claim 7 Qi in view of De and Sugiyama teach the semiconductor device of claim 5, further comprising:
The buffer semiconductor layer is a semiconductor liner [Met under MPEP 2112.01 in --view of Sugiyama wherein the structure is a Si material layer between adjacent layers and the function is lining and/or Broadest reasonable interpretation wherein the buffer layer lines the adjacent layers]
Qi in view of De and Sugiyama as modified above does not teach a semiconductor liner disposed over the buffer semiconductor layer and sidewalls of the channel region of the middle section, the first end section and the second end section.
Sung teaches a semiconductor liner (134 and/or 132 fig. 4) extending along sidewalls of a fin structure (F1 and/or F2 fig. 4) and a top surface of a substrate (110 fig. 4)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Qi in view of De and Sugiyama in further view of Sung such that “a semiconductor liner extending along sidewalls of the fin structure and a top surface of the substrate”.
A person of ordinary skill in the art would have been motivated to make this modification to improve carrier mobility in the channel/active region [disclosed Paragraph for “stress liner” 0061 Sung] and/or to insulate the fin [disclosed “insulating liner” 0060 Sung].
Claim 8 Qi in view of De, Nayak, Sugiyama, and Sung teach as shown above the semiconductor device of claim 7, wherein the semiconductor liner comprises silicon (Si) [met in view of Sugiyama “Si Cap layer” Column 6 lines 5-10 as shown above].
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Qi in view of De and Sung as shown for the claims above and in further view of US 6607948 B1 Sugiyama et al hereafter “Sugiyama”, US 20200035820 A1 Zhang et al hereafter “Zhang”, and US 5963824 A Krivokapic hereafter “Krivokapic”.
Claim 12 Qi in view of De and Sung teaches the semiconductor structure of claim 10,
Qi in view of De and Sung does not Explicitly teach wherein the first gate structure comprises a first gate dielectric layer wrapping over the channel region of the middle section and a first gate electrode wrapping over the first gate dielectric layer,
wherein the second gate structure comprises a second gate dielectric layer wrapping over the first end section and a second gate electrode wrapping over the second gate dielectric layer,
wherein the third gate structure comprises a third gate dielectric layer wrapping over the second end section and a third gate electrode wrapping over the third gate dielectric layer,
wherein a composition of the first gate dielectric layer, a composition of the second gate dielectric layer, and a composition of the third gate dielectric layer are the same,
wherein a composition of the first gate electrode, a composition of the second gate electrode, and a composition of the third gate electrode are the same, wherein the first gate structure is electrically coupled to a gate via over the first gate structure, wherein the second gate structure and the third gate structure are electrically floating.
Sugiyama teaches a gate structure (comprising at least 117 and 116 fig. 3) comprises a gate dielectric layer (116 fig. 3) wrapping over the channel region [sufficiently illustrated fig. 3] and a gate electrode (117 fig. 3) wrapping over the gate dielectric layer [Sufficiently illustrated fig. 3].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the first, second and third gate structures of Qi in view of De in view of the gate structure of Sugiyama such that “the first gate structure comprises a first gate dielectric layer wrapping over the channel region of the middle section and a first gate electrode wrapping over the first gate dielectric layer, wherein the second gate structure comprises a second gate dielectric layer wrapping over the first end section and a second gate electrode wrapping over the second gate dielectric layer, wherein the third gate structure comprises a third gate dielectric layer wrapping over the second end section and a third gate electrode wrapping over the third gate dielectric layer, wherein a composition of the first gate dielectric layer, a composition of the second gate dielectric layer, and a composition of the third gate dielectric layer are the same” as substituting equivalents known of the same purpose is prima facie type obviousness [See MPEP 2144.06 II, in this case gate structure that address a fin type channel region] and/or to necessarily form gate structures for a finFET device.
In view of the above the limitation “wherein a composition of the first gate electrode, a composition of the second gate electrode, and a composition of the third gate electrode are the same” as all three gates comprise the composition of a gate electrode as disclosed by Sugiyama [Si, SiGe or metal such as W disclosed Column 7 lines 40-45]
Zhang teaches a first gate structure (36 fig. 9) is electrically coupled to a gate via (42 fig. 9) over the first gate structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Qi in view of De and Sugiyama in further view of Zhang such that “the first gate structure is electrically coupled to a gate via over the first gate structure”.
A person of ordinary skill in the art would have been motivated to make this modification to electrically address the gate of the transistor from a front end of line and/or the top.
Krivokapic teaches a device comprising a first gate (302 fig. 4), a second gate (300a fig. 4), and a third gate (300b fig. 4), wherein the second gate and third gate are floating gates, and the first gate is addressed [sufficiently illustrated fig. 4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Qi in view of De, Sugiyama and Zhang in further view of Krivokapic such that “the second gate structure and the third gate structure are electrically floating”.
A person of ordinary skill in the art would have been motivated to make this modification to enable an adjustable threshold voltage and/or to form a cell with and adjustable voltage [sufficiently disclosed Column 1 lines 60-65, paragraph 9 Krivokapic].
Claim 13 Qi in view of De, Sung, Zhang, Krivokapic and Sugiyama teach as shown above the semiconductor structure of claim 12
wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer comprise silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, lanthanum oxide, yttrium oxide, or a combination thereof [in view of Sugiyama the embodiment of silicon oxide and/or aluminum oxide, and/or titanium oxide, and/or tantalum Oxide, and/or Zirconium oxide, and/or Hafnium oxide is sufficiently disclosed Column 7 lines 20-35],
wherein the first gate electrode, the second gate electrode, and the third gate electrode comprise titanium nitride, titanium aluminum, titanium aluminum carbide, titanium aluminum nitride, or tungsten [in view of Sugiyama the embodiment of “tungsten” is sufficiently disclosed Column 7 lines 40-45 “metal such as W”].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Qi in view of De and Nayak as shown for the claims above and in further view of US 10950695 B1 Potera et al hereafter “Potera”.
Claim 9 Qi in view of De and Nayak teach as shown above the semiconductor device of claim 1,
Qi in view of De and Nayak does not teach wherein the channel region of the middle section is wavy in a top view.
Potera teaches a MOSFET (10 fig. 1) comprising a channel region (11a and/or 11b) that is wavy in a top view (fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Qi in view of De and Nayak such that “the channel region of the middle section is wavy in a top view” in view of Potera to enable a lower specific on-state resistance and/or support very high voltages in the off-state and/or reduce lateral transistor cell pitch [column 3 lines 25-33 Potera].
Claims 21, and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Qi in view of De, Potera and Sung.
Claim 21 Qi teaches a semiconductor structure, comprising:
a substrate (303 fig. 10) of a first semiconductor material [Silicon paragraph 0027];
a fin structure over the substrate (comprising at least 501, 405, 1001, 505, 411, and 1003 fig. 10), the fin structure comprising:
a middle section (comprising at least 805, 505, 411, and 1003 fig. 10) formed of the first semiconductor material [“compressive strained SiGe” Paragraph 0028 met under broadest reasonable interpretation as the middle section comprises at least the first semiconductor material Si in SiGe (Silicon and germanium)], and
a first end section (comprising 403, 703, 501, 405, and 1001 fig. 10) adjacent the middle section along a direction (left to right of fig. 10) and formed of a second semiconductor material [Tensile strained Si Paragraph 0028] different from the first semiconductor material [met under broadest reasonable interpretation the scope of the embodiment of Si is different than the scope of the embodiment of SiGe];
an isolation feature (comprising 703, 805 and 403 fig. 10) over the substrate, The fin structure rising above the isolation feature[sufficiently illustrated fig. 10 , under broadest reasonable interpretation it is between at least a top portion of the fin and the substrate];
a first gate structure (1007 fig. 10) wrapping over a channel region of the middle section (comprising middle 411 fig. 10);
a second gate structure (1005 fig. 10) wrapping over the first end section; and
a first source/drain feature (comprising left/right 1003 and respective left/right 411 fig. 10 ) and a second source/drain feature (comprising right/left 1003 and right/left 411 fig. 10 respective of the first source/drain feature fig. 10) sandwiching the channel region of the middle section along the direction [sufficiently illustrated fig. 10],
Qi Does not teach a second end section sandwiching the middle section along the direction and formed of the second semiconductor material different from the first semiconductor material; a third gate structure wrapping over the second end section; the channel region of the middle section is wavy when viewed along a vertical direction perpendicular to the direction, nor the fin structure extending through the isolation feature
De teaches a middle section (PMOS fig. 12) sandwiched between a first end section (left/right NMOS fig. 12) and a second end section (right/left NMOS fig. 12 respective to the first end section) along a direction (left to right of fig. 12) of a fin (comprising at least NMOS and PMOS and P-Substrate fig. 12) the second end section comprise a second semiconductor material (P-well semiconductor material fig. 12 sufficiently illustrated) different from a first semiconductor material (N-Well semiconductor material fig. 12 sufficiently illustrated); and three gates (G fig. 12) wrapped around a channel regions (sufficiently illustrated at the locations of B fig. 12) of the middle section, the first end section and the second end section.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to duplicate the first end section of Qi in view of the device of De and/or combine the device of Qi with the device of De such that --a second end section sandwiching the middle section along the direction and formed of the second semiconductor material different from the first semiconductor material; a third gate structure wrapping over the second end section-- as duplication of parts is prima facie type obviousness [2144.04 VI B.] and/or substituting equivalents known for the same purpose is prima facie type obviousness [See 2144.06] in this case substituting the NMOS and PMOS transistors of De with the NMOS and PMOS transistors of Qi to form the device of De and/or to necessarily form a NFET-PFET Array comprising the device of Qi.
Potera teaches a MOSFET (10 fig. 1) comprising a channel region (11a and/or 11b) that is wavy in a top view (fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Qi in view of De such that “the channel region of the middle section is wavy when viewed along a vertical direction perpendicular to the direction” in view of Potera to enable a lower specific on-state resistance and/or support very high voltages in the off-state and/or reduce lateral transistor cell pitch [column 3 lines 25-33 Potera].
Sung teaches a fin structure (F1 and/or F2 fig. 4) extending through an isolation feature (112 fig. 4) and rising above the isolation feature [sufficiently illustrated fig. 4].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify [Qi in view of De in further view of Sung such that “the fin structure extending through the isolation feature and rising above the isolation feature”.
A person of ordinary skill in the art would have been motivated to make this modification to as combining equivalents known for the same purpose is prima facie type obviousness [See MPEP 2144.06]. In this case it is combining isolation structure for the purpose of providing isolation for a finfet comprising a fin and substrate structure.
Claim 23 Qi in view of De, Potera and Sung teach as shown above the semiconductor structure of claim 21, further comprising:
The isolation feature comprises Si [met under broadest reasonable interpretation Paragraph 0027, 403 of the isolation layers comprises Si and 805/703/705 of the isolation feature comprises Silicon oxide fig. 10 ] and is a semiconductor liner [sufficiently illustrated fig. 10 met under broadest reasonable interpretation as it lines the substrate and the fin]
Qi in view of De, Potera, does not teach a semiconductor liner disposed between the lower portion of the fin structure and the isolation feature.
Sung teaches a semiconductor liner comprises (134 and/or 1444 fig. 4) silicon (Si) [disclosed Paragraph 0123 “SiN, SiON, SiBN, SiC, SiC:H, SiCN, SiCN:H, SiOCN, SiOCN:H, SiOC, SiO.sub.2, polysilicon, or a combination thereof” all embodiments comprise silicon] and disposed between the lower portion of the fin structure and the isolation feature.
It would have been obvious to one of ordinary skill in the art to further modify Qi in view of De, Ptera, and Sung, in further view of Sung such that “a semiconductor liner disposed between the lower portion of the fin structure and the isolation feature” to improve carrier mobility in the channel/active region [disclosed Paragraph for “stress liner” 0061 Sung] and/or to insulate the fin [disclosed “insulating liner” 0060 Sung].
Claim 24 Qi in view of De, Potera, and Sung teach as shown above the semiconductor structure of claim 21
wherein the fin structure extends lengthwise along a direction [left to right fig. 10],
wherein a distance between the first end section and the second end section along the direction [met in view of De, there must necessarily be a distance between two different features and in view of De its along the direction (left to right fig. 10) ].
wherein a width of the first end section and the second end section along the direction [not illustrated but necessarily present fig. 10]
Qi in view of De and Potera does not teach the distance between the first end section and the second end section along the direction is between about 100 nm and about 2000 nm,
the width of the first end section and the second end section along the direction is between about 50 nm and about 1000 nm.
It would have been obvious to one of ordinary skill in the art to modify the relative size and/or proportions of the width of middle section and the length of the channels region of the middle section such that “the distance between the first end section and the second end section along the direction is between about 100 nm and about 2000 nm, the width of the first end section and the second end section along the direction is between about 50 nm and about 1000 nm” as relative changes in size and/or proportions is prima facie type obviousness [See MPEP 2144. IV A] and/or as part of routine optimization of conductivity and/ resistance of the channel and/or channel length and/or channel gauge [See 2144.05 II.] which is dependent upon the width of fin sections and the length of the fin section as [illustrated fig. 10 Qi].
Claim 25 Qi in view of De, Sung and Potera teach the semiconductor structure of claim 24, wherein the first end section and the second end section exert a compressive stress (Paragraph 0028 explicitly discloses 505 as “compressive strained SiGe fin”) on the middle section along the direction [Qi disclosed 501 as being a “tensile strained Si” Paragraph 0028 in view of MPEP 2112.01 Qi meets the limitation --the first end section exerts a compressive stress on the middle section along the direction-- under MPEP 2112.01 wherein the structure of a compressively strained/stressed middle section adjacent to a first end section the same as the disclosed and/or claimed structure and/or composition, and the presumed property [under MPEP 2112.01] is that the end section exerts the compressive stress/strain and/or Broadest reasonable interpretation, in view of modification in view of De as shown above --the second end section exert a compressive stress on the middle section along the direction-- is met as well for the same rational as the first end section].
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Qi in view of De Potera, and Sung as shown above in further view of Nayak.
Claim 22 Qi in view of De, Potera, and Sung teach as shown above the semiconductor structure of claim 21 wherein the first semiconductor material comprises silicon (Si) [“SiGe” paragraph 0028 wherein 301 and 303 are the substrate, met under broadest reasonable interpretation as the material SiGe comprises Si].
Qi in view of De and Potera do not teach wherein the second semiconductor material comprises silicon germanium (SiGe).
Nayak teaches an NMOS and/or NFET device (100 fig. 1) with a section (comprising 120 and 130 fig. 1) in tensile strained silicon germanium material (SiGe fig. 1), wherein the section comprises a buffer layer (120 fig. 1) and a channel layer (130 fig. 1) and that silicon germanium is an art recognized alternative to silicon (sufficiently illustrated fig. 1 “Channel Si or SiGe (tensile)”).
It would have been obvious one of ordinary skill in the art before the effective filing date of the claimed invention to select SiGe materials for the first and second end sections including the buffer layer and the channel layer of Qi in view of De and Potera in further view of Nayak such that “the second semiconductor material comprises silicon germanium (SiGe)” as selection of a known material based on its suitability for its intended use is prima facie type obviousness [See MPEP 2144.07] and/or Substituting equivalences known for the same purpose is prima facie type obviousness [in this case materials of NMOS device under tensile strain, See MPEP 2144.06] and/or to enhance the transport of electrons within the device and/or the current drive of the device [See Paragraph 0004 Nayak].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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