DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7, and 13-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20240203879 A1 Xie et al hereafter “Xie”
Claim 1 Xie teaches A semiconductor structure, comprising: first and second active regions (top and bottom 102 fig. 1, illustrated fig. 13 not labeled see annotation below) extending lengthwise along a first direction (perpendicular to cross section BB and CC fig. 1 and 13, hereafter “X”);
metal gate structures (218 fig. 13, labeled fig. 6, 104 fig. 1, see annotation below) over channels of the first and second active regions (210 fig. 13 labeled fig. 2, see annotation below), the metal gate structures extending lengthwise along a second direction (Parallel to cross section BB and CC fig. 13 and 1 hereafter “Y”) perpendicular to the first direction [sufficiently illustrated fig. 13] ;
an insulating structure (214 fig. 13, labeled fig. 2, see annotation below) cutting through the metal gate structures and extending lengthwise along the first direction [sufficiently illustrated fig. 13], wherein the insulating structure is disposed between the first and the second active regions along the second direction [sufficiently illustrated fig. 13];
source/drain (S/D) contacts (comprising 604 and 214 fig. 13, labeled fig. 6) over the insulating structure and over S/D features of the first and second active regions [sufficiently illustrated fig. 13], the S/D contacts extending lengthwise along the second direction [sufficiently illustrated fig. 13]; and
a feedthrough via (1202 fig. 13, labeled fig. 12, see annotation below) contacting a bottom surface of the S/D contacts and penetrating through a portion of the insulating structure [sufficiently illustrated fig. 13],
wherein the insulating structure surrounds the feedthrough via and isolates the feedthrough via from the metal gate structures [sufficiently illustrated fig. 13].
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Xie Annotated fig. 13: explicitly labeling features as matched to the claims
Claim 2 Xie teaches as shown above the semiconductor structure of claim 1, further comprising: an isolation structure (208 fig. 13) separating the first and second active regions along the second direction (sufficiently illustrated fig. 13); and
an interlayer dielectric (ILD) layer [212 fig. 13, labeled fig. 2, see annotation below] over the isolation structure [sufficiently illustrated fig. 13],
wherein the insulating structure cuts through the isolation structure and the ILD layer [sufficiently illustrated fig. 13].
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Xie Annotated fig. 13: highlighting the ILD layer
Claim 3 Xie as shown above the semiconductor structure of claim 3 wherein along the second direction, the insulating structure is in direct contact with and directly between the feedthrough via and the ILD layer [sufficiently illustrated fig. 13 notably cross section BB], and
wherein along the second direction, the insulating structure is in direct contact with and directly between the feedthrough via and the isolation structure [sufficiently illustrated fig. 13 notably cross section BB].
Claim 4 Xie teaches as shown above the semiconductor structure of claim 1, wherein each of the S/D contacts land on top and side surfaces of the S/D features [sufficiently illustrated fig. 13 under broadest reasonable interpretation of “on” which is “used as a function word to indicate position in close proximity with” [Merriam Webster] and the S/D contacts land in close proximity with top and side surfaces of S/D feature].
Claim 7 Xie teaches as shown above the semiconductor structure of claim 1, wherein the insulating structure has a first width [see annotation below] along the second direction, the feedthrough via has a second width [see annotation below] along the second direction, and the first width is greater than the second width [sufficiently illustrated fig. 13].
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Annotated fig. 13 highlighting a first width and a second width
Claim 12 Xie teaches a semiconductor structure, comprising: a first active region (top 102 fig. 1, illustrated fig. 13 but not labeled, see annotation below) having first semiconductor channels (left 210 illustrated fig. 13, labeled fig. 2, see annotation below) and first source/drain (S/D) (left 220 illustrated fig. 13, labeled fig. 2, see annotation below) features adjacent the first semiconductor channels [sufficiently illustrated fig. 13];
a second active region (bottom 102 fig. 1, illustrated fig. 13, see annotation below) having second semiconductor channels (right 210 illustrated fig. 13, labeled fig. 2, see annotation below) and second S/D features (right 220 illustrated fig. 13, labeled fig. 2, see annotation below) adjacent the second semiconductor channels [sufficiently illustrated fig. 13];
an isolation structure (208 illustrated fig. 13, labeled fig. 2, see annotation below) between the first active region and the second active region [sufficiently illustrated fig. 13A-13D];
a metal gate structure (218 illustrated fig. 13, labeled fig. 2, see annotation below, labeled as 104 fig. 1) over the first and second semiconductor channels [sufficiently illustrated fig. 13];
an insulating structure (214 illustrated fig. 13, labeled fig. 2, see annotation below) cutting through the metal gate structure and the isolation structure (sufficiently illustrated fig. 13); and
a feedthrough via (1202 illustrated fig. 13, labeled fig. 12, see annotation below) under the insulating structure [illustrated fig. 13 as measured from the top surfaces under broadest reasonable interpretation, see annotation below], the feedthrough via having a penetrating portion that penetrates through a portion of the insulating structure [sufficiently illustrated fig. 13, the penetrating portion appears to comprise the majority of the feedthrough via], and the insulating structure isolates the penetrating portion of the feedthrough via from the metal gate structure [sufficiently illustrated fig. 13].
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Xie Annotated fig. 13: explicitly labeling features as matched to the claims
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Xie Annotated fig. 13: highlighting the feedthrough via under the insulating structure as measured from the top surfaces.
Claim 13 Xie teaches as shown above the semiconductor structure of claim 12, further comprising: an S/D contact (comprising 604 and 602 illustrated fig. 13, labeled fig. 6, see annotation below) over and in direct contact with the first and second S/D features [sufficiently illustrated fig. 13].
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Xie Annotated fig. 13: highlighting S/D contacts
Claim 14 Xie teaches as shown above the semiconductor structure of claim 13, wherein the feedthrough via is under the S/D contact and in direct contact with the S/D contact [sufficiently illustrated fig. 13].
Claim 15 Xie teaches as shown above the semiconductor structure of claim 13, wherein the S/D contact is disposed along top and side surfaces of the first and second S/D features [sufficiently illustrated fig. 13, met under broadest reasonable interpretation the S/D contacts and extends along the top surfaces of the S/D features and at least a portion of the S/D contact extends between and along the side surfaces of the S/D features.].
Claim 16 Xie teaches as shown above the semiconductor structure of claim 13, wherein the first active region includes third S/D features and the second active region includes fourth S/D features [sufficiently disclosed in view of fig. 1 and 13 wherein cross section AA of fig. 13 represents an identical cross section in both the first active region (top 102 fig. 1) and the second active region (bottom 102 fig. 1), see annotation below], further comprising: a second S/D contact over and in direct contact with the third and fourth S/D features, wherein the feedthrough via is also under the second S/D contact and in direct contact with the second S/D contact [sufficiently disclosed in view of fig. 1 and 13 wherein cross section BB of fig. 13 represents an identical cross sections across perpendicular to the first active region and second active region, see annotation below ].
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Annotated fig. 1: highlighting the relative locations of S/D features and identical BB and AA cross sections.
Claim 17 Xie teaches A method of forming a semiconductor structure, comprising: receiving a workpiece (sufficiently illustrated fig. 1 and fig. 2) having active regions (102 fig. 1, illustrated fig. 2 not labeled, see annotation below) over a substrate (202 fig. 2) and an isolation structure (comprising 208 fig. 2) separating the active regions, the active regions extending lengthwise along a first direction (perpendicular to cross sections BB and CC Fig. 1 and 2 hereafter “X”);
forming metal gate structures (218 fig. 2) over channel regions (210 fig. 2) of the active regions, the metal gate structures extending lengthwise along a second direction (Parallel to cross sections BB and CC fig. 1 and 2 hereafter “Y”) perpendicular to the first direction [sufficiently illustrated fig. 1 and fig. 2];
forming an insulating structure (comprising 216 and 214 fig. 2, and 214 and 402 fig. 4) between two of the active regions, the insulating structure extending lengthwise along the first direction and cuts through multiple metal gate structures [sufficiently illustrated in fig. 2 in view of fig. 1], separating first portions of the metal gate structures from second portions of the metal gate structures [sufficiently illustrated fig. 2 in view of fig. 1];
forming source/drain (S/D) contacts (comprising 604 and 602 fig. 6) over the insulating structure and over S/D regions of the first and second active regions [sufficiently illustrated fig. 6], the S/D contacts extending lengthwise along the second direction [sufficiently illustrated fig. 6]; and
forming a feedthrough via (1202 fig. 12) contacting a bottom surface of the S/D contacts and penetrating through a portion of the insulating structure [sufficiently illustrated fig. 12],
wherein the insulating structure surrounds the feedthrough via and isolates the feedthrough via from the metal gate structures [sufficiently illustrated fig. 12].
Claim 18 Xie teaches as shown above the method of claim 17, wherein the S/D contacts are slot S/D contacts separated from each other by the insulating structure [sufficiently illustrated fig. 13]; and each of the S/D contacts land on multiple S/D features in the S/D regions [sufficiently illustrated fig. 13 in view of fig. 1].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6, 8-11, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie as applied to the claims above.
Claim 5 Xie teaches as shown above the semiconductor structure of claim 1, wherein along the second direction, the insulating structure extends past the feedthrough via [sufficiently illustrated fig. 13].
Xie discloses the insulating structure as “dielectric” paragraph [0034] a dielectric includes the meaning “A substance or medium through or across which electric force acts without conduction; a non-conductor; an insulating medium” [Oxford English Dictionary]
Does not teach the insulating structure extends past the feedthrough via by at least 10 nm on either side of the feedthrough via.
It would have been obvious to one of ordinary skill in the art to modify the insulating structure of Xie such that “the insulating structure extends past the feedthrough via by at least 10 nm on either side of the feedthrough via” as part of routine optimization of the electrical insulation and/or isolation of feedthrough via and adjacent conductive elements enabled by the dielectric material [see MPEP 2144.05 II].
Claim 6 Xie teaches the semiconductor structure of claim 1, wherein along the second direction, the insulating structure extends past the feedthrough via [sufficiently illustrated fig. 13]
Xie discloses the insulating structure as “dielectric” paragraph [0034] a dielectric includes the meaning “A substance or medium through or across which electric force acts without conduction; a non-conductor; an insulating medium” [Oxford English Dictionary]
Xie does not explicitly teach the insulating structure extends past the feedthrough via by at most 20 nm on either side of the feedthrough via.
It would have been obvious to one of ordinary skill in the art to modify the insulating structure of Xie such that “the insulating structure extends past the feedthrough via by at most 20 nm on either side of the feedthrough via” as part of routine optimization of the electrical insulation and/or isolation of feedthrough via and adjacent conductive elements enabled by the dielectric material and the size of the device [see MPEP 2144.05 II].
Claim 8 Xie teaches as shown above the semiconductor structure of claim 7,
Xie does not teach wherein the first width is greater than the second width by at least 20 nm.
Xie discloses the insulating structure as “dielectric” paragraph [0034] a dielectric includes the meaning “A substance or medium through or across which electric force acts without conduction; a non-conductor; an insulating medium” [Oxford English Dictionary]
It would have been obvious to one of ordinary skill in the art to modify the insulating structure of Xie such that “wherein the first width is greater than the second width by at least 20 nm” as part of routine optimization of the electrical insulation and/or isolation of feedthrough via and adjacent conductive elements enabled by the dielectric material and the size of the device [see MPEP 2144.05 II] and/or the resistance of the vias and the areal density of devices on the wafer [Xie Paragraph 0022, see MPEP 2144.05 II]
Claim 9 Xie teaches as shown above the semiconductor structure of claim 7, wherein a spacing (see annotation below, illustrated fig. 13) between the first and second active regions is greater than twice the second width [appear to be met under broadest reasonable interpretation the spacing appears to be at least twice the second width at the bottom of the via as illustrated fig. 13].
Alternatively, should the applicant disagree, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the insulating structure of Xie such that “a between the first and second active regions is greater than twice the second width” as part of routine optimization of the electrical insulation and/or isolation between the feedthrough via and first and second active regions enabled by the dielectric material therebetween and the size of the device [see MPEP 2144.05 II].
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Claim 10 modified Xie teaches as shown above the semiconductor structure of claim 9, wherein
Xie does not explicitly teach the spacing between the first and second active regions is about 100 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the insulating structure of Xie such that “the spacing between the first and second active regions is about 100 nm” as part of routine optimization of the electrical insulation and/or isolation between the feedthrough via and first and second active regions enabled by the dielectric material therebetween and the size of the device [see MPEP 2144.05 II].
Claim 11 modified Xie teaches as shown above the semiconductor structure of claim 10, Xie does not explicitly teach wherein the second width is in a range of 20-50 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modified Xie such that “the second width is in a range of 20-50 nm” as a part of routine optimization of the resistance of the via and the areal density of the device [paragraph 0022 Xie, See MPEP 2144.05 II]
Claim 19 Xie teaches as shown above the method of claim 17, wherein the forming of the feedthrough via further includes: performing an etching process to the insulating structure to form a feedthrough via trench in the insulating structure such that the S/D contacts are exposed within the feedthrough via trench [illustrated fig. 10 and disclosed Paragraph 0047];
depositing a conductive material (1202 fig. 12) in the feedthrough via trench;
performing planarize process to form the top surface of the structure comprising the S/D contacts and the feed through via (604, 602, 214, and 402 fig. 6 sufficiently disclosed paragraph 41-42 “CMP”).
Xie does not explicitly teach performing a planarize process to form the feedthrough via.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use CMP to form the feed through via such that “a planarize process to form the feedthrough via” to remove excess material [sufficiently disclosed paragraph 0042].
Claim 20 modified Xie as shown above teaches the method of claim 17, wherein after forming the feedthrough via, a portion of the insulating structure remains between the feedthrough via and the isolation structure along the second direction [sufficiently illustrated fig. 13].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to William C Trice whose telephone number is (703)756-1875. The examiner can normally be reached M-F 8:30am-5:00pm.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893