Attorney’s Docket Number: 20200350 / 24061.4158US02
Filing Date: 6/15/2023
Claimed Priority Date: 9/30/2020 (US 16/948,745)
3/31/2020 (US 63/002,781)
Inventors: Huang et al.
Examiner: Marcos D. Pizarro
DETAILED ACTION
This Office action responds to the election filed on 11/20/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA (or as subject to pre-AIA ) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
The amendment filed on 11/20/2025 as an election in reply to the restriction in paper no. 3, mailed on 10/1/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-20.
Species Election
Applicant’s election without traverse of the species reading on the transistor in figure 1B, and the methods and cross-sectional views reading on figures 2, 9A and 9B, is acknowledged. The applicants indicated that claims 1-20 read on the elected species. The examiner agrees.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 9, 11 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by You (US 2020/0098922).
Regarding claim 9, You (see, e.g., fig. 10) teaches a method of fabricating a semiconductor device comprising the steps of:
Forming a metal gate via 108 over a metal gate layer 104a, wherein the via has a tapered sidewall profile
Forming sidewall spacers 106/130 on sidewalls of the gate layer, and
Forming a dielectric material 128 interposing the spacers and the via, and at least partially interfacing a top surface of the gate layer
Regarding claim 11, You (see, e.g., figs. 5 and 6) teaches that forming the via comprises:
Etching-back the gate layer 104a and the spacers 106/130
Depositing a metal cap layer 108 over the gate layer and spacers, and
Patterning the cap layer to define the via 108
Regarding claim 13, You (see, e.g., fig. 10) shows that the tapered profile 108 is free of a glue layer.
Regarding claim 14, You (see, e.g., fig. 10) shows that the top surface of the gate layer 104 is recessed with respect to a top surface of the spacers 106/130.
Regarding claim 15, You (see, e.g., fig. 10) shows that the top surface of the spacers 106/130 is recessed with respect to the top surface of the via 108.
Regarding claim 16, You (see, e.g., fig. 5) teaches, prior to forming the via 108, a step of forming an inter-layer dielectric (ILD) 124a adjacent to the gate layer 104, wherein a lateral surface of the ILD interfaces with a lateral surface of the spacers 106/130.
Claims 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie (US 2014/0231885).
Regarding claim 18, Xie (see, e.g., figs. 10-11) teaches a method of fabricating a semiconductor device comprising the steps of:
Etching-back a metal gate structure 78, and
Forming a patterned metal cap layer 90 over the etched-back structure
wherein:
After etching, the top surface of the structure 78 is recessed with respect to the top surface of an adjacent ILD 28
The cap layer 90 has a tapered profile and provides a metal gate via
The top surface of the via is substantially level with the top surface of the ILD 28
The tapered profile 90 is free of a glue layer
Regarding claim 19, Xie (see, e.g., fig. 11) teaches the method further comprising the step of forming a dielectric material 86 on either side of the via 90 and between the via a portion of the ILD 28.
Regarding claim 20, Xie (see, e.g., fig. 9) teaches the method further comprising the step of forming sidewall spacers 36 interposing the etched-back structure 78 and the ILD 28, wherein the top surface of the spacers is recessed with respect to the top surface of the ILD.
Allowable Subject Matter
Claims 1-8 are allowed.
Claims 10, 12 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Papers related to this application may be submitted directly to Art Unit 2814 by facsimile transmission. Papers should be faxed to Art Unit 2814 via the Art Unit 2814 Fax Center. The faxing of such papers must conform to the notice published in the Official Gazette, 1096 OG 30 (15 November 1989). The Art Unit 2814 Fax Center number is (571) 273-8300. The Art Unit 2814 Fax Center is to be used only for papers related to Art Unit 2814 applications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Marcos D. Pizarro at (571) 272-1716 and between the hours of 9:00 AM to 7:00 PM (Eastern Standard Time) Monday through Thursday or by e-mail via Marcos.Pizarro@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/Marcos D. Pizarro/Primary Examiner, Art Unit 2814
MDP/mdp
January 18, 2026